Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T227	7		T228	7		T258	7
all_values[1]	278	1			T227	7		T228	7		T258	7
all_values[2]	278	1			T227	7		T228	7		T258	7
all_values[3]	278	1			T227	7		T228	7		T258	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

592

1

T227

19

T228

18

T258

15

auto[1]

520

1

T227

9

T228

10

T258

13

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

403

1

T227

13

T228

10

T258

8

auto[1]

709

1

T227

15

T228

18

T258

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

646

1

T227

16

T228

17

T258

16

auto[1]

466

1

T227

12

T228

11

T258

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

46

1

T227

2

T228

1

T380

1

all_values[0]

auto[0]

auto[0]

auto[1]

21

1

T228

2

T258

2

T381

1

all_values[0]

auto[0]

auto[1]

auto[0]

66

1

T227

3

T228

1

T258

4

all_values[0]

auto[0]

auto[1]

auto[1]

31

1

T228

1

T264

1

T382

2

all_values[0]

auto[1]

auto[0]

auto[1]

61

1

T227

2

T228

2

T264

1

all_values[0]

auto[1]

auto[1]

auto[1]

53

1

T258

1

T264

2

T382

2

all_values[1]

auto[0]

auto[0]

auto[0]

61

1

T227

2

T228

2

T258

1

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T227

1

T382

1

T383

1

all_values[1]

auto[0]

auto[1]

auto[0]

41

1

T227

1

T228

3

T382

2

all_values[1]

auto[0]

auto[1]

auto[1]

30

1

T227

1

T258

1

T264

1

all_values[1]

auto[1]

auto[0]

auto[1]

71

1

T228

2

T258

1

T264

2

all_values[1]

auto[1]

auto[1]

auto[1]

47

1

T227

2

T258

4

T381

1

all_values[2]

auto[0]

auto[0]

auto[0]

50

1

T227

3

T258

2

T264

1

all_values[2]

auto[0]

auto[0]

auto[1]

37

1

T228

2

T258

4

T381

1

all_values[2]

auto[0]

auto[1]

auto[0]

43

1

T227

1

T264

1

T382

3

all_values[2]

auto[0]

auto[1]

auto[1]

36

1

T228

1

T383

1

T380

1

all_values[2]

auto[1]

auto[0]

auto[1]

62

1

T227

2

T228

1

T258

1

all_values[2]

auto[1]

auto[1]

auto[1]

50

1

T227

1

T228

3

T264

1

all_values[3]

auto[0]

auto[0]

auto[0]

62

1

T227

1

T228

3

T258

1

all_values[3]

auto[0]

auto[0]

auto[1]

27

1

T227

1

T228

1

T258

1

all_values[3]

auto[0]

auto[1]

auto[0]

34

1

T264

1

T382

3

T383

1

all_values[3]

auto[0]

auto[1]

auto[1]

33

1

T381

2

T383

1

T380

1

all_values[3]

auto[1]

auto[0]

auto[1]

66

1

T227

5

T228

2

T258

2

all_values[3]

auto[1]

auto[1]

auto[1]

56

1

T228

1

T258

3

T264

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal