Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	70532	1			T33	77		T328	577		T70	836
accum_cnt_1000	170260	1			T18	1		T31	15		T96	12
accum_cnt_100	18000	1			T49	12		T36	1		T31	37
accum_cnt_50	52606	1			T10	11		T11	34		T16	36
accum_cnt_10	165349	1			T1	2		T2	2		T10	38
accum_cnt_0	316026	1			T1	6		T2	14		T10	31

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	207656	1			T1	2		T2	4		T10	20
class_index[0x1]	207656	1			T1	2		T2	4		T10	20
class_index[0x2]	207656	1			T1	2		T2	4		T10	20
class_index[0x3]	207656	1			T1	2		T2	4		T10	20

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	18369	1			T328	216		T70	229		T300	534
class_index[0x0]	accum_cnt_1000	48141	1			T31	15		T329	16		T86	11
class_index[0x0]	accum_cnt_100	5870	1			T49	12		T36	1		T31	17
class_index[0x0]	accum_cnt_50	13173	1			T11	14		T16	16		T13	10
class_index[0x0]	accum_cnt_10	49746	1			T2	2		T10	15		T28	10
class_index[0x0]	accum_cnt_0	60492	1			T1	2		T2	2		T10	5
class_index[0x1]	accum_cnt_2000	17098	1			T328	361		T70	146		T38	104
class_index[0x1]	accum_cnt_1000	40137	1			T328	358		T70	122		T38	646
class_index[0x1]	accum_cnt_100	3941	1			T58	8		T143	20		T328	24
class_index[0x1]	accum_cnt_50	14518	1			T11	20		T13	10		T36	15
class_index[0x1]	accum_cnt_10	36429	1			T11	6		T13	9		T18	14
class_index[0x1]	accum_cnt_0	85420	1			T1	2		T2	4		T10	20
class_index[0x2]	accum_cnt_2000	16625	1			T33	19		T70	217		T72	182
class_index[0x2]	accum_cnt_1000	41096	1			T96	12		T143	7		T330	27
class_index[0x2]	accum_cnt_100	4319	1			T143	11		T330	21		T86	16
class_index[0x2]	accum_cnt_50	15535	1			T10	10		T17	13		T18	2
class_index[0x2]	accum_cnt_10	42318	1			T1	1		T10	9		T11	26
class_index[0x2]	accum_cnt_0	80599	1			T1	1		T2	4		T10	1
class_index[0x3]	accum_cnt_2000	18440	1			T33	58		T70	244		T72	90
class_index[0x3]	accum_cnt_1000	40886	1			T18	1		T143	11		T99	1
class_index[0x3]	accum_cnt_100	3870	1			T31	20		T58	4		T143	17
class_index[0x3]	accum_cnt_50	9380	1			T10	1		T16	20		T50	4
class_index[0x3]	accum_cnt_10	36856	1			T1	1		T10	14		T11	1
class_index[0x3]	accum_cnt_0	89515	1			T1	1		T2	4		T10	5