Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4535	1			T19	1		T265	1		T42	8
alert[0x1]	4453	1			T46	4		T19	2		T100	3
alert[0x2]	2159	1			T20	1		T331	1		T332	1
alert[0x3]	3815	1			T18	1		T333	1		T51	8
alert[0x4]	8978	1			T107	1		T20	1		T334	2
alert[0x5]	5870	1			T32	8		T47	1		T57	1
alert[0x6]	3614	1			T18	2		T265	1		T259	1
alert[0x7]	10083	1			T57	2		T334	1		T40	35
alert[0x8]	4292	1			T42	1		T333	1		T70	53
alert[0x9]	6522	1			T100	4		T265	2		T334	1
alert[0xa]	2517	1			T18	5		T19	1		T155	1
alert[0xb]	3916	1			T99	2		T265	1		T51	1
alert[0xc]	5425	1			T42	21		T70	8		T91	2
alert[0xd]	3232	1			T96	70		T21	1		T155	1
alert[0xe]	4885	1			T32	14		T20	1		T335	1
alert[0xf]	8258	1			T57	1		T335	1		T333	1
alert[0x10]	11384	1			T155	1		T336	1		T51	1
alert[0x11]	3033	1			T259	2		T334	1		T70	103
alert[0x12]	2331	1			T32	1		T57	77		T70	6
alert[0x13]	2377	1			T265	1		T51	10		T70	102
alert[0x14]	2650	1			T47	9		T19	1		T336	1
alert[0x15]	4856	1			T57	2		T335	1		T70	15
alert[0x16]	4118	1			T19	1		T335	1		T259	12
alert[0x17]	6807	1			T51	1		T70	4		T337	1
alert[0x18]	2544	1			T20	1		T102	1		T334	2
alert[0x19]	7937	1			T94	14		T338	29		T35	128
alert[0x1a]	7633	1			T107	3		T20	1		T100	10
alert[0x1b]	3472	1			T155	1		T333	1		T331	1
alert[0x1c]	5503	1			T21	1		T155	1		T336	1
alert[0x1d]	4820	1			T18	3		T32	2		T155	2
alert[0x1e]	5968	1			T18	1		T46	6		T155	2
alert[0x1f]	5579	1			T19	1		T335	2		T102	1
alert[0x20]	4021	1			T32	2		T335	1		T34	2
alert[0x21]	3603	1			T57	1		T335	1		T334	1
alert[0x22]	4415	1			T32	4		T265	1		T259	2
alert[0x23]	3941	1			T32	1		T265	1		T155	1
alert[0x24]	4722	1			T32	22		T155	1		T336	2
alert[0x25]	3053	1			T335	1		T259	6		T51	3
alert[0x26]	4695	1			T335	1		T334	2		T94	133
alert[0x27]	7776	1			T96	1		T336	1		T70	15
alert[0x28]	3200	1			T18	3		T107	1		T109	2
alert[0x29]	5686	1			T265	1		T336	2		T51	2
alert[0x2a]	7111	1			T18	62		T259	1		T136	22
alert[0x2b]	1530	1			T57	4		T19	1		T99	1
alert[0x2c]	6274	1			T42	1		T335	1		T102	1
alert[0x2d]	3464	1			T70	77		T94	734		T301	2
alert[0x2e]	1823	1			T102	1		T331	1		T334	1
alert[0x2f]	14653	1			T20	1		T100	22		T102	1
alert[0x30]	9394	1			T96	3		T109	6		T21	1
alert[0x31]	3192	1			T100	1		T265	1		T333	1
alert[0x32]	10864	1			T32	8		T19	1		T100	1
alert[0x33]	2202	1			T109	1		T335	1		T51	3
alert[0x34]	12087	1			T32	2		T155	1		T333	2
alert[0x35]	24642	1			T20	1		T51	4		T94	421
alert[0x36]	6457	1			T102	1		T70	13		T94	9
alert[0x37]	10544	1			T57	1		T155	1		T259	1
alert[0x38]	2489	1			T18	13		T155	1		T92	1
alert[0x39]	4437	1			T259	1		T102	2		T70	72
alert[0x3a]	5761	1			T96	1		T57	1		T60	47
alert[0x3b]	3819	1			T155	1		T335	1		T43	1
alert[0x3c]	16184	1			T155	1		T102	1		T333	1
alert[0x3d]	9751	1			T32	5		T57	6		T259	1
alert[0x3e]	3402	1			T265	1		T102	1		T336	1
alert[0x3f]	4037	1			T46	1		T57	1		T333	1
alert[0x40]	4682	1			T60	6		T70	6		T94	2

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	95082	1			T18	1		T32	1		T46	6
class_i[0x1]	82367	1			T18	6		T47	1		T107	2
class_i[0x2]	91380	1			T18	27		T32	5		T46	5
class_i[0x3]	108648	1			T18	56		T32	63		T47	9

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

376768

1

T18

90

T32

69

T47

10

alert_ping_fail

709

1

T19

9

T20

7

T21

4

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4528	1			T42	8		T51	2		T92	4
alert_integrity_fail	alert[0x1]	4438	1			T46	4		T100	3		T259	1
alert_integrity_fail	alert[0x2]	2150	1			T70	37		T72	1119		T74	1
alert_integrity_fail	alert[0x3]	3805	1			T18	1		T51	8		T91	3
alert_integrity_fail	alert[0x4]	8965	1			T107	1		T70	110		T91	4
alert_integrity_fail	alert[0x5]	5850	1			T32	8		T47	1		T57	1
alert_integrity_fail	alert[0x6]	3602	1			T18	2		T259	1		T70	12
alert_integrity_fail	alert[0x7]	10074	1			T57	2		T40	35		T70	310
alert_integrity_fail	alert[0x8]	4278	1			T42	1		T70	53		T94	368
alert_integrity_fail	alert[0x9]	6510	1			T100	4		T72	4		T338	97
alert_integrity_fail	alert[0xa]	2505	1			T18	5		T70	82		T136	2
alert_integrity_fail	alert[0xb]	3907	1			T99	2		T51	1		T70	169
alert_integrity_fail	alert[0xc]	5414	1			T42	21		T70	8		T91	2
alert_integrity_fail	alert[0xd]	3218	1			T96	70		T259	5		T51	1
alert_integrity_fail	alert[0xe]	4875	1			T32	14		T70	63		T72	29
alert_integrity_fail	alert[0xf]	8247	1			T57	1		T92	3		T94	63
alert_integrity_fail	alert[0x10]	11378	1			T51	1		T94	42		T117	5
alert_integrity_fail	alert[0x11]	3025	1			T259	2		T70	103		T94	11
alert_integrity_fail	alert[0x12]	2320	1			T32	1		T57	77		T70	6
alert_integrity_fail	alert[0x13]	2366	1			T51	10		T70	102		T94	130
alert_integrity_fail	alert[0x14]	2640	1			T47	9		T70	47		T94	139
alert_integrity_fail	alert[0x15]	4844	1			T57	2		T70	15		T94	16
alert_integrity_fail	alert[0x16]	4111	1			T259	12		T70	583		T94	40
alert_integrity_fail	alert[0x17]	6801	1			T51	1		T70	4		T145	304
alert_integrity_fail	alert[0x18]	2531	1			T72	197		T74	2		T339	115
alert_integrity_fail	alert[0x19]	7925	1			T94	14		T338	29		T35	128
alert_integrity_fail	alert[0x1a]	7620	1			T107	3		T100	10		T259	1
alert_integrity_fail	alert[0x1b]	3458	1			T94	4		T338	28		T76	13
alert_integrity_fail	alert[0x1c]	5488	1			T70	12		T92	2		T94	29
alert_integrity_fail	alert[0x1d]	4804	1			T18	3		T32	2		T259	46
alert_integrity_fail	alert[0x1e]	5954	1			T18	1		T46	6		T259	1
alert_integrity_fail	alert[0x1f]	5568	1			T70	2486		T94	38		T73	4
alert_integrity_fail	alert[0x20]	4016	1			T32	2		T34	2		T70	24
alert_integrity_fail	alert[0x21]	3593	1			T57	1		T70	38		T72	20
alert_integrity_fail	alert[0x22]	4401	1			T32	4		T259	2		T51	1
alert_integrity_fail	alert[0x23]	3932	1			T32	1		T73	9		T338	1
alert_integrity_fail	alert[0x24]	4714	1			T32	22		T70	19		T142	1
alert_integrity_fail	alert[0x25]	3046	1			T259	6		T51	3		T94	3
alert_integrity_fail	alert[0x26]	4686	1			T94	133		T72	11		T338	1
alert_integrity_fail	alert[0x27]	7767	1			T96	1		T70	15		T94	141
alert_integrity_fail	alert[0x28]	3188	1			T18	3		T107	1		T109	2
alert_integrity_fail	alert[0x29]	5672	1			T51	2		T91	1		T72	472
alert_integrity_fail	alert[0x2a]	7094	1			T18	62		T259	1		T136	22
alert_integrity_fail	alert[0x2b]	1511	1			T57	4		T99	1		T43	1
alert_integrity_fail	alert[0x2c]	6258	1			T42	1		T51	4		T70	52
alert_integrity_fail	alert[0x2d]	3455	1			T70	77		T94	734		T72	6
alert_integrity_fail	alert[0x2e]	1814	1			T94	13		T142	19		T117	6
alert_integrity_fail	alert[0x2f]	14637	1			T100	22		T72	495		T35	35
alert_integrity_fail	alert[0x30]	9376	1			T96	3		T109	6		T70	36
alert_integrity_fail	alert[0x31]	3175	1			T100	1		T72	49		T117	13
alert_integrity_fail	alert[0x32]	10855	1			T32	8		T100	1		T70	43
alert_integrity_fail	alert[0x33]	2191	1			T109	1		T51	3		T117	17
alert_integrity_fail	alert[0x34]	12078	1			T32	2		T94	29		T142	8
alert_integrity_fail	alert[0x35]	24636	1			T51	4		T94	421		T142	8
alert_integrity_fail	alert[0x36]	6447	1			T70	13		T94	9		T38	12
alert_integrity_fail	alert[0x37]	10529	1			T57	1		T259	1		T70	8
alert_integrity_fail	alert[0x38]	2482	1			T18	13		T92	1		T72	156
alert_integrity_fail	alert[0x39]	4430	1			T259	1		T70	72		T91	9
alert_integrity_fail	alert[0x3a]	5752	1			T96	1		T57	1		T60	47
alert_integrity_fail	alert[0x3b]	3808	1			T43	1		T94	501		T72	15
alert_integrity_fail	alert[0x3c]	16176	1			T73	1		T338	1		T35	530
alert_integrity_fail	alert[0x3d]	9746	1			T32	5		T57	6		T259	1
alert_integrity_fail	alert[0x3e]	3393	1			T40	55		T70	19		T338	6
alert_integrity_fail	alert[0x3f]	4033	1			T46	1		T57	1		T92	1
alert_integrity_fail	alert[0x40]	4678	1			T60	6		T70	6		T94	2
alert_ping_fail	alert[0x0]	7	1			T19	1		T265	1		T334	1
alert_ping_fail	alert[0x1]	15	1			T19	2		T335	1		T337	1
alert_ping_fail	alert[0x2]	9	1			T20	1		T331	1		T332	1
alert_ping_fail	alert[0x3]	10	1			T333	1		T332	1		T301	1
alert_ping_fail	alert[0x4]	13	1			T20	1		T334	2		T340	1
alert_ping_fail	alert[0x5]	20	1			T102	1		T333	1		T336	2
alert_ping_fail	alert[0x6]	12	1			T265	1		T102	1		T337	2
alert_ping_fail	alert[0x7]	9	1			T334	1		T301	1		T341	1
alert_ping_fail	alert[0x8]	14	1			T333	1		T342	1		T337	1
alert_ping_fail	alert[0x9]	12	1			T265	2		T334	1		T319	1
alert_ping_fail	alert[0xa]	12	1			T19	1		T155	1		T102	1
alert_ping_fail	alert[0xb]	9	1			T265	1		T342	1		T343	1
alert_ping_fail	alert[0xc]	11	1			T340	1		T342	1		T344	1
alert_ping_fail	alert[0xd]	14	1			T21	1		T155	1		T332	1
alert_ping_fail	alert[0xe]	10	1			T20	1		T335	1		T336	2
alert_ping_fail	alert[0xf]	11	1			T335	1		T333	1		T334	1
alert_ping_fail	alert[0x10]	6	1			T155	1		T336	1		T301	1
alert_ping_fail	alert[0x11]	8	1			T334	1		T343	1		T319	1
alert_ping_fail	alert[0x12]	11	1			T340	2		T337	1		T319	1
alert_ping_fail	alert[0x13]	11	1			T265	1		T342	2		T337	1
alert_ping_fail	alert[0x14]	10	1			T19	1		T336	1		T337	1
alert_ping_fail	alert[0x15]	12	1			T335	1		T345	1		T346	1
alert_ping_fail	alert[0x16]	7	1			T19	1		T335	1		T333	2
alert_ping_fail	alert[0x17]	6	1			T337	1		T346	1		T298	2
alert_ping_fail	alert[0x18]	13	1			T20	1		T102	1		T334	2
alert_ping_fail	alert[0x19]	12	1			T306	1		T347	1		T348	2
alert_ping_fail	alert[0x1a]	13	1			T20	1		T331	1		T332	1
alert_ping_fail	alert[0x1b]	14	1			T155	1		T333	1		T331	1
alert_ping_fail	alert[0x1c]	15	1			T21	1		T155	1		T336	1
alert_ping_fail	alert[0x1d]	16	1			T155	2		T333	1		T326	1
alert_ping_fail	alert[0x1e]	14	1			T155	2		T333	1		T336	1
alert_ping_fail	alert[0x1f]	11	1			T19	1		T335	2		T102	1
alert_ping_fail	alert[0x20]	5	1			T335	1		T343	1		T347	1
alert_ping_fail	alert[0x21]	10	1			T335	1		T334	1		T342	1
alert_ping_fail	alert[0x22]	14	1			T265	1		T344	1		T345	1
alert_ping_fail	alert[0x23]	9	1			T265	1		T155	1		T102	1
alert_ping_fail	alert[0x24]	8	1			T155	1		T336	2		T342	1
alert_ping_fail	alert[0x25]	7	1			T335	1		T331	1		T128	1
alert_ping_fail	alert[0x26]	9	1			T335	1		T334	2		T349	1
alert_ping_fail	alert[0x27]	9	1			T336	1		T337	2		T346	1
alert_ping_fail	alert[0x28]	12	1			T155	1		T335	1		T333	1
alert_ping_fail	alert[0x29]	14	1			T265	1		T336	2		T334	2
alert_ping_fail	alert[0x2a]	17	1			T337	2		T306	1		T345	2
alert_ping_fail	alert[0x2b]	19	1			T19	1		T342	3		T306	1
alert_ping_fail	alert[0x2c]	16	1			T335	1		T102	1		T333	1
alert_ping_fail	alert[0x2d]	9	1			T301	2		T306	1		T343	1
alert_ping_fail	alert[0x2e]	9	1			T102	1		T331	1		T334	1
alert_ping_fail	alert[0x2f]	16	1			T20	1		T102	1		T336	1
alert_ping_fail	alert[0x30]	18	1			T21	1		T336	3		T334	2
alert_ping_fail	alert[0x31]	17	1			T265	1		T333	1		T336	1
alert_ping_fail	alert[0x32]	9	1			T19	1		T21	1		T335	1
alert_ping_fail	alert[0x33]	11	1			T335	1		T331	1		T301	1
alert_ping_fail	alert[0x34]	9	1			T155	1		T333	2		T337	1
alert_ping_fail	alert[0x35]	6	1			T20	1		T346	1		T343	2
alert_ping_fail	alert[0x36]	10	1			T102	1		T337	1		T345	1
alert_ping_fail	alert[0x37]	15	1			T155	1		T331	2		T301	1
alert_ping_fail	alert[0x38]	7	1			T155	1		T342	1		T349	1
alert_ping_fail	alert[0x39]	7	1			T102	2		T347	1		T350	2
alert_ping_fail	alert[0x3a]	9	1			T265	1		T155	1		T332	1
alert_ping_fail	alert[0x3b]	11	1			T155	1		T335	1		T333	1
alert_ping_fail	alert[0x3c]	8	1			T155	1		T102	1		T333	1
alert_ping_fail	alert[0x3d]	5	1			T342	1		T351	1		T352	1
alert_ping_fail	alert[0x3e]	9	1			T265	1		T102	1		T336	1
alert_ping_fail	alert[0x3f]	4	1			T333	1		T345	1		T353	1
alert_ping_fail	alert[0x40]	4	1			T345	1		T354	1		T348	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	94897	1			T18	1		T32	1		T46	6
alert_integrity_fail	class_i[0x1]	82170	1			T18	6		T47	1		T107	2
alert_integrity_fail	class_i[0x2]	91216	1			T18	27		T32	5		T46	5
alert_integrity_fail	class_i[0x3]	108485	1			T18	56		T32	63		T47	9
alert_ping_fail	class_i[0x0]	185	1			T19	9		T20	2		T265	1
alert_ping_fail	class_i[0x1]	197	1			T20	2		T155	17		T335	1
alert_ping_fail	class_i[0x2]	164	1			T20	2		T21	3		T335	2
alert_ping_fail	class_i[0x3]	163	1			T20	1		T21	1		T265	11