Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	68657	1			T14	430		T30	78		T18	7
class_i[0x1]	33313	1			T17	8		T14	608		T19	8
class_i[0x2]	38455	1			T17	3		T43	86		T73	5
class_i[0x3]	59724	1			T40	2919		T51	6		T248	4

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	49116	1			T17	4		T14	653		T40	3
alert[0x1]	51132	1			T17	3		T14	22		T40	1873
alert[0x2]	51366	1			T17	4		T14	331		T40	1024
alert[0x3]	48535	1			T14	32		T40	19		T51	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

199867

1

T17

8

T14

1038

T40

2919

esc_ping_fail

282

1

T17

3

T18

6

T19

8

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	49035	1			T17	3		T14	653		T40	3
esc_integrity_fail	alert[0x1]	51060	1			T17	2		T14	22		T40	1873
esc_integrity_fail	alert[0x2]	51295	1			T17	3		T14	331		T40	1024
esc_integrity_fail	alert[0x3]	48477	1			T14	32		T40	19		T51	1
esc_ping_fail	alert[0x0]	81	1			T17	1		T18	3		T19	2
esc_ping_fail	alert[0x1]	72	1			T17	1		T19	2		T241	1
esc_ping_fail	alert[0x2]	71	1			T17	1		T18	3		T19	1
esc_ping_fail	alert[0x3]	58	1			T19	3		T241	1		T116	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	68576	1			T14	430		T30	78		T18	2
esc_integrity_fail	class_i[0x1]	33252	1			T17	8		T14	608		T54	1
esc_integrity_fail	class_i[0x2]	38364	1			T43	86		T73	5		T244	13
esc_integrity_fail	class_i[0x3]	59675	1			T40	2919		T51	6		T248	4
esc_ping_fail	class_i[0x0]	81	1			T18	5		T241	4		T258	5
esc_ping_fail	class_i[0x1]	61	1			T19	8		T241	1		T77	9
esc_ping_fail	class_i[0x2]	91	1			T17	3		T18	1		T336	4
esc_ping_fail	class_i[0x3]	49	1			T116	6		T353	1		T340	9