Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	555259424	0	0	617
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	555259424	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	555259424	555076380	0	0
tb.dut.CheckAccuCntDw	0	0	617	617	0	0
tb.dut.CheckEscCntDw	0	0	617	617	0	0
tb.dut.CheckNAlerts	0	0	617	617	0	0
tb.dut.CheckNClasses	0	0	617	617	0	0
tb.dut.CheckNEscSev	0	0	617	617	0	0
tb.dut.CrashdumpKnownO_A	0	0	555259424	555076380	0	0
tb.dut.EdnKnownO_A	0	0	555259424	555076380	0	0
tb.dut.EscPKnownO_A	0	0	555259424	555076380	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	555259424	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	555259424	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	555259424	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	555259424	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	555259424	90	0	0
tb.dut.IrqAKnownO_A	0	0	555259424	555076380	0	0
tb.dut.IrqBKnownO_A	0	0	555259424	555076380	0	0
tb.dut.IrqCKnownO_A	0	0	555259424	555076380	0	0
tb.dut.IrqDKnownO_A	0	0	555259424	555076380	0	0
tb.dut.TlAReadyKnownO_A	0	0	555259424	555076380	0	0
tb.dut.TlDValidKnownO_A	0	0	555259424	555076380	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	582163207	174451	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	582163207	9342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	582163207	8965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	582163207	9235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	582163207	8526	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	582163207	8999	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	582163207	8603	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	582163207	8852	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	582163207	8384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	582163207	8745	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	582163207	8375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	582163207	9970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	582163207	8978	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	582163207	8654	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	582163207	9057	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	582163207	8235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	582163207	8246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	582163207	8659	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	582163207	8387	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	582163207	8343	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	582163207	8902	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	582163207	8593	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	582163207	8556	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	582163207	9776	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	582163207	9389	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	582163207	9212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	582163207	9261	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	582163207	9277	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	582163207	8635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	582163207	8922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	582163207	8450	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	582163207	9042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	582163207	9814	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	582163207	9015	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	582163207	8894	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	582163207	9231	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	582163207	9226	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	582163207	9339	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	582163207	8864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	582163207	8840	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	582163207	8616	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	582163207	9137	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	582163207	8967	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	582163207	9396	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	582163207	8890	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	582163207	9361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	582163207	8330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	582163207	8954	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	582163207	8381	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	582163207	9600	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	582163207	9214	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	582163207	8922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	582163207	9311	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	582163207	8480	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	582163207	8650	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	582163207	8327	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	582163207	8684	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	582163207	9155	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	582163207	8645	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	582163207	8330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	582163207	9809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	582163207	9714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	582163207	9196	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	582163207	9223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	582163207	8345	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	582163207	8570	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	582163207	8369	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	582163207	8312	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	582163207	8407	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	582163207	8533	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	582163207	13693	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	582163207	8793	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	582163207	8387	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	582163207	9171	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	582163207	8533	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	582163207	8895	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	582163207	8797	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	582163207	8676	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	582163207	9169	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	555259424	3211	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	555259424	181498	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	555259424	266300915	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	555259424	276	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	555259424	698	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	555259424	33	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	555259424	299	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	554926211	195299963	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	555259424	770	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	555259424	758	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	555259424	745	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	555259424	730	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	555259424	791	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	555259424	85763	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	555259424	693	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	555259424	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	555259424	1466	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	555259424	1196	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	554924711	554857027	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	555259424	555076380	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	555259424	823	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	555259424	181031	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	555259424	291492604	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	555259424	316	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	555259424	439	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	555259424	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	555259424	186	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	554926211	220013227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	555259424	490	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	555259424	479	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	555259424	474	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	555259424	470	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	555259424	404	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	555259424	57652	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	555259424	334	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	555259424	43	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	555259424	1461	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	555259424	1191	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	554924711	554857027	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	555259424	555076380	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	555259424	3952	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	555259424	150745	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	555259424	324385167	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	555259424	220	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	555259424	398	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	555259424	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	555259424	147	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	554926211	255740889	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	555259424	451	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	555259424	442	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	555259424	434	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	555259424	424	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	555259424	439	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	555259424	61328	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	555259424	374	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	555259424	47	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	555259424	1443	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	555259424	1173	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	554924711	554857027	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	555259424	555076380	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	555259424	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	555259424	6324	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	555259424	170383	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	555259424	300072126	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	555259424	295	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	555259424	463	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	555259424	15	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	555259424	192	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	554926211	235456991	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	555259424	515	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	555259424	502	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	555259424	489	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	555259424	476	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	555259424	366	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	555259424	54061	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	555259424	304	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	555259424	44	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	555259424	1473	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	555259424	1203	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	554924711	554857027	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	617	617	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	555259424	555076380	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	582163207	80792374	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	582163207	581461330	0	0
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tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	822	822	0	0
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tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	822	822	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	822	822	0	0

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