Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	165	1			T13	1		T92	1		T293	1
index[0x1]	133	1			T2	1		T11	1		T13	2
index[0x2]	131	1			T29	1		T48	1		T53	1
index[0x3]	177	1			T11	1		T25	1		T29	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	189	1			T11	1		T13	3		T53	1
lens_less_than_1000[1]	114	1			T2	1		T11	1		T29	1
lens_less_than_1000[2]	90	1			T48	1		T293	1		T30	1
lens_less_than_1000[3]	92	1			T29	1		T242	1		T54	1
lens_less_than_1000[4]	34	1			T25	1		T88	1		T89	1
lens_less_than_1000[5]	27	1			T72	1		T39	1		T122	1
lens_less_than_1000[6]	16	1			T122	1		T65	2		T67	1
lens_less_than_1000[7]	13	1			T246	1		T294	1		T295	1
lens_less_than_1000[8]	8	1			T296	1		T144	1		T137	1
lens_less_than_1000[9]	3	1			T297	1		T67	1		T146	1
len_2	20	1			T298	1		T57	16		T64	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[8]]	0	1	1
[index[0x2]]	[lens_less_than_1000[9] , len_2]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	57	1			T13	1		T30	1		T38	7
index[0x0]	lens_less_than_1000[1]	39	1			T92	1		T31	1		T88	1
index[0x0]	lens_less_than_1000[2]	21	1			T293	1		T299	1		T33	2
index[0x0]	lens_less_than_1000[3]	20	1			T256	1		T106	1		T122	1
index[0x0]	lens_less_than_1000[4]	5	1			T59	1		T270	1		T300	2
index[0x0]	lens_less_than_1000[5]	9	1			T39	1		T122	1		T60	1
index[0x0]	lens_less_than_1000[6]	4	1			T65	1		T146	1		T301	2
index[0x0]	lens_less_than_1000[7]	5	1			T295	1		T302	1		T268	1
index[0x0]	lens_less_than_1000[8]	2	1			T137	1		T70	1		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T297	1		-	-		-	-
index[0x0]	len_2	2	1			T298	1		T303	1		-	-
index[0x1]	lens_less_than_1000[0]	51	1			T11	1		T13	2		T43	1
index[0x1]	lens_less_than_1000[1]	20	1			T2	1		T51	1		T122	1
index[0x1]	lens_less_than_1000[2]	15	1			T43	1		T33	1		T54	1
index[0x1]	lens_less_than_1000[3]	20	1			T256	1		T122	1		T304	1
index[0x1]	lens_less_than_1000[4]	8	1			T34	1		T305	1		T306	1
index[0x1]	lens_less_than_1000[5]	4	1			T72	1		T267	1		T307	1
index[0x1]	lens_less_than_1000[6]	2	1			T122	1		T308	1		-	-
index[0x1]	lens_less_than_1000[7]	3	1			T294	1		T140	1		T309	1
index[0x1]	lens_less_than_1000[9]	1	1			T146	1		-	-		-	-
index[0x1]	len_2	9	1			T57	8		T310	1		-	-
index[0x2]	lens_less_than_1000[0]	32	1			T53	1		T54	1		T89	2
index[0x2]	lens_less_than_1000[1]	28	1			T56	1		T311	1		T62	1
index[0x2]	lens_less_than_1000[2]	21	1			T48	1		T312	1		T134	1
index[0x2]	lens_less_than_1000[3]	24	1			T29	1		T242	1		T54	1
index[0x2]	lens_less_than_1000[4]	13	1			T313	1		T314	1		T62	1
index[0x2]	lens_less_than_1000[5]	8	1			T42	1		T63	1		T315	1
index[0x2]	lens_less_than_1000[6]	1	1			T65	1		-	-		-	-
index[0x2]	lens_less_than_1000[7]	3	1			T138	1		T64	1		T114	1
index[0x2]	lens_less_than_1000[8]	1	1			T296	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	49	1			T73	1		T89	3		T245	1
index[0x3]	lens_less_than_1000[1]	27	1			T11	1		T29	1		T54	1
index[0x3]	lens_less_than_1000[2]	33	1			T30	1		T33	1		T241	1
index[0x3]	lens_less_than_1000[3]	28	1			T122	1		T316	1		T317	2
index[0x3]	lens_less_than_1000[4]	8	1			T25	1		T88	1		T89	1
index[0x3]	lens_less_than_1000[5]	6	1			T318	1		T305	1		T270	1
index[0x3]	lens_less_than_1000[6]	9	1			T67	1		T319	4		T320	1
index[0x3]	lens_less_than_1000[7]	2	1			T246	1		T277	1		-	-
index[0x3]	lens_less_than_1000[8]	5	1			T144	1		T267	2		T321	1
index[0x3]	lens_less_than_1000[9]	1	1			T67	1		-	-		-	-
index[0x3]	len_2	9	1			T57	8		T64	1		-	-