Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.89	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	6	34	85.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	6	34	85.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T1	1		T73	1		T38	8
class_index[0x1]	43	1			T14	1		T40	1		T43	1
class_index[0x2]	47	1			T30	1		T43	1		T73	1
class_index[0x3]	44	1			T1	1		T92	1		T51	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	71	1			T1	1		T33	1		T54	2
intr_timeout_cnt[1]	51	1			T1	1		T92	1		T40	1
intr_timeout_cnt[2]	20	1			T51	1		T90	1		T56	1
intr_timeout_cnt[3]	12	1			T43	1		T56	1		T266	2
intr_timeout_cnt[4]	13	1			T43	1		T73	1		T88	1
intr_timeout_cnt[5]	8	1			T73	1		T97	1		T55	1
intr_timeout_cnt[6]	3	1			T30	1		T146	1		T268	1
intr_timeout_cnt[7]	5	1			T14	1		T30	2		T269	1
intr_timeout_cnt[8]	9	1			T43	1		T270	2		T264	1
intr_timeout_cnt[9]	4	1			T81	1		T271	1		T272	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	6	34	85.00	6

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6] , intr_timeout_cnt[7]]	--	--	2
[class_index[0x1]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	19	1			T1	1		T33	1		T54	1
class_index[0x0]	intr_timeout_cnt[1]	22	1			T38	8		T100	1		T144	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T273	1		T274	1		T275	1
class_index[0x0]	intr_timeout_cnt[3]	7	1			T266	1		T276	1		T145	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T73	1		T268	1		T277	1
class_index[0x0]	intr_timeout_cnt[5]	4	1			T55	1		T278	1		T137	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T270	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T268	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	14	1			T279	1		T280	1		T65	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T40	1		T39	1		T54	1
class_index[0x1]	intr_timeout_cnt[2]	3	1			T56	1		T281	1		T274	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T56	1		T272	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T88	1		T266	1		T249	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T97	1		T282	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T14	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T43	1		T101	1		T114	1
class_index[0x1]	intr_timeout_cnt[9]	3	1			T81	1		T271	1		T272	1
class_index[0x2]	intr_timeout_cnt[0]	23	1			T54	1		T36	5		T34	1
class_index[0x2]	intr_timeout_cnt[1]	6	1			T144	1		T283	1		T284	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T285	1		T286	1		T287	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T266	1		T269	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T43	1		T62	1		T271	1
class_index[0x2]	intr_timeout_cnt[5]	2	1			T73	1		T147	1		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T146	1		T268	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T30	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	4	1			T270	1		T264	1		T288	1
class_index[0x3]	intr_timeout_cnt[0]	15	1			T81	1		T289	1		T61	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T1	1		T92	1		T98	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T51	1		T90	1		T123	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T43	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	3	1			T122	1		T146	1		T290	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T30	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T30	1		T269	1		T291	1
class_index[0x3]	intr_timeout_cnt[8]	1	1			T292	1		-	-		-	-