Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290781	1			T1	9		T2	23		T10	8
all_values[1]	290781	1			T1	9		T2	23		T10	8
all_values[2]	290781	1			T1	9		T2	23		T10	8
all_values[3]	290781	1			T1	9		T2	23		T10	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577977

1

T1

14

T2

53

T10

15

auto[1]

585147

1

T1

22

T2

39

T10

17

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

694527

1

T1

20

T2

83

T10

7

auto[1]

468597

1

T1

16

T2

9

T10

25

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	84580	1			T1	1		T2	10		T11	4
all_values[0]	auto[0]	auto[1]	59690	1			T1	1		T2	5		T10	2
all_values[0]	auto[1]	auto[0]	86499	1			T1	4		T2	4		T10	2
all_values[0]	auto[1]	auto[1]	60012	1			T1	3		T2	4		T10	4
all_values[1]	auto[0]	auto[0]	87061	1			T1	3		T2	9		T10	1
all_values[1]	auto[0]	auto[1]	57237	1			T1	2		T10	4		T11	8
all_values[1]	auto[1]	auto[0]	88607	1			T1	2		T2	14		T10	1
all_values[1]	auto[1]	auto[1]	57876	1			T1	2		T10	2		T11	6
all_values[2]	auto[0]	auto[0]	85328	1			T1	2		T2	15		T11	6
all_values[2]	auto[0]	auto[1]	59445	1			T1	2		T10	2		T11	6
all_values[2]	auto[1]	auto[0]	86476	1			T1	3		T2	8		T10	1
all_values[2]	auto[1]	auto[1]	59532	1			T1	2		T10	5		T11	8
all_values[3]	auto[0]	auto[0]	87190	1			T1	2		T2	14		T10	2
all_values[3]	auto[0]	auto[1]	57446	1			T1	1		T10	4		T11	5
all_values[3]	auto[1]	auto[0]	88786	1			T1	3		T2	9		T11	8
all_values[3]	auto[1]	auto[1]	57359	1			T1	3		T10	2		T11	8