Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	290781	1			T1	9		T2	23		T10	8
all_pins[1]	290781	1			T1	9		T2	23		T10	8
all_pins[2]	290781	1			T1	9		T2	23		T10	8
all_pins[3]	290781	1			T1	9		T2	23		T10	8

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	928345	1			T1	26		T2	88		T10	19
values[0x1]	234779	1			T1	10		T2	4		T10	13
transitions[0x0=>0x1]	155326	1			T1	6		T2	4		T10	6
transitions[0x1=>0x0]	155563	1			T1	6		T2	4		T10	7

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	230769	1			T1	6		T2	19		T10	4
all_pins[0]	values[0x1]	60012	1			T1	3		T2	4		T10	4
all_pins[0]	transitions[0x0=>0x1]	59462	1			T1	3		T2	4		T10	2
all_pins[0]	transitions[0x1=>0x0]	57046	1			T1	3		T10	1		T11	8
all_pins[1]	values[0x0]	232905	1			T1	7		T2	23		T10	6
all_pins[1]	values[0x1]	57876	1			T1	2		T10	2		T11	6
all_pins[1]	transitions[0x0=>0x1]	31860	1			T11	2		T16	1		T25	2
all_pins[1]	transitions[0x1=>0x0]	33996	1			T1	1		T2	4		T10	2
all_pins[2]	values[0x0]	231249	1			T1	7		T2	23		T10	3
all_pins[2]	values[0x1]	59532	1			T1	2		T10	5		T11	8
all_pins[2]	transitions[0x0=>0x1]	33048	1			T1	1		T10	3		T11	6
all_pins[2]	transitions[0x1=>0x0]	31392	1			T1	1		T11	4		T25	2
all_pins[3]	values[0x0]	233422	1			T1	6		T2	23		T10	6
all_pins[3]	values[0x1]	57359	1			T1	3		T10	2		T11	8
all_pins[3]	transitions[0x0=>0x1]	30956	1			T1	2		T10	1		T11	4
all_pins[3]	transitions[0x1=>0x0]	33129	1			T1	1		T10	4		T11	4