Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	260	1			T211	7		T212	4		T243	4
all_values[1]	260	1			T211	7		T212	4		T243	4
all_values[2]	260	1			T211	7		T212	4		T243	4
all_values[3]	260	1			T211	7		T212	4		T243	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

579

1

T211

13

T212

9

T243

10

auto[1]

461

1

T211

15

T212

7

T243

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

361

1

T211

6

T212

11

T243

5

auto[1]

679

1

T211

22

T212

5

T243

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T211

12

T212

13

T243

10

auto[1]

444

1

T211

16

T212

3

T243

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

34

1

T211

1

T243

2

T263

1

all_values[0]

auto[0]

auto[0]

auto[1]

39

1

T212

1

T397

1

T398

1

all_values[0]

auto[0]

auto[1]

auto[0]

38

1

T211

1

T212

2

T397

1

all_values[0]

auto[0]

auto[1]

auto[1]

29

1

T211

2

T263

2

T399

1

all_values[0]

auto[1]

auto[0]

auto[1]

70

1

T212

1

T243

2

T263

1

all_values[0]

auto[1]

auto[1]

auto[1]

50

1

T211

3

T263

3

T399

2

all_values[1]

auto[0]

auto[0]

auto[0]

56

1

T211

3

T212

1

T243

2

all_values[1]

auto[0]

auto[0]

auto[1]

30

1

T211

1

T212

1

T263

1

all_values[1]

auto[0]

auto[1]

auto[0]

36

1

T397

1

T400

1

T401

2

all_values[1]

auto[0]

auto[1]

auto[1]

28

1

T243

1

T399

1

T398

1

all_values[1]

auto[1]

auto[0]

auto[1]

58

1

T211

2

T263

2

T399

1

all_values[1]

auto[1]

auto[1]

auto[1]

52

1

T211

1

T212

2

T243

1

all_values[2]

auto[0]

auto[0]

auto[0]

59

1

T212

3

T243

1

T263

1

all_values[2]

auto[0]

auto[0]

auto[1]

20

1

T211

1

T397

1

T402

2

all_values[2]

auto[0]

auto[1]

auto[0]

41

1

T212

1

T263

2

T399

3

all_values[2]

auto[0]

auto[1]

auto[1]

34

1

T243

1

T403

1

T398

1

all_values[2]

auto[1]

auto[0]

auto[1]

61

1

T211

4

T243

1

T263

2

all_values[2]

auto[1]

auto[1]

auto[1]

45

1

T211

2

T243

1

T263

2

all_values[3]

auto[0]

auto[0]

auto[0]

61

1

T212

2

T263

2

T399

1

all_values[3]

auto[0]

auto[0]

auto[1]

29

1

T243

1

T399

2

T397

1

all_values[3]

auto[0]

auto[1]

auto[0]

36

1

T211

1

T212

2

T263

3

all_values[3]

auto[0]

auto[1]

auto[1]

26

1

T211

2

T243

2

T397

2

all_values[3]

auto[1]

auto[0]

auto[1]

62

1

T211

1

T243

1

T263

2

all_values[3]

auto[1]

auto[1]

auto[1]

46

1

T211

3

T397

1

T398

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal