Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	84238	1			T40	17		T102	301		T245	122
accum_cnt_1000	183568	1			T14	2		T52	65		T331	3
accum_cnt_100	21652	1			T26	10		T96	3		T52	44
accum_cnt_50	56147	1			T1	4		T11	23		T24	1
accum_cnt_10	148232	1			T1	24		T2	18		T10	19
accum_cnt_0	328125	1			T1	4		T2	58		T10	21

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	215911	1			T1	8		T2	19		T10	10
class_index[0x1]	215911	1			T1	8		T2	19		T10	10
class_index[0x2]	215911	1			T1	8		T2	19		T10	10
class_index[0x3]	215911	1			T1	8		T2	19		T10	10

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	21504	1			T102	301		T124	106		T332	520
class_index[0x0]	accum_cnt_1000	48521	1			T331	3		T43	33		T244	8
class_index[0x0]	accum_cnt_100	7204	1			T26	10		T96	3		T331	11
class_index[0x0]	accum_cnt_50	13825	1			T1	2		T24	1		T25	7
class_index[0x0]	accum_cnt_10	40287	1			T1	4		T2	18		T10	10
class_index[0x0]	accum_cnt_0	71722	1			T1	2		T2	1		T16	4
class_index[0x1]	accum_cnt_2000	23447	1			T245	14		T333	178		T334	435
class_index[0x1]	accum_cnt_1000	49973	1			T14	2		T52	39		T136	30
class_index[0x1]	accum_cnt_100	5562	1			T52	19		T43	14		T136	25
class_index[0x1]	accum_cnt_50	18587	1			T11	7		T13	10		T14	12
class_index[0x1]	accum_cnt_10	32211	1			T1	8		T11	14		T13	6
class_index[0x1]	accum_cnt_0	75808	1			T2	19		T10	10		T11	1
class_index[0x2]	accum_cnt_2000	19473	1			T245	108		T334	550		T134	528
class_index[0x2]	accum_cnt_1000	39984	1			T43	24		T54	37		T117	49
class_index[0x2]	accum_cnt_100	4446	1			T43	20		T142	6		T54	13
class_index[0x2]	accum_cnt_50	12014	1			T1	2		T11	16		T25	5
class_index[0x2]	accum_cnt_10	34638	1			T1	6		T10	9		T11	6
class_index[0x2]	accum_cnt_0	96867	1			T2	19		T10	1		T16	4
class_index[0x3]	accum_cnt_2000	19814	1			T40	17		T334	488		T332	589
class_index[0x3]	accum_cnt_1000	45090	1			T52	26		T43	4		T54	52
class_index[0x3]	accum_cnt_100	4440	1			T52	25		T43	24		T142	5
class_index[0x3]	accum_cnt_50	11721	1			T13	6		T92	20		T14	12
class_index[0x3]	accum_cnt_10	41096	1			T1	6		T16	2		T25	12
class_index[0x3]	accum_cnt_0	83728	1			T1	2		T2	19		T10	10