Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	1124	1			T30	2		T54	5		T335	12
alert[0x1]	5054	1			T40	1		T55	1		T77	1
alert[0x2]	4503	1			T241	1		T336	1		T55	47
alert[0x3]	3443	1			T258	1		T337	1		T338	2
alert[0x4]	3353	1			T54	1		T97	22		T338	1
alert[0x5]	6601	1			T40	1		T54	2		T89	1
alert[0x6]	5107	1			T13	3		T18	1		T54	54
alert[0x7]	2894	1			T10	2		T241	1		T337	1
alert[0x8]	2692	1			T10	21		T40	4		T51	1
alert[0x9]	3368	1			T19	1		T88	4		T89	9
alert[0xa]	5499	1			T19	1		T55	1		T339	1
alert[0xb]	5163	1			T55	2		T337	1		T122	2
alert[0xc]	3124	1			T30	2		T241	1		T54	213
alert[0xd]	10345	1			T30	13		T19	1		T54	1
alert[0xe]	1339	1			T335	4		T104	10		T311	375
alert[0xf]	5566	1			T13	1		T19	2		T85	1
alert[0x10]	3829	1			T73	57		T54	10		T116	1
alert[0x11]	6433	1			T13	131		T17	1		T30	1
alert[0x12]	4622	1			T10	5		T89	1		T90	106
alert[0x13]	3556	1			T54	11		T89	21		T90	1
alert[0x14]	12147	1			T13	4		T54	4		T97	16
alert[0x15]	6167	1			T116	1		T77	1		T151	6
alert[0x16]	4665	1			T13	2		T73	1		T18	1
alert[0x17]	6877	1			T73	3		T116	1		T81	1
alert[0x18]	3937	1			T51	8		T54	165		T116	1
alert[0x19]	3506	1			T13	2		T241	1		T336	1
alert[0x1a]	7569	1			T30	1		T18	1		T19	1
alert[0x1b]	2491	1			T19	1		T54	31		T258	1
alert[0x1c]	1698	1			T13	3		T73	1		T336	1
alert[0x1d]	4504	1			T13	7		T30	4		T19	1
alert[0x1e]	1176	1			T13	5		T40	11		T43	5
alert[0x1f]	2230	1			T40	17		T241	1		T54	11
alert[0x20]	5259	1			T40	14		T97	2		T258	1
alert[0x21]	1912	1			T40	2		T55	5		T340	1
alert[0x22]	2014	1			T89	20		T81	1		T85	1
alert[0x23]	2468	1			T40	4		T30	13		T19	1
alert[0x24]	6256	1			T55	6		T81	2		T56	4
alert[0x25]	2867	1			T18	1		T33	1		T54	3
alert[0x26]	4322	1			T19	1		T337	1		T313	9
alert[0x27]	3525	1			T13	12		T73	1		T89	3
alert[0x28]	5669	1			T13	2		T51	2		T73	8
alert[0x29]	7304	1			T10	1		T89	12		T341	1
alert[0x2a]	1454	1			T241	1		T54	3		T97	61
alert[0x2b]	2572	1			T40	2		T19	1		T54	1
alert[0x2c]	2649	1			T336	1		T55	3		T77	1
alert[0x2d]	2955	1			T54	50		T336	1		T89	2
alert[0x2e]	3227	1			T17	1		T40	16		T340	1
alert[0x2f]	5249	1			T97	1		T89	6		T77	1
alert[0x30]	7322	1			T40	1		T336	1		T77	1
alert[0x31]	2112	1			T13	3		T17	1		T40	2
alert[0x32]	3027	1			T97	8		T342	1		T311	1
alert[0x33]	3021	1			T55	3		T56	1		T104	62
alert[0x34]	2794	1			T116	2		T55	4		T81	2
alert[0x35]	2630	1			T18	1		T77	1		T56	5
alert[0x36]	4404	1			T13	1		T18	1		T19	1
alert[0x37]	4077	1			T341	1		T338	1		T340	1
alert[0x38]	4554	1			T30	4		T258	1		T336	1
alert[0x39]	2543	1			T19	1		T241	1		T337	1
alert[0x3a]	2471	1			T40	3		T18	1		T89	2
alert[0x3b]	7095	1			T13	7		T54	38		T336	1
alert[0x3c]	7494	1			T13	1		T18	1		T54	8
alert[0x3d]	2904	1			T13	1		T30	2		T18	1
alert[0x3e]	2926	1			T30	33		T73	2		T19	1
alert[0x3f]	3399	1			T51	1		T245	19		T56	3
alert[0x40]	3508	1			T30	5		T54	8		T341	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	66609	1			T17	3		T40	78		T30	46
class_i[0x1]	57187	1			T18	2		T19	13		T241	8
class_i[0x2]	55965	1			T10	29		T51	4		T30	34
class_i[0x3]	90804	1			T13	185		T51	8		T73	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

269877

1

T10

29

T13

185

T40

78

alert_ping_fail

688

1

T17

3

T18

10

T19

15

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	1114	1			T30	2		T54	5		T335	12
alert_integrity_fail	alert[0x1]	5048	1			T40	1		T55	1		T56	7
alert_integrity_fail	alert[0x2]	4497	1			T55	47		T56	20		T343	1
alert_integrity_fail	alert[0x3]	3432	1			T313	2		T344	20		T104	20
alert_integrity_fail	alert[0x4]	3346	1			T54	1		T97	22		T344	7
alert_integrity_fail	alert[0x5]	6589	1			T40	1		T54	2		T89	1
alert_integrity_fail	alert[0x6]	5099	1			T13	3		T54	54		T89	1
alert_integrity_fail	alert[0x7]	2887	1			T10	2		T245	7		T151	3
alert_integrity_fail	alert[0x8]	2685	1			T10	21		T40	4		T51	1
alert_integrity_fail	alert[0x9]	3357	1			T88	4		T89	9		T313	16
alert_integrity_fail	alert[0xa]	5486	1			T55	1		T339	1		T281	1
alert_integrity_fail	alert[0xb]	5147	1			T55	2		T122	2		T313	145
alert_integrity_fail	alert[0xc]	3114	1			T30	2		T54	213		T335	60
alert_integrity_fail	alert[0xd]	10336	1			T30	13		T54	1		T343	3
alert_integrity_fail	alert[0xe]	1330	1			T335	4		T104	10		T311	375
alert_integrity_fail	alert[0xf]	5553	1			T13	1		T151	1		T313	12
alert_integrity_fail	alert[0x10]	3821	1			T73	57		T54	10		T122	2
alert_integrity_fail	alert[0x11]	6423	1			T13	131		T30	1		T97	1
alert_integrity_fail	alert[0x12]	4607	1			T10	5		T89	1		T90	106
alert_integrity_fail	alert[0x13]	3540	1			T54	11		T89	21		T90	1
alert_integrity_fail	alert[0x14]	12136	1			T13	4		T54	4		T97	16
alert_integrity_fail	alert[0x15]	6148	1			T151	6		T345	1		T339	1
alert_integrity_fail	alert[0x16]	4655	1			T13	2		T73	1		T54	1
alert_integrity_fail	alert[0x17]	6868	1			T73	3		T81	1		T245	2
alert_integrity_fail	alert[0x18]	3931	1			T51	8		T54	165		T344	41
alert_integrity_fail	alert[0x19]	3497	1			T13	2		T313	477		T344	15
alert_integrity_fail	alert[0x1a]	7552	1			T30	1		T81	3		T56	40
alert_integrity_fail	alert[0x1b]	2475	1			T54	31		T313	177		T344	100
alert_integrity_fail	alert[0x1c]	1686	1			T13	3		T73	1		T89	3
alert_integrity_fail	alert[0x1d]	4489	1			T13	7		T30	4		T89	7
alert_integrity_fail	alert[0x1e]	1167	1			T13	5		T40	11		T43	5
alert_integrity_fail	alert[0x1f]	2208	1			T40	17		T54	11		T55	2
alert_integrity_fail	alert[0x20]	5243	1			T40	14		T97	2		T104	92
alert_integrity_fail	alert[0x21]	1905	1			T40	2		T55	5		T344	304
alert_integrity_fail	alert[0x22]	2005	1			T89	20		T81	1		T122	46
alert_integrity_fail	alert[0x23]	2458	1			T40	4		T30	13		T54	65
alert_integrity_fail	alert[0x24]	6248	1			T55	6		T81	2		T56	4
alert_integrity_fail	alert[0x25]	2853	1			T33	1		T54	3		T56	35
alert_integrity_fail	alert[0x26]	4313	1			T313	9		T314	2		T344	42
alert_integrity_fail	alert[0x27]	3515	1			T13	12		T73	1		T89	3
alert_integrity_fail	alert[0x28]	5656	1			T13	2		T51	2		T73	8
alert_integrity_fail	alert[0x29]	7299	1			T10	1		T89	12		T104	72
alert_integrity_fail	alert[0x2a]	1440	1			T54	3		T97	61		T89	1
alert_integrity_fail	alert[0x2b]	2557	1			T40	2		T54	1		T81	3
alert_integrity_fail	alert[0x2c]	2634	1			T55	3		T344	134		T104	16
alert_integrity_fail	alert[0x2d]	2938	1			T54	50		T89	2		T343	1
alert_integrity_fail	alert[0x2e]	3216	1			T40	16		T313	190		T314	5
alert_integrity_fail	alert[0x2f]	5242	1			T97	1		T89	6		T344	76
alert_integrity_fail	alert[0x30]	7315	1			T40	1		T81	4		T56	4
alert_integrity_fail	alert[0x31]	2106	1			T13	3		T40	2		T54	1
alert_integrity_fail	alert[0x32]	3017	1			T97	8		T311	1		T62	35
alert_integrity_fail	alert[0x33]	3011	1			T55	3		T56	1		T104	62
alert_integrity_fail	alert[0x34]	2781	1			T55	4		T81	2		T313	143
alert_integrity_fail	alert[0x35]	2621	1			T56	5		T313	33		T344	307
alert_integrity_fail	alert[0x36]	4396	1			T13	1		T81	2		T343	12
alert_integrity_fail	alert[0x37]	4070	1			T313	9		T344	69		T104	24
alert_integrity_fail	alert[0x38]	4542	1			T30	4		T89	1		T61	5
alert_integrity_fail	alert[0x39]	2529	1			T246	2		T56	20		T61	1
alert_integrity_fail	alert[0x3a]	2467	1			T40	3		T89	2		T55	4
alert_integrity_fail	alert[0x3b]	7086	1			T13	7		T54	38		T55	5
alert_integrity_fail	alert[0x3c]	7479	1			T13	1		T54	8		T56	10
alert_integrity_fail	alert[0x3d]	2896	1			T13	1		T30	2		T54	3
alert_integrity_fail	alert[0x3e]	2917	1			T30	33		T73	2		T55	1
alert_integrity_fail	alert[0x3f]	3396	1			T51	1		T245	19		T56	3
alert_integrity_fail	alert[0x40]	3503	1			T30	5		T54	8		T313	19
alert_ping_fail	alert[0x0]	10	1			T346	1		T347	1		T348	3
alert_ping_fail	alert[0x1]	6	1			T77	1		T349	1		T350	1
alert_ping_fail	alert[0x2]	6	1			T241	1		T336	1		T85	1
alert_ping_fail	alert[0x3]	11	1			T258	1		T337	1		T338	2
alert_ping_fail	alert[0x4]	7	1			T338	1		T342	1		T340	1
alert_ping_fail	alert[0x5]	12	1			T77	1		T351	1		T352	1
alert_ping_fail	alert[0x6]	8	1			T18	1		T77	1		T85	1
alert_ping_fail	alert[0x7]	7	1			T241	1		T337	1		T322	1
alert_ping_fail	alert[0x8]	7	1			T18	1		T241	1		T341	1
alert_ping_fail	alert[0x9]	11	1			T19	1		T341	2		T353	1
alert_ping_fail	alert[0xa]	13	1			T19	1		T354	1		T328	1
alert_ping_fail	alert[0xb]	16	1			T337	1		T341	1		T354	1
alert_ping_fail	alert[0xc]	10	1			T241	1		T258	1		T77	1
alert_ping_fail	alert[0xd]	9	1			T19	1		T116	1		T258	1
alert_ping_fail	alert[0xe]	9	1			T352	2		T355	1		T356	1
alert_ping_fail	alert[0xf]	13	1			T19	2		T85	1		T341	1
alert_ping_fail	alert[0x10]	8	1			T116	1		T258	1		T337	1
alert_ping_fail	alert[0x11]	10	1			T17	1		T77	1		T338	1
alert_ping_fail	alert[0x12]	15	1			T77	3		T337	1		T340	1
alert_ping_fail	alert[0x13]	16	1			T322	2		T357	1		T346	1
alert_ping_fail	alert[0x14]	11	1			T323	1		T340	1		T354	1
alert_ping_fail	alert[0x15]	19	1			T116	1		T77	1		T338	1
alert_ping_fail	alert[0x16]	10	1			T18	1		T116	1		T337	1
alert_ping_fail	alert[0x17]	9	1			T116	1		T338	2		T351	1
alert_ping_fail	alert[0x18]	6	1			T116	1		T85	1		T354	1
alert_ping_fail	alert[0x19]	9	1			T241	1		T336	1		T358	2
alert_ping_fail	alert[0x1a]	17	1			T18	1		T19	1		T258	1
alert_ping_fail	alert[0x1b]	16	1			T19	1		T258	1		T85	1
alert_ping_fail	alert[0x1c]	12	1			T336	1		T337	1		T338	1
alert_ping_fail	alert[0x1d]	15	1			T19	1		T337	1		T342	1
alert_ping_fail	alert[0x1e]	9	1			T19	1		T336	1		T355	1
alert_ping_fail	alert[0x1f]	22	1			T241	1		T116	1		T337	1
alert_ping_fail	alert[0x20]	16	1			T258	1		T342	1		T325	1
alert_ping_fail	alert[0x21]	7	1			T340	1		T359	1		T360	1
alert_ping_fail	alert[0x22]	9	1			T85	1		T338	1		T330	1
alert_ping_fail	alert[0x23]	10	1			T19	1		T336	1		T351	1
alert_ping_fail	alert[0x24]	8	1			T353	1		T128	1		T348	1
alert_ping_fail	alert[0x25]	14	1			T18	1		T336	1		T77	2
alert_ping_fail	alert[0x26]	9	1			T19	1		T337	1		T351	1
alert_ping_fail	alert[0x27]	10	1			T341	1		T348	1		T356	1
alert_ping_fail	alert[0x28]	13	1			T116	1		T85	1		T337	1
alert_ping_fail	alert[0x29]	5	1			T341	1		T358	1		T361	1
alert_ping_fail	alert[0x2a]	14	1			T241	1		T354	1		T362	1
alert_ping_fail	alert[0x2b]	15	1			T19	1		T258	1		T337	1
alert_ping_fail	alert[0x2c]	15	1			T336	1		T77	1		T341	1
alert_ping_fail	alert[0x2d]	17	1			T336	1		T85	1		T338	1
alert_ping_fail	alert[0x2e]	11	1			T17	1		T340	1		T363	1
alert_ping_fail	alert[0x2f]	7	1			T77	1		T85	1		T337	1
alert_ping_fail	alert[0x30]	7	1			T336	1		T77	1		T364	1
alert_ping_fail	alert[0x31]	6	1			T17	1		T116	1		T365	1
alert_ping_fail	alert[0x32]	10	1			T342	1		T356	2		T366	1
alert_ping_fail	alert[0x33]	10	1			T358	1		T355	1		T365	1
alert_ping_fail	alert[0x34]	13	1			T116	2		T354	2		T364	1
alert_ping_fail	alert[0x35]	9	1			T18	1		T77	1		T341	1
alert_ping_fail	alert[0x36]	8	1			T18	1		T19	1		T340	1
alert_ping_fail	alert[0x37]	7	1			T341	1		T338	1		T340	1
alert_ping_fail	alert[0x38]	12	1			T258	1		T336	1		T77	1
alert_ping_fail	alert[0x39]	14	1			T19	1		T241	1		T337	1
alert_ping_fail	alert[0x3a]	4	1			T18	1		T85	1		T364	1
alert_ping_fail	alert[0x3b]	9	1			T336	1		T337	1		T340	2
alert_ping_fail	alert[0x3c]	15	1			T18	1		T116	1		T77	1
alert_ping_fail	alert[0x3d]	8	1			T18	1		T241	1		T116	1
alert_ping_fail	alert[0x3e]	9	1			T19	1		T116	1		T352	1
alert_ping_fail	alert[0x3f]	3	1			T355	1		T360	1		T367	1
alert_ping_fail	alert[0x40]	5	1			T341	1		T340	1		T366	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	66424	1			T40	78		T30	46		T43	5
alert_integrity_fail	class_i[0x1]	56993	1			T97	1		T89	112		T245	28
alert_integrity_fail	class_i[0x2]	55817	1			T10	29		T51	4		T30	34
alert_integrity_fail	class_i[0x3]	90643	1			T13	185		T51	8		T73	2
alert_ping_fail	class_i[0x0]	185	1			T17	3		T18	7		T116	12
alert_ping_fail	class_i[0x1]	194	1			T18	2		T19	13		T241	8
alert_ping_fail	class_i[0x2]	148	1			T18	1		T19	1		T241	1
alert_ping_fail	class_i[0x3]	161	1			T19	1		T116	2		T336	11