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71 always_ff @(posedge clk_i or negedge rst_ni) begin
72 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
73 1/1 err_q <= '0;
Tests: T1 T2 T3
74 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
75 1/1 err_q <= 1'b1;
Tests: T7 T8 T9
76 end
MISSING_ELSE
77 end
78
79 // integrity error output is permanent and should be used for alert generation
80 // register errors are transactional
81 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
82
83 // outgoing integrity generation
84 tlul_pkg::tl_d2h_t tl_o_pre;
85 tlul_rsp_intg_gen #(
86 .EnableRspIntgGen(1),
87 .EnableDataIntgGen(1)
88 ) u_rsp_intg_gen (
89 .tl_i(tl_o_pre),
90 .tl_o(tl_o)
91 );
92
93 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
94 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
95
96 tlul_adapter_reg #(
97 .RegAw(AW),
98 .RegDw(DW),
99 .EnableDataIntgGen(0)
100 ) u_reg_if (
101 .clk_i (clk_i),
102 .rst_ni (rst_ni),
103
104 .tl_i (tl_reg_h2d),
105 .tl_o (tl_reg_d2h),
106
107 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
108 .intg_error_o(),
109
110 .we_o (reg_we),
111 .re_o (reg_re),
112 .addr_o (reg_addr),
113 .wdata_o (reg_wdata),
114 .be_o (reg_be),
115 .busy_i (reg_busy),
116 .rdata_i (reg_rdata),
117 .error_i (reg_error)
118 );
119
120 // cdc oversampling signals
121
122 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
123 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T37 T43 T33
124
125 // Define SW related signals
126 // Format: <reg>_<field>_{wd|we|qs}
127 // or <reg>_{wd|we|qs} if field == 1 or 0
128 logic intr_state_we;
129 logic intr_state_classa_qs;
130 logic intr_state_classa_wd;
131 logic intr_state_classb_qs;
132 logic intr_state_classb_wd;
133 logic intr_state_classc_qs;
134 logic intr_state_classc_wd;
135 logic intr_state_classd_qs;
136 logic intr_state_classd_wd;
137 logic intr_enable_we;
138 logic intr_enable_classa_qs;
139 logic intr_enable_classa_wd;
140 logic intr_enable_classb_qs;
141 logic intr_enable_classb_wd;
142 logic intr_enable_classc_qs;
143 logic intr_enable_classc_wd;
144 logic intr_enable_classd_qs;
145 logic intr_enable_classd_wd;
146 logic intr_test_we;
147 logic intr_test_classa_wd;
148 logic intr_test_classb_wd;
149 logic intr_test_classc_wd;
150 logic intr_test_classd_wd;
151 logic ping_timer_regwen_we;
152 logic ping_timer_regwen_qs;
153 logic ping_timer_regwen_wd;
154 logic ping_timeout_cyc_shadowed_re;
155 logic ping_timeout_cyc_shadowed_we;
156 logic [15:0] ping_timeout_cyc_shadowed_qs;
157 logic [15:0] ping_timeout_cyc_shadowed_wd;
158 logic ping_timeout_cyc_shadowed_storage_err;
159 logic ping_timeout_cyc_shadowed_update_err;
160 logic ping_timer_en_shadowed_re;
161 logic ping_timer_en_shadowed_we;
162 logic ping_timer_en_shadowed_qs;
163 logic ping_timer_en_shadowed_wd;
164 logic ping_timer_en_shadowed_storage_err;
165 logic ping_timer_en_shadowed_update_err;
166 logic alert_regwen_0_we;
167 logic alert_regwen_0_qs;
168 logic alert_regwen_0_wd;
169 logic alert_regwen_1_we;
170 logic alert_regwen_1_qs;
171 logic alert_regwen_1_wd;
172 logic alert_regwen_2_we;
173 logic alert_regwen_2_qs;
174 logic alert_regwen_2_wd;
175 logic alert_regwen_3_we;
176 logic alert_regwen_3_qs;
177 logic alert_regwen_3_wd;
178 logic alert_regwen_4_we;
179 logic alert_regwen_4_qs;
180 logic alert_regwen_4_wd;
181 logic alert_regwen_5_we;
182 logic alert_regwen_5_qs;
183 logic alert_regwen_5_wd;
184 logic alert_regwen_6_we;
185 logic alert_regwen_6_qs;
186 logic alert_regwen_6_wd;
187 logic alert_regwen_7_we;
188 logic alert_regwen_7_qs;
189 logic alert_regwen_7_wd;
190 logic alert_regwen_8_we;
191 logic alert_regwen_8_qs;
192 logic alert_regwen_8_wd;
193 logic alert_regwen_9_we;
194 logic alert_regwen_9_qs;
195 logic alert_regwen_9_wd;
196 logic alert_regwen_10_we;
197 logic alert_regwen_10_qs;
198 logic alert_regwen_10_wd;
199 logic alert_regwen_11_we;
200 logic alert_regwen_11_qs;
201 logic alert_regwen_11_wd;
202 logic alert_regwen_12_we;
203 logic alert_regwen_12_qs;
204 logic alert_regwen_12_wd;
205 logic alert_regwen_13_we;
206 logic alert_regwen_13_qs;
207 logic alert_regwen_13_wd;
208 logic alert_regwen_14_we;
209 logic alert_regwen_14_qs;
210 logic alert_regwen_14_wd;
211 logic alert_regwen_15_we;
212 logic alert_regwen_15_qs;
213 logic alert_regwen_15_wd;
214 logic alert_regwen_16_we;
215 logic alert_regwen_16_qs;
216 logic alert_regwen_16_wd;
217 logic alert_regwen_17_we;
218 logic alert_regwen_17_qs;
219 logic alert_regwen_17_wd;
220 logic alert_regwen_18_we;
221 logic alert_regwen_18_qs;
222 logic alert_regwen_18_wd;
223 logic alert_regwen_19_we;
224 logic alert_regwen_19_qs;
225 logic alert_regwen_19_wd;
226 logic alert_regwen_20_we;
227 logic alert_regwen_20_qs;
228 logic alert_regwen_20_wd;
229 logic alert_regwen_21_we;
230 logic alert_regwen_21_qs;
231 logic alert_regwen_21_wd;
232 logic alert_regwen_22_we;
233 logic alert_regwen_22_qs;
234 logic alert_regwen_22_wd;
235 logic alert_regwen_23_we;
236 logic alert_regwen_23_qs;
237 logic alert_regwen_23_wd;
238 logic alert_regwen_24_we;
239 logic alert_regwen_24_qs;
240 logic alert_regwen_24_wd;
241 logic alert_regwen_25_we;
242 logic alert_regwen_25_qs;
243 logic alert_regwen_25_wd;
244 logic alert_regwen_26_we;
245 logic alert_regwen_26_qs;
246 logic alert_regwen_26_wd;
247 logic alert_regwen_27_we;
248 logic alert_regwen_27_qs;
249 logic alert_regwen_27_wd;
250 logic alert_regwen_28_we;
251 logic alert_regwen_28_qs;
252 logic alert_regwen_28_wd;
253 logic alert_regwen_29_we;
254 logic alert_regwen_29_qs;
255 logic alert_regwen_29_wd;
256 logic alert_regwen_30_we;
257 logic alert_regwen_30_qs;
258 logic alert_regwen_30_wd;
259 logic alert_regwen_31_we;
260 logic alert_regwen_31_qs;
261 logic alert_regwen_31_wd;
262 logic alert_regwen_32_we;
263 logic alert_regwen_32_qs;
264 logic alert_regwen_32_wd;
265 logic alert_regwen_33_we;
266 logic alert_regwen_33_qs;
267 logic alert_regwen_33_wd;
268 logic alert_regwen_34_we;
269 logic alert_regwen_34_qs;
270 logic alert_regwen_34_wd;
271 logic alert_regwen_35_we;
272 logic alert_regwen_35_qs;
273 logic alert_regwen_35_wd;
274 logic alert_regwen_36_we;
275 logic alert_regwen_36_qs;
276 logic alert_regwen_36_wd;
277 logic alert_regwen_37_we;
278 logic alert_regwen_37_qs;
279 logic alert_regwen_37_wd;
280 logic alert_regwen_38_we;
281 logic alert_regwen_38_qs;
282 logic alert_regwen_38_wd;
283 logic alert_regwen_39_we;
284 logic alert_regwen_39_qs;
285 logic alert_regwen_39_wd;
286 logic alert_regwen_40_we;
287 logic alert_regwen_40_qs;
288 logic alert_regwen_40_wd;
289 logic alert_regwen_41_we;
290 logic alert_regwen_41_qs;
291 logic alert_regwen_41_wd;
292 logic alert_regwen_42_we;
293 logic alert_regwen_42_qs;
294 logic alert_regwen_42_wd;
295 logic alert_regwen_43_we;
296 logic alert_regwen_43_qs;
297 logic alert_regwen_43_wd;
298 logic alert_regwen_44_we;
299 logic alert_regwen_44_qs;
300 logic alert_regwen_44_wd;
301 logic alert_regwen_45_we;
302 logic alert_regwen_45_qs;
303 logic alert_regwen_45_wd;
304 logic alert_regwen_46_we;
305 logic alert_regwen_46_qs;
306 logic alert_regwen_46_wd;
307 logic alert_regwen_47_we;
308 logic alert_regwen_47_qs;
309 logic alert_regwen_47_wd;
310 logic alert_regwen_48_we;
311 logic alert_regwen_48_qs;
312 logic alert_regwen_48_wd;
313 logic alert_regwen_49_we;
314 logic alert_regwen_49_qs;
315 logic alert_regwen_49_wd;
316 logic alert_regwen_50_we;
317 logic alert_regwen_50_qs;
318 logic alert_regwen_50_wd;
319 logic alert_regwen_51_we;
320 logic alert_regwen_51_qs;
321 logic alert_regwen_51_wd;
322 logic alert_regwen_52_we;
323 logic alert_regwen_52_qs;
324 logic alert_regwen_52_wd;
325 logic alert_regwen_53_we;
326 logic alert_regwen_53_qs;
327 logic alert_regwen_53_wd;
328 logic alert_regwen_54_we;
329 logic alert_regwen_54_qs;
330 logic alert_regwen_54_wd;
331 logic alert_regwen_55_we;
332 logic alert_regwen_55_qs;
333 logic alert_regwen_55_wd;
334 logic alert_regwen_56_we;
335 logic alert_regwen_56_qs;
336 logic alert_regwen_56_wd;
337 logic alert_regwen_57_we;
338 logic alert_regwen_57_qs;
339 logic alert_regwen_57_wd;
340 logic alert_regwen_58_we;
341 logic alert_regwen_58_qs;
342 logic alert_regwen_58_wd;
343 logic alert_regwen_59_we;
344 logic alert_regwen_59_qs;
345 logic alert_regwen_59_wd;
346 logic alert_regwen_60_we;
347 logic alert_regwen_60_qs;
348 logic alert_regwen_60_wd;
349 logic alert_regwen_61_we;
350 logic alert_regwen_61_qs;
351 logic alert_regwen_61_wd;
352 logic alert_regwen_62_we;
353 logic alert_regwen_62_qs;
354 logic alert_regwen_62_wd;
355 logic alert_regwen_63_we;
356 logic alert_regwen_63_qs;
357 logic alert_regwen_63_wd;
358 logic alert_regwen_64_we;
359 logic alert_regwen_64_qs;
360 logic alert_regwen_64_wd;
361 logic alert_en_shadowed_0_re;
362 logic alert_en_shadowed_0_we;
363 logic alert_en_shadowed_0_qs;
364 logic alert_en_shadowed_0_wd;
365 logic alert_en_shadowed_0_storage_err;
366 logic alert_en_shadowed_0_update_err;
367 logic alert_en_shadowed_1_re;
368 logic alert_en_shadowed_1_we;
369 logic alert_en_shadowed_1_qs;
370 logic alert_en_shadowed_1_wd;
371 logic alert_en_shadowed_1_storage_err;
372 logic alert_en_shadowed_1_update_err;
373 logic alert_en_shadowed_2_re;
374 logic alert_en_shadowed_2_we;
375 logic alert_en_shadowed_2_qs;
376 logic alert_en_shadowed_2_wd;
377 logic alert_en_shadowed_2_storage_err;
378 logic alert_en_shadowed_2_update_err;
379 logic alert_en_shadowed_3_re;
380 logic alert_en_shadowed_3_we;
381 logic alert_en_shadowed_3_qs;
382 logic alert_en_shadowed_3_wd;
383 logic alert_en_shadowed_3_storage_err;
384 logic alert_en_shadowed_3_update_err;
385 logic alert_en_shadowed_4_re;
386 logic alert_en_shadowed_4_we;
387 logic alert_en_shadowed_4_qs;
388 logic alert_en_shadowed_4_wd;
389 logic alert_en_shadowed_4_storage_err;
390 logic alert_en_shadowed_4_update_err;
391 logic alert_en_shadowed_5_re;
392 logic alert_en_shadowed_5_we;
393 logic alert_en_shadowed_5_qs;
394 logic alert_en_shadowed_5_wd;
395 logic alert_en_shadowed_5_storage_err;
396 logic alert_en_shadowed_5_update_err;
397 logic alert_en_shadowed_6_re;
398 logic alert_en_shadowed_6_we;
399 logic alert_en_shadowed_6_qs;
400 logic alert_en_shadowed_6_wd;
401 logic alert_en_shadowed_6_storage_err;
402 logic alert_en_shadowed_6_update_err;
403 logic alert_en_shadowed_7_re;
404 logic alert_en_shadowed_7_we;
405 logic alert_en_shadowed_7_qs;
406 logic alert_en_shadowed_7_wd;
407 logic alert_en_shadowed_7_storage_err;
408 logic alert_en_shadowed_7_update_err;
409 logic alert_en_shadowed_8_re;
410 logic alert_en_shadowed_8_we;
411 logic alert_en_shadowed_8_qs;
412 logic alert_en_shadowed_8_wd;
413 logic alert_en_shadowed_8_storage_err;
414 logic alert_en_shadowed_8_update_err;
415 logic alert_en_shadowed_9_re;
416 logic alert_en_shadowed_9_we;
417 logic alert_en_shadowed_9_qs;
418 logic alert_en_shadowed_9_wd;
419 logic alert_en_shadowed_9_storage_err;
420 logic alert_en_shadowed_9_update_err;
421 logic alert_en_shadowed_10_re;
422 logic alert_en_shadowed_10_we;
423 logic alert_en_shadowed_10_qs;
424 logic alert_en_shadowed_10_wd;
425 logic alert_en_shadowed_10_storage_err;
426 logic alert_en_shadowed_10_update_err;
427 logic alert_en_shadowed_11_re;
428 logic alert_en_shadowed_11_we;
429 logic alert_en_shadowed_11_qs;
430 logic alert_en_shadowed_11_wd;
431 logic alert_en_shadowed_11_storage_err;
432 logic alert_en_shadowed_11_update_err;
433 logic alert_en_shadowed_12_re;
434 logic alert_en_shadowed_12_we;
435 logic alert_en_shadowed_12_qs;
436 logic alert_en_shadowed_12_wd;
437 logic alert_en_shadowed_12_storage_err;
438 logic alert_en_shadowed_12_update_err;
439 logic alert_en_shadowed_13_re;
440 logic alert_en_shadowed_13_we;
441 logic alert_en_shadowed_13_qs;
442 logic alert_en_shadowed_13_wd;
443 logic alert_en_shadowed_13_storage_err;
444 logic alert_en_shadowed_13_update_err;
445 logic alert_en_shadowed_14_re;
446 logic alert_en_shadowed_14_we;
447 logic alert_en_shadowed_14_qs;
448 logic alert_en_shadowed_14_wd;
449 logic alert_en_shadowed_14_storage_err;
450 logic alert_en_shadowed_14_update_err;
451 logic alert_en_shadowed_15_re;
452 logic alert_en_shadowed_15_we;
453 logic alert_en_shadowed_15_qs;
454 logic alert_en_shadowed_15_wd;
455 logic alert_en_shadowed_15_storage_err;
456 logic alert_en_shadowed_15_update_err;
457 logic alert_en_shadowed_16_re;
458 logic alert_en_shadowed_16_we;
459 logic alert_en_shadowed_16_qs;
460 logic alert_en_shadowed_16_wd;
461 logic alert_en_shadowed_16_storage_err;
462 logic alert_en_shadowed_16_update_err;
463 logic alert_en_shadowed_17_re;
464 logic alert_en_shadowed_17_we;
465 logic alert_en_shadowed_17_qs;
466 logic alert_en_shadowed_17_wd;
467 logic alert_en_shadowed_17_storage_err;
468 logic alert_en_shadowed_17_update_err;
469 logic alert_en_shadowed_18_re;
470 logic alert_en_shadowed_18_we;
471 logic alert_en_shadowed_18_qs;
472 logic alert_en_shadowed_18_wd;
473 logic alert_en_shadowed_18_storage_err;
474 logic alert_en_shadowed_18_update_err;
475 logic alert_en_shadowed_19_re;
476 logic alert_en_shadowed_19_we;
477 logic alert_en_shadowed_19_qs;
478 logic alert_en_shadowed_19_wd;
479 logic alert_en_shadowed_19_storage_err;
480 logic alert_en_shadowed_19_update_err;
481 logic alert_en_shadowed_20_re;
482 logic alert_en_shadowed_20_we;
483 logic alert_en_shadowed_20_qs;
484 logic alert_en_shadowed_20_wd;
485 logic alert_en_shadowed_20_storage_err;
486 logic alert_en_shadowed_20_update_err;
487 logic alert_en_shadowed_21_re;
488 logic alert_en_shadowed_21_we;
489 logic alert_en_shadowed_21_qs;
490 logic alert_en_shadowed_21_wd;
491 logic alert_en_shadowed_21_storage_err;
492 logic alert_en_shadowed_21_update_err;
493 logic alert_en_shadowed_22_re;
494 logic alert_en_shadowed_22_we;
495 logic alert_en_shadowed_22_qs;
496 logic alert_en_shadowed_22_wd;
497 logic alert_en_shadowed_22_storage_err;
498 logic alert_en_shadowed_22_update_err;
499 logic alert_en_shadowed_23_re;
500 logic alert_en_shadowed_23_we;
501 logic alert_en_shadowed_23_qs;
502 logic alert_en_shadowed_23_wd;
503 logic alert_en_shadowed_23_storage_err;
504 logic alert_en_shadowed_23_update_err;
505 logic alert_en_shadowed_24_re;
506 logic alert_en_shadowed_24_we;
507 logic alert_en_shadowed_24_qs;
508 logic alert_en_shadowed_24_wd;
509 logic alert_en_shadowed_24_storage_err;
510 logic alert_en_shadowed_24_update_err;
511 logic alert_en_shadowed_25_re;
512 logic alert_en_shadowed_25_we;
513 logic alert_en_shadowed_25_qs;
514 logic alert_en_shadowed_25_wd;
515 logic alert_en_shadowed_25_storage_err;
516 logic alert_en_shadowed_25_update_err;
517 logic alert_en_shadowed_26_re;
518 logic alert_en_shadowed_26_we;
519 logic alert_en_shadowed_26_qs;
520 logic alert_en_shadowed_26_wd;
521 logic alert_en_shadowed_26_storage_err;
522 logic alert_en_shadowed_26_update_err;
523 logic alert_en_shadowed_27_re;
524 logic alert_en_shadowed_27_we;
525 logic alert_en_shadowed_27_qs;
526 logic alert_en_shadowed_27_wd;
527 logic alert_en_shadowed_27_storage_err;
528 logic alert_en_shadowed_27_update_err;
529 logic alert_en_shadowed_28_re;
530 logic alert_en_shadowed_28_we;
531 logic alert_en_shadowed_28_qs;
532 logic alert_en_shadowed_28_wd;
533 logic alert_en_shadowed_28_storage_err;
534 logic alert_en_shadowed_28_update_err;
535 logic alert_en_shadowed_29_re;
536 logic alert_en_shadowed_29_we;
537 logic alert_en_shadowed_29_qs;
538 logic alert_en_shadowed_29_wd;
539 logic alert_en_shadowed_29_storage_err;
540 logic alert_en_shadowed_29_update_err;
541 logic alert_en_shadowed_30_re;
542 logic alert_en_shadowed_30_we;
543 logic alert_en_shadowed_30_qs;
544 logic alert_en_shadowed_30_wd;
545 logic alert_en_shadowed_30_storage_err;
546 logic alert_en_shadowed_30_update_err;
547 logic alert_en_shadowed_31_re;
548 logic alert_en_shadowed_31_we;
549 logic alert_en_shadowed_31_qs;
550 logic alert_en_shadowed_31_wd;
551 logic alert_en_shadowed_31_storage_err;
552 logic alert_en_shadowed_31_update_err;
553 logic alert_en_shadowed_32_re;
554 logic alert_en_shadowed_32_we;
555 logic alert_en_shadowed_32_qs;
556 logic alert_en_shadowed_32_wd;
557 logic alert_en_shadowed_32_storage_err;
558 logic alert_en_shadowed_32_update_err;
559 logic alert_en_shadowed_33_re;
560 logic alert_en_shadowed_33_we;
561 logic alert_en_shadowed_33_qs;
562 logic alert_en_shadowed_33_wd;
563 logic alert_en_shadowed_33_storage_err;
564 logic alert_en_shadowed_33_update_err;
565 logic alert_en_shadowed_34_re;
566 logic alert_en_shadowed_34_we;
567 logic alert_en_shadowed_34_qs;
568 logic alert_en_shadowed_34_wd;
569 logic alert_en_shadowed_34_storage_err;
570 logic alert_en_shadowed_34_update_err;
571 logic alert_en_shadowed_35_re;
572 logic alert_en_shadowed_35_we;
573 logic alert_en_shadowed_35_qs;
574 logic alert_en_shadowed_35_wd;
575 logic alert_en_shadowed_35_storage_err;
576 logic alert_en_shadowed_35_update_err;
577 logic alert_en_shadowed_36_re;
578 logic alert_en_shadowed_36_we;
579 logic alert_en_shadowed_36_qs;
580 logic alert_en_shadowed_36_wd;
581 logic alert_en_shadowed_36_storage_err;
582 logic alert_en_shadowed_36_update_err;
583 logic alert_en_shadowed_37_re;
584 logic alert_en_shadowed_37_we;
585 logic alert_en_shadowed_37_qs;
586 logic alert_en_shadowed_37_wd;
587 logic alert_en_shadowed_37_storage_err;
588 logic alert_en_shadowed_37_update_err;
589 logic alert_en_shadowed_38_re;
590 logic alert_en_shadowed_38_we;
591 logic alert_en_shadowed_38_qs;
592 logic alert_en_shadowed_38_wd;
593 logic alert_en_shadowed_38_storage_err;
594 logic alert_en_shadowed_38_update_err;
595 logic alert_en_shadowed_39_re;
596 logic alert_en_shadowed_39_we;
597 logic alert_en_shadowed_39_qs;
598 logic alert_en_shadowed_39_wd;
599 logic alert_en_shadowed_39_storage_err;
600 logic alert_en_shadowed_39_update_err;
601 logic alert_en_shadowed_40_re;
602 logic alert_en_shadowed_40_we;
603 logic alert_en_shadowed_40_qs;
604 logic alert_en_shadowed_40_wd;
605 logic alert_en_shadowed_40_storage_err;
606 logic alert_en_shadowed_40_update_err;
607 logic alert_en_shadowed_41_re;
608 logic alert_en_shadowed_41_we;
609 logic alert_en_shadowed_41_qs;
610 logic alert_en_shadowed_41_wd;
611 logic alert_en_shadowed_41_storage_err;
612 logic alert_en_shadowed_41_update_err;
613 logic alert_en_shadowed_42_re;
614 logic alert_en_shadowed_42_we;
615 logic alert_en_shadowed_42_qs;
616 logic alert_en_shadowed_42_wd;
617 logic alert_en_shadowed_42_storage_err;
618 logic alert_en_shadowed_42_update_err;
619 logic alert_en_shadowed_43_re;
620 logic alert_en_shadowed_43_we;
621 logic alert_en_shadowed_43_qs;
622 logic alert_en_shadowed_43_wd;
623 logic alert_en_shadowed_43_storage_err;
624 logic alert_en_shadowed_43_update_err;
625 logic alert_en_shadowed_44_re;
626 logic alert_en_shadowed_44_we;
627 logic alert_en_shadowed_44_qs;
628 logic alert_en_shadowed_44_wd;
629 logic alert_en_shadowed_44_storage_err;
630 logic alert_en_shadowed_44_update_err;
631 logic alert_en_shadowed_45_re;
632 logic alert_en_shadowed_45_we;
633 logic alert_en_shadowed_45_qs;
634 logic alert_en_shadowed_45_wd;
635 logic alert_en_shadowed_45_storage_err;
636 logic alert_en_shadowed_45_update_err;
637 logic alert_en_shadowed_46_re;
638 logic alert_en_shadowed_46_we;
639 logic alert_en_shadowed_46_qs;
640 logic alert_en_shadowed_46_wd;
641 logic alert_en_shadowed_46_storage_err;
642 logic alert_en_shadowed_46_update_err;
643 logic alert_en_shadowed_47_re;
644 logic alert_en_shadowed_47_we;
645 logic alert_en_shadowed_47_qs;
646 logic alert_en_shadowed_47_wd;
647 logic alert_en_shadowed_47_storage_err;
648 logic alert_en_shadowed_47_update_err;
649 logic alert_en_shadowed_48_re;
650 logic alert_en_shadowed_48_we;
651 logic alert_en_shadowed_48_qs;
652 logic alert_en_shadowed_48_wd;
653 logic alert_en_shadowed_48_storage_err;
654 logic alert_en_shadowed_48_update_err;
655 logic alert_en_shadowed_49_re;
656 logic alert_en_shadowed_49_we;
657 logic alert_en_shadowed_49_qs;
658 logic alert_en_shadowed_49_wd;
659 logic alert_en_shadowed_49_storage_err;
660 logic alert_en_shadowed_49_update_err;
661 logic alert_en_shadowed_50_re;
662 logic alert_en_shadowed_50_we;
663 logic alert_en_shadowed_50_qs;
664 logic alert_en_shadowed_50_wd;
665 logic alert_en_shadowed_50_storage_err;
666 logic alert_en_shadowed_50_update_err;
667 logic alert_en_shadowed_51_re;
668 logic alert_en_shadowed_51_we;
669 logic alert_en_shadowed_51_qs;
670 logic alert_en_shadowed_51_wd;
671 logic alert_en_shadowed_51_storage_err;
672 logic alert_en_shadowed_51_update_err;
673 logic alert_en_shadowed_52_re;
674 logic alert_en_shadowed_52_we;
675 logic alert_en_shadowed_52_qs;
676 logic alert_en_shadowed_52_wd;
677 logic alert_en_shadowed_52_storage_err;
678 logic alert_en_shadowed_52_update_err;
679 logic alert_en_shadowed_53_re;
680 logic alert_en_shadowed_53_we;
681 logic alert_en_shadowed_53_qs;
682 logic alert_en_shadowed_53_wd;
683 logic alert_en_shadowed_53_storage_err;
684 logic alert_en_shadowed_53_update_err;
685 logic alert_en_shadowed_54_re;
686 logic alert_en_shadowed_54_we;
687 logic alert_en_shadowed_54_qs;
688 logic alert_en_shadowed_54_wd;
689 logic alert_en_shadowed_54_storage_err;
690 logic alert_en_shadowed_54_update_err;
691 logic alert_en_shadowed_55_re;
692 logic alert_en_shadowed_55_we;
693 logic alert_en_shadowed_55_qs;
694 logic alert_en_shadowed_55_wd;
695 logic alert_en_shadowed_55_storage_err;
696 logic alert_en_shadowed_55_update_err;
697 logic alert_en_shadowed_56_re;
698 logic alert_en_shadowed_56_we;
699 logic alert_en_shadowed_56_qs;
700 logic alert_en_shadowed_56_wd;
701 logic alert_en_shadowed_56_storage_err;
702 logic alert_en_shadowed_56_update_err;
703 logic alert_en_shadowed_57_re;
704 logic alert_en_shadowed_57_we;
705 logic alert_en_shadowed_57_qs;
706 logic alert_en_shadowed_57_wd;
707 logic alert_en_shadowed_57_storage_err;
708 logic alert_en_shadowed_57_update_err;
709 logic alert_en_shadowed_58_re;
710 logic alert_en_shadowed_58_we;
711 logic alert_en_shadowed_58_qs;
712 logic alert_en_shadowed_58_wd;
713 logic alert_en_shadowed_58_storage_err;
714 logic alert_en_shadowed_58_update_err;
715 logic alert_en_shadowed_59_re;
716 logic alert_en_shadowed_59_we;
717 logic alert_en_shadowed_59_qs;
718 logic alert_en_shadowed_59_wd;
719 logic alert_en_shadowed_59_storage_err;
720 logic alert_en_shadowed_59_update_err;
721 logic alert_en_shadowed_60_re;
722 logic alert_en_shadowed_60_we;
723 logic alert_en_shadowed_60_qs;
724 logic alert_en_shadowed_60_wd;
725 logic alert_en_shadowed_60_storage_err;
726 logic alert_en_shadowed_60_update_err;
727 logic alert_en_shadowed_61_re;
728 logic alert_en_shadowed_61_we;
729 logic alert_en_shadowed_61_qs;
730 logic alert_en_shadowed_61_wd;
731 logic alert_en_shadowed_61_storage_err;
732 logic alert_en_shadowed_61_update_err;
733 logic alert_en_shadowed_62_re;
734 logic alert_en_shadowed_62_we;
735 logic alert_en_shadowed_62_qs;
736 logic alert_en_shadowed_62_wd;
737 logic alert_en_shadowed_62_storage_err;
738 logic alert_en_shadowed_62_update_err;
739 logic alert_en_shadowed_63_re;
740 logic alert_en_shadowed_63_we;
741 logic alert_en_shadowed_63_qs;
742 logic alert_en_shadowed_63_wd;
743 logic alert_en_shadowed_63_storage_err;
744 logic alert_en_shadowed_63_update_err;
745 logic alert_en_shadowed_64_re;
746 logic alert_en_shadowed_64_we;
747 logic alert_en_shadowed_64_qs;
748 logic alert_en_shadowed_64_wd;
749 logic alert_en_shadowed_64_storage_err;
750 logic alert_en_shadowed_64_update_err;
751 logic alert_class_shadowed_0_re;
752 logic alert_class_shadowed_0_we;
753 logic [1:0] alert_class_shadowed_0_qs;
754 logic [1:0] alert_class_shadowed_0_wd;
755 logic alert_class_shadowed_0_storage_err;
756 logic alert_class_shadowed_0_update_err;
757 logic alert_class_shadowed_1_re;
758 logic alert_class_shadowed_1_we;
759 logic [1:0] alert_class_shadowed_1_qs;
760 logic [1:0] alert_class_shadowed_1_wd;
761 logic alert_class_shadowed_1_storage_err;
762 logic alert_class_shadowed_1_update_err;
763 logic alert_class_shadowed_2_re;
764 logic alert_class_shadowed_2_we;
765 logic [1:0] alert_class_shadowed_2_qs;
766 logic [1:0] alert_class_shadowed_2_wd;
767 logic alert_class_shadowed_2_storage_err;
768 logic alert_class_shadowed_2_update_err;
769 logic alert_class_shadowed_3_re;
770 logic alert_class_shadowed_3_we;
771 logic [1:0] alert_class_shadowed_3_qs;
772 logic [1:0] alert_class_shadowed_3_wd;
773 logic alert_class_shadowed_3_storage_err;
774 logic alert_class_shadowed_3_update_err;
775 logic alert_class_shadowed_4_re;
776 logic alert_class_shadowed_4_we;
777 logic [1:0] alert_class_shadowed_4_qs;
778 logic [1:0] alert_class_shadowed_4_wd;
779 logic alert_class_shadowed_4_storage_err;
780 logic alert_class_shadowed_4_update_err;
781 logic alert_class_shadowed_5_re;
782 logic alert_class_shadowed_5_we;
783 logic [1:0] alert_class_shadowed_5_qs;
784 logic [1:0] alert_class_shadowed_5_wd;
785 logic alert_class_shadowed_5_storage_err;
786 logic alert_class_shadowed_5_update_err;
787 logic alert_class_shadowed_6_re;
788 logic alert_class_shadowed_6_we;
789 logic [1:0] alert_class_shadowed_6_qs;
790 logic [1:0] alert_class_shadowed_6_wd;
791 logic alert_class_shadowed_6_storage_err;
792 logic alert_class_shadowed_6_update_err;
793 logic alert_class_shadowed_7_re;
794 logic alert_class_shadowed_7_we;
795 logic [1:0] alert_class_shadowed_7_qs;
796 logic [1:0] alert_class_shadowed_7_wd;
797 logic alert_class_shadowed_7_storage_err;
798 logic alert_class_shadowed_7_update_err;
799 logic alert_class_shadowed_8_re;
800 logic alert_class_shadowed_8_we;
801 logic [1:0] alert_class_shadowed_8_qs;
802 logic [1:0] alert_class_shadowed_8_wd;
803 logic alert_class_shadowed_8_storage_err;
804 logic alert_class_shadowed_8_update_err;
805 logic alert_class_shadowed_9_re;
806 logic alert_class_shadowed_9_we;
807 logic [1:0] alert_class_shadowed_9_qs;
808 logic [1:0] alert_class_shadowed_9_wd;
809 logic alert_class_shadowed_9_storage_err;
810 logic alert_class_shadowed_9_update_err;
811 logic alert_class_shadowed_10_re;
812 logic alert_class_shadowed_10_we;
813 logic [1:0] alert_class_shadowed_10_qs;
814 logic [1:0] alert_class_shadowed_10_wd;
815 logic alert_class_shadowed_10_storage_err;
816 logic alert_class_shadowed_10_update_err;
817 logic alert_class_shadowed_11_re;
818 logic alert_class_shadowed_11_we;
819 logic [1:0] alert_class_shadowed_11_qs;
820 logic [1:0] alert_class_shadowed_11_wd;
821 logic alert_class_shadowed_11_storage_err;
822 logic alert_class_shadowed_11_update_err;
823 logic alert_class_shadowed_12_re;
824 logic alert_class_shadowed_12_we;
825 logic [1:0] alert_class_shadowed_12_qs;
826 logic [1:0] alert_class_shadowed_12_wd;
827 logic alert_class_shadowed_12_storage_err;
828 logic alert_class_shadowed_12_update_err;
829 logic alert_class_shadowed_13_re;
830 logic alert_class_shadowed_13_we;
831 logic [1:0] alert_class_shadowed_13_qs;
832 logic [1:0] alert_class_shadowed_13_wd;
833 logic alert_class_shadowed_13_storage_err;
834 logic alert_class_shadowed_13_update_err;
835 logic alert_class_shadowed_14_re;
836 logic alert_class_shadowed_14_we;
837 logic [1:0] alert_class_shadowed_14_qs;
838 logic [1:0] alert_class_shadowed_14_wd;
839 logic alert_class_shadowed_14_storage_err;
840 logic alert_class_shadowed_14_update_err;
841 logic alert_class_shadowed_15_re;
842 logic alert_class_shadowed_15_we;
843 logic [1:0] alert_class_shadowed_15_qs;
844 logic [1:0] alert_class_shadowed_15_wd;
845 logic alert_class_shadowed_15_storage_err;
846 logic alert_class_shadowed_15_update_err;
847 logic alert_class_shadowed_16_re;
848 logic alert_class_shadowed_16_we;
849 logic [1:0] alert_class_shadowed_16_qs;
850 logic [1:0] alert_class_shadowed_16_wd;
851 logic alert_class_shadowed_16_storage_err;
852 logic alert_class_shadowed_16_update_err;
853 logic alert_class_shadowed_17_re;
854 logic alert_class_shadowed_17_we;
855 logic [1:0] alert_class_shadowed_17_qs;
856 logic [1:0] alert_class_shadowed_17_wd;
857 logic alert_class_shadowed_17_storage_err;
858 logic alert_class_shadowed_17_update_err;
859 logic alert_class_shadowed_18_re;
860 logic alert_class_shadowed_18_we;
861 logic [1:0] alert_class_shadowed_18_qs;
862 logic [1:0] alert_class_shadowed_18_wd;
863 logic alert_class_shadowed_18_storage_err;
864 logic alert_class_shadowed_18_update_err;
865 logic alert_class_shadowed_19_re;
866 logic alert_class_shadowed_19_we;
867 logic [1:0] alert_class_shadowed_19_qs;
868 logic [1:0] alert_class_shadowed_19_wd;
869 logic alert_class_shadowed_19_storage_err;
870 logic alert_class_shadowed_19_update_err;
871 logic alert_class_shadowed_20_re;
872 logic alert_class_shadowed_20_we;
873 logic [1:0] alert_class_shadowed_20_qs;
874 logic [1:0] alert_class_shadowed_20_wd;
875 logic alert_class_shadowed_20_storage_err;
876 logic alert_class_shadowed_20_update_err;
877 logic alert_class_shadowed_21_re;
878 logic alert_class_shadowed_21_we;
879 logic [1:0] alert_class_shadowed_21_qs;
880 logic [1:0] alert_class_shadowed_21_wd;
881 logic alert_class_shadowed_21_storage_err;
882 logic alert_class_shadowed_21_update_err;
883 logic alert_class_shadowed_22_re;
884 logic alert_class_shadowed_22_we;
885 logic [1:0] alert_class_shadowed_22_qs;
886 logic [1:0] alert_class_shadowed_22_wd;
887 logic alert_class_shadowed_22_storage_err;
888 logic alert_class_shadowed_22_update_err;
889 logic alert_class_shadowed_23_re;
890 logic alert_class_shadowed_23_we;
891 logic [1:0] alert_class_shadowed_23_qs;
892 logic [1:0] alert_class_shadowed_23_wd;
893 logic alert_class_shadowed_23_storage_err;
894 logic alert_class_shadowed_23_update_err;
895 logic alert_class_shadowed_24_re;
896 logic alert_class_shadowed_24_we;
897 logic [1:0] alert_class_shadowed_24_qs;
898 logic [1:0] alert_class_shadowed_24_wd;
899 logic alert_class_shadowed_24_storage_err;
900 logic alert_class_shadowed_24_update_err;
901 logic alert_class_shadowed_25_re;
902 logic alert_class_shadowed_25_we;
903 logic [1:0] alert_class_shadowed_25_qs;
904 logic [1:0] alert_class_shadowed_25_wd;
905 logic alert_class_shadowed_25_storage_err;
906 logic alert_class_shadowed_25_update_err;
907 logic alert_class_shadowed_26_re;
908 logic alert_class_shadowed_26_we;
909 logic [1:0] alert_class_shadowed_26_qs;
910 logic [1:0] alert_class_shadowed_26_wd;
911 logic alert_class_shadowed_26_storage_err;
912 logic alert_class_shadowed_26_update_err;
913 logic alert_class_shadowed_27_re;
914 logic alert_class_shadowed_27_we;
915 logic [1:0] alert_class_shadowed_27_qs;
916 logic [1:0] alert_class_shadowed_27_wd;
917 logic alert_class_shadowed_27_storage_err;
918 logic alert_class_shadowed_27_update_err;
919 logic alert_class_shadowed_28_re;
920 logic alert_class_shadowed_28_we;
921 logic [1:0] alert_class_shadowed_28_qs;
922 logic [1:0] alert_class_shadowed_28_wd;
923 logic alert_class_shadowed_28_storage_err;
924 logic alert_class_shadowed_28_update_err;
925 logic alert_class_shadowed_29_re;
926 logic alert_class_shadowed_29_we;
927 logic [1:0] alert_class_shadowed_29_qs;
928 logic [1:0] alert_class_shadowed_29_wd;
929 logic alert_class_shadowed_29_storage_err;
930 logic alert_class_shadowed_29_update_err;
931 logic alert_class_shadowed_30_re;
932 logic alert_class_shadowed_30_we;
933 logic [1:0] alert_class_shadowed_30_qs;
934 logic [1:0] alert_class_shadowed_30_wd;
935 logic alert_class_shadowed_30_storage_err;
936 logic alert_class_shadowed_30_update_err;
937 logic alert_class_shadowed_31_re;
938 logic alert_class_shadowed_31_we;
939 logic [1:0] alert_class_shadowed_31_qs;
940 logic [1:0] alert_class_shadowed_31_wd;
941 logic alert_class_shadowed_31_storage_err;
942 logic alert_class_shadowed_31_update_err;
943 logic alert_class_shadowed_32_re;
944 logic alert_class_shadowed_32_we;
945 logic [1:0] alert_class_shadowed_32_qs;
946 logic [1:0] alert_class_shadowed_32_wd;
947 logic alert_class_shadowed_32_storage_err;
948 logic alert_class_shadowed_32_update_err;
949 logic alert_class_shadowed_33_re;
950 logic alert_class_shadowed_33_we;
951 logic [1:0] alert_class_shadowed_33_qs;
952 logic [1:0] alert_class_shadowed_33_wd;
953 logic alert_class_shadowed_33_storage_err;
954 logic alert_class_shadowed_33_update_err;
955 logic alert_class_shadowed_34_re;
956 logic alert_class_shadowed_34_we;
957 logic [1:0] alert_class_shadowed_34_qs;
958 logic [1:0] alert_class_shadowed_34_wd;
959 logic alert_class_shadowed_34_storage_err;
960 logic alert_class_shadowed_34_update_err;
961 logic alert_class_shadowed_35_re;
962 logic alert_class_shadowed_35_we;
963 logic [1:0] alert_class_shadowed_35_qs;
964 logic [1:0] alert_class_shadowed_35_wd;
965 logic alert_class_shadowed_35_storage_err;
966 logic alert_class_shadowed_35_update_err;
967 logic alert_class_shadowed_36_re;
968 logic alert_class_shadowed_36_we;
969 logic [1:0] alert_class_shadowed_36_qs;
970 logic [1:0] alert_class_shadowed_36_wd;
971 logic alert_class_shadowed_36_storage_err;
972 logic alert_class_shadowed_36_update_err;
973 logic alert_class_shadowed_37_re;
974 logic alert_class_shadowed_37_we;
975 logic [1:0] alert_class_shadowed_37_qs;
976 logic [1:0] alert_class_shadowed_37_wd;
977 logic alert_class_shadowed_37_storage_err;
978 logic alert_class_shadowed_37_update_err;
979 logic alert_class_shadowed_38_re;
980 logic alert_class_shadowed_38_we;
981 logic [1:0] alert_class_shadowed_38_qs;
982 logic [1:0] alert_class_shadowed_38_wd;
983 logic alert_class_shadowed_38_storage_err;
984 logic alert_class_shadowed_38_update_err;
985 logic alert_class_shadowed_39_re;
986 logic alert_class_shadowed_39_we;
987 logic [1:0] alert_class_shadowed_39_qs;
988 logic [1:0] alert_class_shadowed_39_wd;
989 logic alert_class_shadowed_39_storage_err;
990 logic alert_class_shadowed_39_update_err;
991 logic alert_class_shadowed_40_re;
992 logic alert_class_shadowed_40_we;
993 logic [1:0] alert_class_shadowed_40_qs;
994 logic [1:0] alert_class_shadowed_40_wd;
995 logic alert_class_shadowed_40_storage_err;
996 logic alert_class_shadowed_40_update_err;
997 logic alert_class_shadowed_41_re;
998 logic alert_class_shadowed_41_we;
999 logic [1:0] alert_class_shadowed_41_qs;
1000 logic [1:0] alert_class_shadowed_41_wd;
1001 logic alert_class_shadowed_41_storage_err;
1002 logic alert_class_shadowed_41_update_err;
1003 logic alert_class_shadowed_42_re;
1004 logic alert_class_shadowed_42_we;
1005 logic [1:0] alert_class_shadowed_42_qs;
1006 logic [1:0] alert_class_shadowed_42_wd;
1007 logic alert_class_shadowed_42_storage_err;
1008 logic alert_class_shadowed_42_update_err;
1009 logic alert_class_shadowed_43_re;
1010 logic alert_class_shadowed_43_we;
1011 logic [1:0] alert_class_shadowed_43_qs;
1012 logic [1:0] alert_class_shadowed_43_wd;
1013 logic alert_class_shadowed_43_storage_err;
1014 logic alert_class_shadowed_43_update_err;
1015 logic alert_class_shadowed_44_re;
1016 logic alert_class_shadowed_44_we;
1017 logic [1:0] alert_class_shadowed_44_qs;
1018 logic [1:0] alert_class_shadowed_44_wd;
1019 logic alert_class_shadowed_44_storage_err;
1020 logic alert_class_shadowed_44_update_err;
1021 logic alert_class_shadowed_45_re;
1022 logic alert_class_shadowed_45_we;
1023 logic [1:0] alert_class_shadowed_45_qs;
1024 logic [1:0] alert_class_shadowed_45_wd;
1025 logic alert_class_shadowed_45_storage_err;
1026 logic alert_class_shadowed_45_update_err;
1027 logic alert_class_shadowed_46_re;
1028 logic alert_class_shadowed_46_we;
1029 logic [1:0] alert_class_shadowed_46_qs;
1030 logic [1:0] alert_class_shadowed_46_wd;
1031 logic alert_class_shadowed_46_storage_err;
1032 logic alert_class_shadowed_46_update_err;
1033 logic alert_class_shadowed_47_re;
1034 logic alert_class_shadowed_47_we;
1035 logic [1:0] alert_class_shadowed_47_qs;
1036 logic [1:0] alert_class_shadowed_47_wd;
1037 logic alert_class_shadowed_47_storage_err;
1038 logic alert_class_shadowed_47_update_err;
1039 logic alert_class_shadowed_48_re;
1040 logic alert_class_shadowed_48_we;
1041 logic [1:0] alert_class_shadowed_48_qs;
1042 logic [1:0] alert_class_shadowed_48_wd;
1043 logic alert_class_shadowed_48_storage_err;
1044 logic alert_class_shadowed_48_update_err;
1045 logic alert_class_shadowed_49_re;
1046 logic alert_class_shadowed_49_we;
1047 logic [1:0] alert_class_shadowed_49_qs;
1048 logic [1:0] alert_class_shadowed_49_wd;
1049 logic alert_class_shadowed_49_storage_err;
1050 logic alert_class_shadowed_49_update_err;
1051 logic alert_class_shadowed_50_re;
1052 logic alert_class_shadowed_50_we;
1053 logic [1:0] alert_class_shadowed_50_qs;
1054 logic [1:0] alert_class_shadowed_50_wd;
1055 logic alert_class_shadowed_50_storage_err;
1056 logic alert_class_shadowed_50_update_err;
1057 logic alert_class_shadowed_51_re;
1058 logic alert_class_shadowed_51_we;
1059 logic [1:0] alert_class_shadowed_51_qs;
1060 logic [1:0] alert_class_shadowed_51_wd;
1061 logic alert_class_shadowed_51_storage_err;
1062 logic alert_class_shadowed_51_update_err;
1063 logic alert_class_shadowed_52_re;
1064 logic alert_class_shadowed_52_we;
1065 logic [1:0] alert_class_shadowed_52_qs;
1066 logic [1:0] alert_class_shadowed_52_wd;
1067 logic alert_class_shadowed_52_storage_err;
1068 logic alert_class_shadowed_52_update_err;
1069 logic alert_class_shadowed_53_re;
1070 logic alert_class_shadowed_53_we;
1071 logic [1:0] alert_class_shadowed_53_qs;
1072 logic [1:0] alert_class_shadowed_53_wd;
1073 logic alert_class_shadowed_53_storage_err;
1074 logic alert_class_shadowed_53_update_err;
1075 logic alert_class_shadowed_54_re;
1076 logic alert_class_shadowed_54_we;
1077 logic [1:0] alert_class_shadowed_54_qs;
1078 logic [1:0] alert_class_shadowed_54_wd;
1079 logic alert_class_shadowed_54_storage_err;
1080 logic alert_class_shadowed_54_update_err;
1081 logic alert_class_shadowed_55_re;
1082 logic alert_class_shadowed_55_we;
1083 logic [1:0] alert_class_shadowed_55_qs;
1084 logic [1:0] alert_class_shadowed_55_wd;
1085 logic alert_class_shadowed_55_storage_err;
1086 logic alert_class_shadowed_55_update_err;
1087 logic alert_class_shadowed_56_re;
1088 logic alert_class_shadowed_56_we;
1089 logic [1:0] alert_class_shadowed_56_qs;
1090 logic [1:0] alert_class_shadowed_56_wd;
1091 logic alert_class_shadowed_56_storage_err;
1092 logic alert_class_shadowed_56_update_err;
1093 logic alert_class_shadowed_57_re;
1094 logic alert_class_shadowed_57_we;
1095 logic [1:0] alert_class_shadowed_57_qs;
1096 logic [1:0] alert_class_shadowed_57_wd;
1097 logic alert_class_shadowed_57_storage_err;
1098 logic alert_class_shadowed_57_update_err;
1099 logic alert_class_shadowed_58_re;
1100 logic alert_class_shadowed_58_we;
1101 logic [1:0] alert_class_shadowed_58_qs;
1102 logic [1:0] alert_class_shadowed_58_wd;
1103 logic alert_class_shadowed_58_storage_err;
1104 logic alert_class_shadowed_58_update_err;
1105 logic alert_class_shadowed_59_re;
1106 logic alert_class_shadowed_59_we;
1107 logic [1:0] alert_class_shadowed_59_qs;
1108 logic [1:0] alert_class_shadowed_59_wd;
1109 logic alert_class_shadowed_59_storage_err;
1110 logic alert_class_shadowed_59_update_err;
1111 logic alert_class_shadowed_60_re;
1112 logic alert_class_shadowed_60_we;
1113 logic [1:0] alert_class_shadowed_60_qs;
1114 logic [1:0] alert_class_shadowed_60_wd;
1115 logic alert_class_shadowed_60_storage_err;
1116 logic alert_class_shadowed_60_update_err;
1117 logic alert_class_shadowed_61_re;
1118 logic alert_class_shadowed_61_we;
1119 logic [1:0] alert_class_shadowed_61_qs;
1120 logic [1:0] alert_class_shadowed_61_wd;
1121 logic alert_class_shadowed_61_storage_err;
1122 logic alert_class_shadowed_61_update_err;
1123 logic alert_class_shadowed_62_re;
1124 logic alert_class_shadowed_62_we;
1125 logic [1:0] alert_class_shadowed_62_qs;
1126 logic [1:0] alert_class_shadowed_62_wd;
1127 logic alert_class_shadowed_62_storage_err;
1128 logic alert_class_shadowed_62_update_err;
1129 logic alert_class_shadowed_63_re;
1130 logic alert_class_shadowed_63_we;
1131 logic [1:0] alert_class_shadowed_63_qs;
1132 logic [1:0] alert_class_shadowed_63_wd;
1133 logic alert_class_shadowed_63_storage_err;
1134 logic alert_class_shadowed_63_update_err;
1135 logic alert_class_shadowed_64_re;
1136 logic alert_class_shadowed_64_we;
1137 logic [1:0] alert_class_shadowed_64_qs;
1138 logic [1:0] alert_class_shadowed_64_wd;
1139 logic alert_class_shadowed_64_storage_err;
1140 logic alert_class_shadowed_64_update_err;
1141 logic alert_cause_0_we;
1142 logic alert_cause_0_qs;
1143 logic alert_cause_0_wd;
1144 logic alert_cause_1_we;
1145 logic alert_cause_1_qs;
1146 logic alert_cause_1_wd;
1147 logic alert_cause_2_we;
1148 logic alert_cause_2_qs;
1149 logic alert_cause_2_wd;
1150 logic alert_cause_3_we;
1151 logic alert_cause_3_qs;
1152 logic alert_cause_3_wd;
1153 logic alert_cause_4_we;
1154 logic alert_cause_4_qs;
1155 logic alert_cause_4_wd;
1156 logic alert_cause_5_we;
1157 logic alert_cause_5_qs;
1158 logic alert_cause_5_wd;
1159 logic alert_cause_6_we;
1160 logic alert_cause_6_qs;
1161 logic alert_cause_6_wd;
1162 logic alert_cause_7_we;
1163 logic alert_cause_7_qs;
1164 logic alert_cause_7_wd;
1165 logic alert_cause_8_we;
1166 logic alert_cause_8_qs;
1167 logic alert_cause_8_wd;
1168 logic alert_cause_9_we;
1169 logic alert_cause_9_qs;
1170 logic alert_cause_9_wd;
1171 logic alert_cause_10_we;
1172 logic alert_cause_10_qs;
1173 logic alert_cause_10_wd;
1174 logic alert_cause_11_we;
1175 logic alert_cause_11_qs;
1176 logic alert_cause_11_wd;
1177 logic alert_cause_12_we;
1178 logic alert_cause_12_qs;
1179 logic alert_cause_12_wd;
1180 logic alert_cause_13_we;
1181 logic alert_cause_13_qs;
1182 logic alert_cause_13_wd;
1183 logic alert_cause_14_we;
1184 logic alert_cause_14_qs;
1185 logic alert_cause_14_wd;
1186 logic alert_cause_15_we;
1187 logic alert_cause_15_qs;
1188 logic alert_cause_15_wd;
1189 logic alert_cause_16_we;
1190 logic alert_cause_16_qs;
1191 logic alert_cause_16_wd;
1192 logic alert_cause_17_we;
1193 logic alert_cause_17_qs;
1194 logic alert_cause_17_wd;
1195 logic alert_cause_18_we;
1196 logic alert_cause_18_qs;
1197 logic alert_cause_18_wd;
1198 logic alert_cause_19_we;
1199 logic alert_cause_19_qs;
1200 logic alert_cause_19_wd;
1201 logic alert_cause_20_we;
1202 logic alert_cause_20_qs;
1203 logic alert_cause_20_wd;
1204 logic alert_cause_21_we;
1205 logic alert_cause_21_qs;
1206 logic alert_cause_21_wd;
1207 logic alert_cause_22_we;
1208 logic alert_cause_22_qs;
1209 logic alert_cause_22_wd;
1210 logic alert_cause_23_we;
1211 logic alert_cause_23_qs;
1212 logic alert_cause_23_wd;
1213 logic alert_cause_24_we;
1214 logic alert_cause_24_qs;
1215 logic alert_cause_24_wd;
1216 logic alert_cause_25_we;
1217 logic alert_cause_25_qs;
1218 logic alert_cause_25_wd;
1219 logic alert_cause_26_we;
1220 logic alert_cause_26_qs;
1221 logic alert_cause_26_wd;
1222 logic alert_cause_27_we;
1223 logic alert_cause_27_qs;
1224 logic alert_cause_27_wd;
1225 logic alert_cause_28_we;
1226 logic alert_cause_28_qs;
1227 logic alert_cause_28_wd;
1228 logic alert_cause_29_we;
1229 logic alert_cause_29_qs;
1230 logic alert_cause_29_wd;
1231 logic alert_cause_30_we;
1232 logic alert_cause_30_qs;
1233 logic alert_cause_30_wd;
1234 logic alert_cause_31_we;
1235 logic alert_cause_31_qs;
1236 logic alert_cause_31_wd;
1237 logic alert_cause_32_we;
1238 logic alert_cause_32_qs;
1239 logic alert_cause_32_wd;
1240 logic alert_cause_33_we;
1241 logic alert_cause_33_qs;
1242 logic alert_cause_33_wd;
1243 logic alert_cause_34_we;
1244 logic alert_cause_34_qs;
1245 logic alert_cause_34_wd;
1246 logic alert_cause_35_we;
1247 logic alert_cause_35_qs;
1248 logic alert_cause_35_wd;
1249 logic alert_cause_36_we;
1250 logic alert_cause_36_qs;
1251 logic alert_cause_36_wd;
1252 logic alert_cause_37_we;
1253 logic alert_cause_37_qs;
1254 logic alert_cause_37_wd;
1255 logic alert_cause_38_we;
1256 logic alert_cause_38_qs;
1257 logic alert_cause_38_wd;
1258 logic alert_cause_39_we;
1259 logic alert_cause_39_qs;
1260 logic alert_cause_39_wd;
1261 logic alert_cause_40_we;
1262 logic alert_cause_40_qs;
1263 logic alert_cause_40_wd;
1264 logic alert_cause_41_we;
1265 logic alert_cause_41_qs;
1266 logic alert_cause_41_wd;
1267 logic alert_cause_42_we;
1268 logic alert_cause_42_qs;
1269 logic alert_cause_42_wd;
1270 logic alert_cause_43_we;
1271 logic alert_cause_43_qs;
1272 logic alert_cause_43_wd;
1273 logic alert_cause_44_we;
1274 logic alert_cause_44_qs;
1275 logic alert_cause_44_wd;
1276 logic alert_cause_45_we;
1277 logic alert_cause_45_qs;
1278 logic alert_cause_45_wd;
1279 logic alert_cause_46_we;
1280 logic alert_cause_46_qs;
1281 logic alert_cause_46_wd;
1282 logic alert_cause_47_we;
1283 logic alert_cause_47_qs;
1284 logic alert_cause_47_wd;
1285 logic alert_cause_48_we;
1286 logic alert_cause_48_qs;
1287 logic alert_cause_48_wd;
1288 logic alert_cause_49_we;
1289 logic alert_cause_49_qs;
1290 logic alert_cause_49_wd;
1291 logic alert_cause_50_we;
1292 logic alert_cause_50_qs;
1293 logic alert_cause_50_wd;
1294 logic alert_cause_51_we;
1295 logic alert_cause_51_qs;
1296 logic alert_cause_51_wd;
1297 logic alert_cause_52_we;
1298 logic alert_cause_52_qs;
1299 logic alert_cause_52_wd;
1300 logic alert_cause_53_we;
1301 logic alert_cause_53_qs;
1302 logic alert_cause_53_wd;
1303 logic alert_cause_54_we;
1304 logic alert_cause_54_qs;
1305 logic alert_cause_54_wd;
1306 logic alert_cause_55_we;
1307 logic alert_cause_55_qs;
1308 logic alert_cause_55_wd;
1309 logic alert_cause_56_we;
1310 logic alert_cause_56_qs;
1311 logic alert_cause_56_wd;
1312 logic alert_cause_57_we;
1313 logic alert_cause_57_qs;
1314 logic alert_cause_57_wd;
1315 logic alert_cause_58_we;
1316 logic alert_cause_58_qs;
1317 logic alert_cause_58_wd;
1318 logic alert_cause_59_we;
1319 logic alert_cause_59_qs;
1320 logic alert_cause_59_wd;
1321 logic alert_cause_60_we;
1322 logic alert_cause_60_qs;
1323 logic alert_cause_60_wd;
1324 logic alert_cause_61_we;
1325 logic alert_cause_61_qs;
1326 logic alert_cause_61_wd;
1327 logic alert_cause_62_we;
1328 logic alert_cause_62_qs;
1329 logic alert_cause_62_wd;
1330 logic alert_cause_63_we;
1331 logic alert_cause_63_qs;
1332 logic alert_cause_63_wd;
1333 logic alert_cause_64_we;
1334 logic alert_cause_64_qs;
1335 logic alert_cause_64_wd;
1336 logic loc_alert_regwen_0_we;
1337 logic loc_alert_regwen_0_qs;
1338 logic loc_alert_regwen_0_wd;
1339 logic loc_alert_regwen_1_we;
1340 logic loc_alert_regwen_1_qs;
1341 logic loc_alert_regwen_1_wd;
1342 logic loc_alert_regwen_2_we;
1343 logic loc_alert_regwen_2_qs;
1344 logic loc_alert_regwen_2_wd;
1345 logic loc_alert_regwen_3_we;
1346 logic loc_alert_regwen_3_qs;
1347 logic loc_alert_regwen_3_wd;
1348 logic loc_alert_regwen_4_we;
1349 logic loc_alert_regwen_4_qs;
1350 logic loc_alert_regwen_4_wd;
1351 logic loc_alert_regwen_5_we;
1352 logic loc_alert_regwen_5_qs;
1353 logic loc_alert_regwen_5_wd;
1354 logic loc_alert_regwen_6_we;
1355 logic loc_alert_regwen_6_qs;
1356 logic loc_alert_regwen_6_wd;
1357 logic loc_alert_en_shadowed_0_re;
1358 logic loc_alert_en_shadowed_0_we;
1359 logic loc_alert_en_shadowed_0_qs;
1360 logic loc_alert_en_shadowed_0_wd;
1361 logic loc_alert_en_shadowed_0_storage_err;
1362 logic loc_alert_en_shadowed_0_update_err;
1363 logic loc_alert_en_shadowed_1_re;
1364 logic loc_alert_en_shadowed_1_we;
1365 logic loc_alert_en_shadowed_1_qs;
1366 logic loc_alert_en_shadowed_1_wd;
1367 logic loc_alert_en_shadowed_1_storage_err;
1368 logic loc_alert_en_shadowed_1_update_err;
1369 logic loc_alert_en_shadowed_2_re;
1370 logic loc_alert_en_shadowed_2_we;
1371 logic loc_alert_en_shadowed_2_qs;
1372 logic loc_alert_en_shadowed_2_wd;
1373 logic loc_alert_en_shadowed_2_storage_err;
1374 logic loc_alert_en_shadowed_2_update_err;
1375 logic loc_alert_en_shadowed_3_re;
1376 logic loc_alert_en_shadowed_3_we;
1377 logic loc_alert_en_shadowed_3_qs;
1378 logic loc_alert_en_shadowed_3_wd;
1379 logic loc_alert_en_shadowed_3_storage_err;
1380 logic loc_alert_en_shadowed_3_update_err;
1381 logic loc_alert_en_shadowed_4_re;
1382 logic loc_alert_en_shadowed_4_we;
1383 logic loc_alert_en_shadowed_4_qs;
1384 logic loc_alert_en_shadowed_4_wd;
1385 logic loc_alert_en_shadowed_4_storage_err;
1386 logic loc_alert_en_shadowed_4_update_err;
1387 logic loc_alert_en_shadowed_5_re;
1388 logic loc_alert_en_shadowed_5_we;
1389 logic loc_alert_en_shadowed_5_qs;
1390 logic loc_alert_en_shadowed_5_wd;
1391 logic loc_alert_en_shadowed_5_storage_err;
1392 logic loc_alert_en_shadowed_5_update_err;
1393 logic loc_alert_en_shadowed_6_re;
1394 logic loc_alert_en_shadowed_6_we;
1395 logic loc_alert_en_shadowed_6_qs;
1396 logic loc_alert_en_shadowed_6_wd;
1397 logic loc_alert_en_shadowed_6_storage_err;
1398 logic loc_alert_en_shadowed_6_update_err;
1399 logic loc_alert_class_shadowed_0_re;
1400 logic loc_alert_class_shadowed_0_we;
1401 logic [1:0] loc_alert_class_shadowed_0_qs;
1402 logic [1:0] loc_alert_class_shadowed_0_wd;
1403 logic loc_alert_class_shadowed_0_storage_err;
1404 logic loc_alert_class_shadowed_0_update_err;
1405 logic loc_alert_class_shadowed_1_re;
1406 logic loc_alert_class_shadowed_1_we;
1407 logic [1:0] loc_alert_class_shadowed_1_qs;
1408 logic [1:0] loc_alert_class_shadowed_1_wd;
1409 logic loc_alert_class_shadowed_1_storage_err;
1410 logic loc_alert_class_shadowed_1_update_err;
1411 logic loc_alert_class_shadowed_2_re;
1412 logic loc_alert_class_shadowed_2_we;
1413 logic [1:0] loc_alert_class_shadowed_2_qs;
1414 logic [1:0] loc_alert_class_shadowed_2_wd;
1415 logic loc_alert_class_shadowed_2_storage_err;
1416 logic loc_alert_class_shadowed_2_update_err;
1417 logic loc_alert_class_shadowed_3_re;
1418 logic loc_alert_class_shadowed_3_we;
1419 logic [1:0] loc_alert_class_shadowed_3_qs;
1420 logic [1:0] loc_alert_class_shadowed_3_wd;
1421 logic loc_alert_class_shadowed_3_storage_err;
1422 logic loc_alert_class_shadowed_3_update_err;
1423 logic loc_alert_class_shadowed_4_re;
1424 logic loc_alert_class_shadowed_4_we;
1425 logic [1:0] loc_alert_class_shadowed_4_qs;
1426 logic [1:0] loc_alert_class_shadowed_4_wd;
1427 logic loc_alert_class_shadowed_4_storage_err;
1428 logic loc_alert_class_shadowed_4_update_err;
1429 logic loc_alert_class_shadowed_5_re;
1430 logic loc_alert_class_shadowed_5_we;
1431 logic [1:0] loc_alert_class_shadowed_5_qs;
1432 logic [1:0] loc_alert_class_shadowed_5_wd;
1433 logic loc_alert_class_shadowed_5_storage_err;
1434 logic loc_alert_class_shadowed_5_update_err;
1435 logic loc_alert_class_shadowed_6_re;
1436 logic loc_alert_class_shadowed_6_we;
1437 logic [1:0] loc_alert_class_shadowed_6_qs;
1438 logic [1:0] loc_alert_class_shadowed_6_wd;
1439 logic loc_alert_class_shadowed_6_storage_err;
1440 logic loc_alert_class_shadowed_6_update_err;
1441 logic loc_alert_cause_0_we;
1442 logic loc_alert_cause_0_qs;
1443 logic loc_alert_cause_0_wd;
1444 logic loc_alert_cause_1_we;
1445 logic loc_alert_cause_1_qs;
1446 logic loc_alert_cause_1_wd;
1447 logic loc_alert_cause_2_we;
1448 logic loc_alert_cause_2_qs;
1449 logic loc_alert_cause_2_wd;
1450 logic loc_alert_cause_3_we;
1451 logic loc_alert_cause_3_qs;
1452 logic loc_alert_cause_3_wd;
1453 logic loc_alert_cause_4_we;
1454 logic loc_alert_cause_4_qs;
1455 logic loc_alert_cause_4_wd;
1456 logic loc_alert_cause_5_we;
1457 logic loc_alert_cause_5_qs;
1458 logic loc_alert_cause_5_wd;
1459 logic loc_alert_cause_6_we;
1460 logic loc_alert_cause_6_qs;
1461 logic loc_alert_cause_6_wd;
1462 logic classa_regwen_we;
1463 logic classa_regwen_qs;
1464 logic classa_regwen_wd;
1465 logic classa_ctrl_shadowed_re;
1466 logic classa_ctrl_shadowed_we;
1467 logic classa_ctrl_shadowed_en_qs;
1468 logic classa_ctrl_shadowed_en_wd;
1469 logic classa_ctrl_shadowed_en_storage_err;
1470 logic classa_ctrl_shadowed_en_update_err;
1471 logic classa_ctrl_shadowed_lock_qs;
1472 logic classa_ctrl_shadowed_lock_wd;
1473 logic classa_ctrl_shadowed_lock_storage_err;
1474 logic classa_ctrl_shadowed_lock_update_err;
1475 logic classa_ctrl_shadowed_en_e0_qs;
1476 logic classa_ctrl_shadowed_en_e0_wd;
1477 logic classa_ctrl_shadowed_en_e0_storage_err;
1478 logic classa_ctrl_shadowed_en_e0_update_err;
1479 logic classa_ctrl_shadowed_en_e1_qs;
1480 logic classa_ctrl_shadowed_en_e1_wd;
1481 logic classa_ctrl_shadowed_en_e1_storage_err;
1482 logic classa_ctrl_shadowed_en_e1_update_err;
1483 logic classa_ctrl_shadowed_en_e2_qs;
1484 logic classa_ctrl_shadowed_en_e2_wd;
1485 logic classa_ctrl_shadowed_en_e2_storage_err;
1486 logic classa_ctrl_shadowed_en_e2_update_err;
1487 logic classa_ctrl_shadowed_en_e3_qs;
1488 logic classa_ctrl_shadowed_en_e3_wd;
1489 logic classa_ctrl_shadowed_en_e3_storage_err;
1490 logic classa_ctrl_shadowed_en_e3_update_err;
1491 logic [1:0] classa_ctrl_shadowed_map_e0_qs;
1492 logic [1:0] classa_ctrl_shadowed_map_e0_wd;
1493 logic classa_ctrl_shadowed_map_e0_storage_err;
1494 logic classa_ctrl_shadowed_map_e0_update_err;
1495 logic [1:0] classa_ctrl_shadowed_map_e1_qs;
1496 logic [1:0] classa_ctrl_shadowed_map_e1_wd;
1497 logic classa_ctrl_shadowed_map_e1_storage_err;
1498 logic classa_ctrl_shadowed_map_e1_update_err;
1499 logic [1:0] classa_ctrl_shadowed_map_e2_qs;
1500 logic [1:0] classa_ctrl_shadowed_map_e2_wd;
1501 logic classa_ctrl_shadowed_map_e2_storage_err;
1502 logic classa_ctrl_shadowed_map_e2_update_err;
1503 logic [1:0] classa_ctrl_shadowed_map_e3_qs;
1504 logic [1:0] classa_ctrl_shadowed_map_e3_wd;
1505 logic classa_ctrl_shadowed_map_e3_storage_err;
1506 logic classa_ctrl_shadowed_map_e3_update_err;
1507 logic classa_clr_regwen_we;
1508 logic classa_clr_regwen_qs;
1509 logic classa_clr_regwen_wd;
1510 logic classa_clr_shadowed_re;
1511 logic classa_clr_shadowed_we;
1512 logic classa_clr_shadowed_qs;
1513 logic classa_clr_shadowed_wd;
1514 logic classa_clr_shadowed_storage_err;
1515 logic classa_clr_shadowed_update_err;
1516 logic classa_accum_cnt_re;
1517 logic [15:0] classa_accum_cnt_qs;
1518 logic classa_accum_thresh_shadowed_re;
1519 logic classa_accum_thresh_shadowed_we;
1520 logic [15:0] classa_accum_thresh_shadowed_qs;
1521 logic [15:0] classa_accum_thresh_shadowed_wd;
1522 logic classa_accum_thresh_shadowed_storage_err;
1523 logic classa_accum_thresh_shadowed_update_err;
1524 logic classa_timeout_cyc_shadowed_re;
1525 logic classa_timeout_cyc_shadowed_we;
1526 logic [31:0] classa_timeout_cyc_shadowed_qs;
1527 logic [31:0] classa_timeout_cyc_shadowed_wd;
1528 logic classa_timeout_cyc_shadowed_storage_err;
1529 logic classa_timeout_cyc_shadowed_update_err;
1530 logic classa_crashdump_trigger_shadowed_re;
1531 logic classa_crashdump_trigger_shadowed_we;
1532 logic [1:0] classa_crashdump_trigger_shadowed_qs;
1533 logic [1:0] classa_crashdump_trigger_shadowed_wd;
1534 logic classa_crashdump_trigger_shadowed_storage_err;
1535 logic classa_crashdump_trigger_shadowed_update_err;
1536 logic classa_phase0_cyc_shadowed_re;
1537 logic classa_phase0_cyc_shadowed_we;
1538 logic [31:0] classa_phase0_cyc_shadowed_qs;
1539 logic [31:0] classa_phase0_cyc_shadowed_wd;
1540 logic classa_phase0_cyc_shadowed_storage_err;
1541 logic classa_phase0_cyc_shadowed_update_err;
1542 logic classa_phase1_cyc_shadowed_re;
1543 logic classa_phase1_cyc_shadowed_we;
1544 logic [31:0] classa_phase1_cyc_shadowed_qs;
1545 logic [31:0] classa_phase1_cyc_shadowed_wd;
1546 logic classa_phase1_cyc_shadowed_storage_err;
1547 logic classa_phase1_cyc_shadowed_update_err;
1548 logic classa_phase2_cyc_shadowed_re;
1549 logic classa_phase2_cyc_shadowed_we;
1550 logic [31:0] classa_phase2_cyc_shadowed_qs;
1551 logic [31:0] classa_phase2_cyc_shadowed_wd;
1552 logic classa_phase2_cyc_shadowed_storage_err;
1553 logic classa_phase2_cyc_shadowed_update_err;
1554 logic classa_phase3_cyc_shadowed_re;
1555 logic classa_phase3_cyc_shadowed_we;
1556 logic [31:0] classa_phase3_cyc_shadowed_qs;
1557 logic [31:0] classa_phase3_cyc_shadowed_wd;
1558 logic classa_phase3_cyc_shadowed_storage_err;
1559 logic classa_phase3_cyc_shadowed_update_err;
1560 logic classa_esc_cnt_re;
1561 logic [31:0] classa_esc_cnt_qs;
1562 logic classa_state_re;
1563 logic [2:0] classa_state_qs;
1564 logic classb_regwen_we;
1565 logic classb_regwen_qs;
1566 logic classb_regwen_wd;
1567 logic classb_ctrl_shadowed_re;
1568 logic classb_ctrl_shadowed_we;
1569 logic classb_ctrl_shadowed_en_qs;
1570 logic classb_ctrl_shadowed_en_wd;
1571 logic classb_ctrl_shadowed_en_storage_err;
1572 logic classb_ctrl_shadowed_en_update_err;
1573 logic classb_ctrl_shadowed_lock_qs;
1574 logic classb_ctrl_shadowed_lock_wd;
1575 logic classb_ctrl_shadowed_lock_storage_err;
1576 logic classb_ctrl_shadowed_lock_update_err;
1577 logic classb_ctrl_shadowed_en_e0_qs;
1578 logic classb_ctrl_shadowed_en_e0_wd;
1579 logic classb_ctrl_shadowed_en_e0_storage_err;
1580 logic classb_ctrl_shadowed_en_e0_update_err;
1581 logic classb_ctrl_shadowed_en_e1_qs;
1582 logic classb_ctrl_shadowed_en_e1_wd;
1583 logic classb_ctrl_shadowed_en_e1_storage_err;
1584 logic classb_ctrl_shadowed_en_e1_update_err;
1585 logic classb_ctrl_shadowed_en_e2_qs;
1586 logic classb_ctrl_shadowed_en_e2_wd;
1587 logic classb_ctrl_shadowed_en_e2_storage_err;
1588 logic classb_ctrl_shadowed_en_e2_update_err;
1589 logic classb_ctrl_shadowed_en_e3_qs;
1590 logic classb_ctrl_shadowed_en_e3_wd;
1591 logic classb_ctrl_shadowed_en_e3_storage_err;
1592 logic classb_ctrl_shadowed_en_e3_update_err;
1593 logic [1:0] classb_ctrl_shadowed_map_e0_qs;
1594 logic [1:0] classb_ctrl_shadowed_map_e0_wd;
1595 logic classb_ctrl_shadowed_map_e0_storage_err;
1596 logic classb_ctrl_shadowed_map_e0_update_err;
1597 logic [1:0] classb_ctrl_shadowed_map_e1_qs;
1598 logic [1:0] classb_ctrl_shadowed_map_e1_wd;
1599 logic classb_ctrl_shadowed_map_e1_storage_err;
1600 logic classb_ctrl_shadowed_map_e1_update_err;
1601 logic [1:0] classb_ctrl_shadowed_map_e2_qs;
1602 logic [1:0] classb_ctrl_shadowed_map_e2_wd;
1603 logic classb_ctrl_shadowed_map_e2_storage_err;
1604 logic classb_ctrl_shadowed_map_e2_update_err;
1605 logic [1:0] classb_ctrl_shadowed_map_e3_qs;
1606 logic [1:0] classb_ctrl_shadowed_map_e3_wd;
1607 logic classb_ctrl_shadowed_map_e3_storage_err;
1608 logic classb_ctrl_shadowed_map_e3_update_err;
1609 logic classb_clr_regwen_we;
1610 logic classb_clr_regwen_qs;
1611 logic classb_clr_regwen_wd;
1612 logic classb_clr_shadowed_re;
1613 logic classb_clr_shadowed_we;
1614 logic classb_clr_shadowed_qs;
1615 logic classb_clr_shadowed_wd;
1616 logic classb_clr_shadowed_storage_err;
1617 logic classb_clr_shadowed_update_err;
1618 logic classb_accum_cnt_re;
1619 logic [15:0] classb_accum_cnt_qs;
1620 logic classb_accum_thresh_shadowed_re;
1621 logic classb_accum_thresh_shadowed_we;
1622 logic [15:0] classb_accum_thresh_shadowed_qs;
1623 logic [15:0] classb_accum_thresh_shadowed_wd;
1624 logic classb_accum_thresh_shadowed_storage_err;
1625 logic classb_accum_thresh_shadowed_update_err;
1626 logic classb_timeout_cyc_shadowed_re;
1627 logic classb_timeout_cyc_shadowed_we;
1628 logic [31:0] classb_timeout_cyc_shadowed_qs;
1629 logic [31:0] classb_timeout_cyc_shadowed_wd;
1630 logic classb_timeout_cyc_shadowed_storage_err;
1631 logic classb_timeout_cyc_shadowed_update_err;
1632 logic classb_crashdump_trigger_shadowed_re;
1633 logic classb_crashdump_trigger_shadowed_we;
1634 logic [1:0] classb_crashdump_trigger_shadowed_qs;
1635 logic [1:0] classb_crashdump_trigger_shadowed_wd;
1636 logic classb_crashdump_trigger_shadowed_storage_err;
1637 logic classb_crashdump_trigger_shadowed_update_err;
1638 logic classb_phase0_cyc_shadowed_re;
1639 logic classb_phase0_cyc_shadowed_we;
1640 logic [31:0] classb_phase0_cyc_shadowed_qs;
1641 logic [31:0] classb_phase0_cyc_shadowed_wd;
1642 logic classb_phase0_cyc_shadowed_storage_err;
1643 logic classb_phase0_cyc_shadowed_update_err;
1644 logic classb_phase1_cyc_shadowed_re;
1645 logic classb_phase1_cyc_shadowed_we;
1646 logic [31:0] classb_phase1_cyc_shadowed_qs;
1647 logic [31:0] classb_phase1_cyc_shadowed_wd;
1648 logic classb_phase1_cyc_shadowed_storage_err;
1649 logic classb_phase1_cyc_shadowed_update_err;
1650 logic classb_phase2_cyc_shadowed_re;
1651 logic classb_phase2_cyc_shadowed_we;
1652 logic [31:0] classb_phase2_cyc_shadowed_qs;
1653 logic [31:0] classb_phase2_cyc_shadowed_wd;
1654 logic classb_phase2_cyc_shadowed_storage_err;
1655 logic classb_phase2_cyc_shadowed_update_err;
1656 logic classb_phase3_cyc_shadowed_re;
1657 logic classb_phase3_cyc_shadowed_we;
1658 logic [31:0] classb_phase3_cyc_shadowed_qs;
1659 logic [31:0] classb_phase3_cyc_shadowed_wd;
1660 logic classb_phase3_cyc_shadowed_storage_err;
1661 logic classb_phase3_cyc_shadowed_update_err;
1662 logic classb_esc_cnt_re;
1663 logic [31:0] classb_esc_cnt_qs;
1664 logic classb_state_re;
1665 logic [2:0] classb_state_qs;
1666 logic classc_regwen_we;
1667 logic classc_regwen_qs;
1668 logic classc_regwen_wd;
1669 logic classc_ctrl_shadowed_re;
1670 logic classc_ctrl_shadowed_we;
1671 logic classc_ctrl_shadowed_en_qs;
1672 logic classc_ctrl_shadowed_en_wd;
1673 logic classc_ctrl_shadowed_en_storage_err;
1674 logic classc_ctrl_shadowed_en_update_err;
1675 logic classc_ctrl_shadowed_lock_qs;
1676 logic classc_ctrl_shadowed_lock_wd;
1677 logic classc_ctrl_shadowed_lock_storage_err;
1678 logic classc_ctrl_shadowed_lock_update_err;
1679 logic classc_ctrl_shadowed_en_e0_qs;
1680 logic classc_ctrl_shadowed_en_e0_wd;
1681 logic classc_ctrl_shadowed_en_e0_storage_err;
1682 logic classc_ctrl_shadowed_en_e0_update_err;
1683 logic classc_ctrl_shadowed_en_e1_qs;
1684 logic classc_ctrl_shadowed_en_e1_wd;
1685 logic classc_ctrl_shadowed_en_e1_storage_err;
1686 logic classc_ctrl_shadowed_en_e1_update_err;
1687 logic classc_ctrl_shadowed_en_e2_qs;
1688 logic classc_ctrl_shadowed_en_e2_wd;
1689 logic classc_ctrl_shadowed_en_e2_storage_err;
1690 logic classc_ctrl_shadowed_en_e2_update_err;
1691 logic classc_ctrl_shadowed_en_e3_qs;
1692 logic classc_ctrl_shadowed_en_e3_wd;
1693 logic classc_ctrl_shadowed_en_e3_storage_err;
1694 logic classc_ctrl_shadowed_en_e3_update_err;
1695 logic [1:0] classc_ctrl_shadowed_map_e0_qs;
1696 logic [1:0] classc_ctrl_shadowed_map_e0_wd;
1697 logic classc_ctrl_shadowed_map_e0_storage_err;
1698 logic classc_ctrl_shadowed_map_e0_update_err;
1699 logic [1:0] classc_ctrl_shadowed_map_e1_qs;
1700 logic [1:0] classc_ctrl_shadowed_map_e1_wd;
1701 logic classc_ctrl_shadowed_map_e1_storage_err;
1702 logic classc_ctrl_shadowed_map_e1_update_err;
1703 logic [1:0] classc_ctrl_shadowed_map_e2_qs;
1704 logic [1:0] classc_ctrl_shadowed_map_e2_wd;
1705 logic classc_ctrl_shadowed_map_e2_storage_err;
1706 logic classc_ctrl_shadowed_map_e2_update_err;
1707 logic [1:0] classc_ctrl_shadowed_map_e3_qs;
1708 logic [1:0] classc_ctrl_shadowed_map_e3_wd;
1709 logic classc_ctrl_shadowed_map_e3_storage_err;
1710 logic classc_ctrl_shadowed_map_e3_update_err;
1711 logic classc_clr_regwen_we;
1712 logic classc_clr_regwen_qs;
1713 logic classc_clr_regwen_wd;
1714 logic classc_clr_shadowed_re;
1715 logic classc_clr_shadowed_we;
1716 logic classc_clr_shadowed_qs;
1717 logic classc_clr_shadowed_wd;
1718 logic classc_clr_shadowed_storage_err;
1719 logic classc_clr_shadowed_update_err;
1720 logic classc_accum_cnt_re;
1721 logic [15:0] classc_accum_cnt_qs;
1722 logic classc_accum_thresh_shadowed_re;
1723 logic classc_accum_thresh_shadowed_we;
1724 logic [15:0] classc_accum_thresh_shadowed_qs;
1725 logic [15:0] classc_accum_thresh_shadowed_wd;
1726 logic classc_accum_thresh_shadowed_storage_err;
1727 logic classc_accum_thresh_shadowed_update_err;
1728 logic classc_timeout_cyc_shadowed_re;
1729 logic classc_timeout_cyc_shadowed_we;
1730 logic [31:0] classc_timeout_cyc_shadowed_qs;
1731 logic [31:0] classc_timeout_cyc_shadowed_wd;
1732 logic classc_timeout_cyc_shadowed_storage_err;
1733 logic classc_timeout_cyc_shadowed_update_err;
1734 logic classc_crashdump_trigger_shadowed_re;
1735 logic classc_crashdump_trigger_shadowed_we;
1736 logic [1:0] classc_crashdump_trigger_shadowed_qs;
1737 logic [1:0] classc_crashdump_trigger_shadowed_wd;
1738 logic classc_crashdump_trigger_shadowed_storage_err;
1739 logic classc_crashdump_trigger_shadowed_update_err;
1740 logic classc_phase0_cyc_shadowed_re;
1741 logic classc_phase0_cyc_shadowed_we;
1742 logic [31:0] classc_phase0_cyc_shadowed_qs;
1743 logic [31:0] classc_phase0_cyc_shadowed_wd;
1744 logic classc_phase0_cyc_shadowed_storage_err;
1745 logic classc_phase0_cyc_shadowed_update_err;
1746 logic classc_phase1_cyc_shadowed_re;
1747 logic classc_phase1_cyc_shadowed_we;
1748 logic [31:0] classc_phase1_cyc_shadowed_qs;
1749 logic [31:0] classc_phase1_cyc_shadowed_wd;
1750 logic classc_phase1_cyc_shadowed_storage_err;
1751 logic classc_phase1_cyc_shadowed_update_err;
1752 logic classc_phase2_cyc_shadowed_re;
1753 logic classc_phase2_cyc_shadowed_we;
1754 logic [31:0] classc_phase2_cyc_shadowed_qs;
1755 logic [31:0] classc_phase2_cyc_shadowed_wd;
1756 logic classc_phase2_cyc_shadowed_storage_err;
1757 logic classc_phase2_cyc_shadowed_update_err;
1758 logic classc_phase3_cyc_shadowed_re;
1759 logic classc_phase3_cyc_shadowed_we;
1760 logic [31:0] classc_phase3_cyc_shadowed_qs;
1761 logic [31:0] classc_phase3_cyc_shadowed_wd;
1762 logic classc_phase3_cyc_shadowed_storage_err;
1763 logic classc_phase3_cyc_shadowed_update_err;
1764 logic classc_esc_cnt_re;
1765 logic [31:0] classc_esc_cnt_qs;
1766 logic classc_state_re;
1767 logic [2:0] classc_state_qs;
1768 logic classd_regwen_we;
1769 logic classd_regwen_qs;
1770 logic classd_regwen_wd;
1771 logic classd_ctrl_shadowed_re;
1772 logic classd_ctrl_shadowed_we;
1773 logic classd_ctrl_shadowed_en_qs;
1774 logic classd_ctrl_shadowed_en_wd;
1775 logic classd_ctrl_shadowed_en_storage_err;
1776 logic classd_ctrl_shadowed_en_update_err;
1777 logic classd_ctrl_shadowed_lock_qs;
1778 logic classd_ctrl_shadowed_lock_wd;
1779 logic classd_ctrl_shadowed_lock_storage_err;
1780 logic classd_ctrl_shadowed_lock_update_err;
1781 logic classd_ctrl_shadowed_en_e0_qs;
1782 logic classd_ctrl_shadowed_en_e0_wd;
1783 logic classd_ctrl_shadowed_en_e0_storage_err;
1784 logic classd_ctrl_shadowed_en_e0_update_err;
1785 logic classd_ctrl_shadowed_en_e1_qs;
1786 logic classd_ctrl_shadowed_en_e1_wd;
1787 logic classd_ctrl_shadowed_en_e1_storage_err;
1788 logic classd_ctrl_shadowed_en_e1_update_err;
1789 logic classd_ctrl_shadowed_en_e2_qs;
1790 logic classd_ctrl_shadowed_en_e2_wd;
1791 logic classd_ctrl_shadowed_en_e2_storage_err;
1792 logic classd_ctrl_shadowed_en_e2_update_err;
1793 logic classd_ctrl_shadowed_en_e3_qs;
1794 logic classd_ctrl_shadowed_en_e3_wd;
1795 logic classd_ctrl_shadowed_en_e3_storage_err;
1796 logic classd_ctrl_shadowed_en_e3_update_err;
1797 logic [1:0] classd_ctrl_shadowed_map_e0_qs;
1798 logic [1:0] classd_ctrl_shadowed_map_e0_wd;
1799 logic classd_ctrl_shadowed_map_e0_storage_err;
1800 logic classd_ctrl_shadowed_map_e0_update_err;
1801 logic [1:0] classd_ctrl_shadowed_map_e1_qs;
1802 logic [1:0] classd_ctrl_shadowed_map_e1_wd;
1803 logic classd_ctrl_shadowed_map_e1_storage_err;
1804 logic classd_ctrl_shadowed_map_e1_update_err;
1805 logic [1:0] classd_ctrl_shadowed_map_e2_qs;
1806 logic [1:0] classd_ctrl_shadowed_map_e2_wd;
1807 logic classd_ctrl_shadowed_map_e2_storage_err;
1808 logic classd_ctrl_shadowed_map_e2_update_err;
1809 logic [1:0] classd_ctrl_shadowed_map_e3_qs;
1810 logic [1:0] classd_ctrl_shadowed_map_e3_wd;
1811 logic classd_ctrl_shadowed_map_e3_storage_err;
1812 logic classd_ctrl_shadowed_map_e3_update_err;
1813 logic classd_clr_regwen_we;
1814 logic classd_clr_regwen_qs;
1815 logic classd_clr_regwen_wd;
1816 logic classd_clr_shadowed_re;
1817 logic classd_clr_shadowed_we;
1818 logic classd_clr_shadowed_qs;
1819 logic classd_clr_shadowed_wd;
1820 logic classd_clr_shadowed_storage_err;
1821 logic classd_clr_shadowed_update_err;
1822 logic classd_accum_cnt_re;
1823 logic [15:0] classd_accum_cnt_qs;
1824 logic classd_accum_thresh_shadowed_re;
1825 logic classd_accum_thresh_shadowed_we;
1826 logic [15:0] classd_accum_thresh_shadowed_qs;
1827 logic [15:0] classd_accum_thresh_shadowed_wd;
1828 logic classd_accum_thresh_shadowed_storage_err;
1829 logic classd_accum_thresh_shadowed_update_err;
1830 logic classd_timeout_cyc_shadowed_re;
1831 logic classd_timeout_cyc_shadowed_we;
1832 logic [31:0] classd_timeout_cyc_shadowed_qs;
1833 logic [31:0] classd_timeout_cyc_shadowed_wd;
1834 logic classd_timeout_cyc_shadowed_storage_err;
1835 logic classd_timeout_cyc_shadowed_update_err;
1836 logic classd_crashdump_trigger_shadowed_re;
1837 logic classd_crashdump_trigger_shadowed_we;
1838 logic [1:0] classd_crashdump_trigger_shadowed_qs;
1839 logic [1:0] classd_crashdump_trigger_shadowed_wd;
1840 logic classd_crashdump_trigger_shadowed_storage_err;
1841 logic classd_crashdump_trigger_shadowed_update_err;
1842 logic classd_phase0_cyc_shadowed_re;
1843 logic classd_phase0_cyc_shadowed_we;
1844 logic [31:0] classd_phase0_cyc_shadowed_qs;
1845 logic [31:0] classd_phase0_cyc_shadowed_wd;
1846 logic classd_phase0_cyc_shadowed_storage_err;
1847 logic classd_phase0_cyc_shadowed_update_err;
1848 logic classd_phase1_cyc_shadowed_re;
1849 logic classd_phase1_cyc_shadowed_we;
1850 logic [31:0] classd_phase1_cyc_shadowed_qs;
1851 logic [31:0] classd_phase1_cyc_shadowed_wd;
1852 logic classd_phase1_cyc_shadowed_storage_err;
1853 logic classd_phase1_cyc_shadowed_update_err;
1854 logic classd_phase2_cyc_shadowed_re;
1855 logic classd_phase2_cyc_shadowed_we;
1856 logic [31:0] classd_phase2_cyc_shadowed_qs;
1857 logic [31:0] classd_phase2_cyc_shadowed_wd;
1858 logic classd_phase2_cyc_shadowed_storage_err;
1859 logic classd_phase2_cyc_shadowed_update_err;
1860 logic classd_phase3_cyc_shadowed_re;
1861 logic classd_phase3_cyc_shadowed_we;
1862 logic [31:0] classd_phase3_cyc_shadowed_qs;
1863 logic [31:0] classd_phase3_cyc_shadowed_wd;
1864 logic classd_phase3_cyc_shadowed_storage_err;
1865 logic classd_phase3_cyc_shadowed_update_err;
1866 logic classd_esc_cnt_re;
1867 logic [31:0] classd_esc_cnt_qs;
1868 logic classd_state_re;
1869 logic [2:0] classd_state_qs;
1870
1871 // Register instances
1872 // R[intr_state]: V(False)
1873 // F[classa]: 0:0
1874 prim_subreg #(
1875 .DW (1),
1876 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1877 .RESVAL (1'h0),
1878 .Mubi (1'b0)
1879 ) u_intr_state_classa (
1880 .clk_i (clk_i),
1881 .rst_ni (rst_ni),
1882
1883 // from register interface
1884 .we (intr_state_we),
1885 .wd (intr_state_classa_wd),
1886
1887 // from internal hardware
1888 .de (hw2reg.intr_state.classa.de),
1889 .d (hw2reg.intr_state.classa.d),
1890
1891 // to internal hardware
1892 .qe (),
1893 .q (reg2hw.intr_state.classa.q),
1894 .ds (),
1895
1896 // to register interface (read)
1897 .qs (intr_state_classa_qs)
1898 );
1899
1900 // F[classb]: 1:1
1901 prim_subreg #(
1902 .DW (1),
1903 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1904 .RESVAL (1'h0),
1905 .Mubi (1'b0)
1906 ) u_intr_state_classb (
1907 .clk_i (clk_i),
1908 .rst_ni (rst_ni),
1909
1910 // from register interface
1911 .we (intr_state_we),
1912 .wd (intr_state_classb_wd),
1913
1914 // from internal hardware
1915 .de (hw2reg.intr_state.classb.de),
1916 .d (hw2reg.intr_state.classb.d),
1917
1918 // to internal hardware
1919 .qe (),
1920 .q (reg2hw.intr_state.classb.q),
1921 .ds (),
1922
1923 // to register interface (read)
1924 .qs (intr_state_classb_qs)
1925 );
1926
1927 // F[classc]: 2:2
1928 prim_subreg #(
1929 .DW (1),
1930 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1931 .RESVAL (1'h0),
1932 .Mubi (1'b0)
1933 ) u_intr_state_classc (
1934 .clk_i (clk_i),
1935 .rst_ni (rst_ni),
1936
1937 // from register interface
1938 .we (intr_state_we),
1939 .wd (intr_state_classc_wd),
1940
1941 // from internal hardware
1942 .de (hw2reg.intr_state.classc.de),
1943 .d (hw2reg.intr_state.classc.d),
1944
1945 // to internal hardware
1946 .qe (),
1947 .q (reg2hw.intr_state.classc.q),
1948 .ds (),
1949
1950 // to register interface (read)
1951 .qs (intr_state_classc_qs)
1952 );
1953
1954 // F[classd]: 3:3
1955 prim_subreg #(
1956 .DW (1),
1957 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1958 .RESVAL (1'h0),
1959 .Mubi (1'b0)
1960 ) u_intr_state_classd (
1961 .clk_i (clk_i),
1962 .rst_ni (rst_ni),
1963
1964 // from register interface
1965 .we (intr_state_we),
1966 .wd (intr_state_classd_wd),
1967
1968 // from internal hardware
1969 .de (hw2reg.intr_state.classd.de),
1970 .d (hw2reg.intr_state.classd.d),
1971
1972 // to internal hardware
1973 .qe (),
1974 .q (reg2hw.intr_state.classd.q),
1975 .ds (),
1976
1977 // to register interface (read)
1978 .qs (intr_state_classd_qs)
1979 );
1980
1981
1982 // R[intr_enable]: V(False)
1983 // F[classa]: 0:0
1984 prim_subreg #(
1985 .DW (1),
1986 .SwAccess(prim_subreg_pkg::SwAccessRW),
1987 .RESVAL (1'h0),
1988 .Mubi (1'b0)
1989 ) u_intr_enable_classa (
1990 .clk_i (clk_i),
1991 .rst_ni (rst_ni),
1992
1993 // from register interface
1994 .we (intr_enable_we),
1995 .wd (intr_enable_classa_wd),
1996
1997 // from internal hardware
1998 .de (1'b0),
1999 .d ('0),
2000
2001 // to internal hardware
2002 .qe (),
2003 .q (reg2hw.intr_enable.classa.q),
2004 .ds (),
2005
2006 // to register interface (read)
2007 .qs (intr_enable_classa_qs)
2008 );
2009
2010 // F[classb]: 1:1
2011 prim_subreg #(
2012 .DW (1),
2013 .SwAccess(prim_subreg_pkg::SwAccessRW),
2014 .RESVAL (1'h0),
2015 .Mubi (1'b0)
2016 ) u_intr_enable_classb (
2017 .clk_i (clk_i),
2018 .rst_ni (rst_ni),
2019
2020 // from register interface
2021 .we (intr_enable_we),
2022 .wd (intr_enable_classb_wd),
2023
2024 // from internal hardware
2025 .de (1'b0),
2026 .d ('0),
2027
2028 // to internal hardware
2029 .qe (),
2030 .q (reg2hw.intr_enable.classb.q),
2031 .ds (),
2032
2033 // to register interface (read)
2034 .qs (intr_enable_classb_qs)
2035 );
2036
2037 // F[classc]: 2:2
2038 prim_subreg #(
2039 .DW (1),
2040 .SwAccess(prim_subreg_pkg::SwAccessRW),
2041 .RESVAL (1'h0),
2042 .Mubi (1'b0)
2043 ) u_intr_enable_classc (
2044 .clk_i (clk_i),
2045 .rst_ni (rst_ni),
2046
2047 // from register interface
2048 .we (intr_enable_we),
2049 .wd (intr_enable_classc_wd),
2050
2051 // from internal hardware
2052 .de (1'b0),
2053 .d ('0),
2054
2055 // to internal hardware
2056 .qe (),
2057 .q (reg2hw.intr_enable.classc.q),
2058 .ds (),
2059
2060 // to register interface (read)
2061 .qs (intr_enable_classc_qs)
2062 );
2063
2064 // F[classd]: 3:3
2065 prim_subreg #(
2066 .DW (1),
2067 .SwAccess(prim_subreg_pkg::SwAccessRW),
2068 .RESVAL (1'h0),
2069 .Mubi (1'b0)
2070 ) u_intr_enable_classd (
2071 .clk_i (clk_i),
2072 .rst_ni (rst_ni),
2073
2074 // from register interface
2075 .we (intr_enable_we),
2076 .wd (intr_enable_classd_wd),
2077
2078 // from internal hardware
2079 .de (1'b0),
2080 .d ('0),
2081
2082 // to internal hardware
2083 .qe (),
2084 .q (reg2hw.intr_enable.classd.q),
2085 .ds (),
2086
2087 // to register interface (read)
2088 .qs (intr_enable_classd_qs)
2089 );
2090
2091
2092 // R[intr_test]: V(True)
2093 logic intr_test_qe;
2094 logic [3:0] intr_test_flds_we;
2095 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T37 T43 T33
2096 // F[classa]: 0:0
2097 prim_subreg_ext #(
2098 .DW (1)
2099 ) u_intr_test_classa (
2100 .re (1'b0),
2101 .we (intr_test_we),
2102 .wd (intr_test_classa_wd),
2103 .d ('0),
2104 .qre (),
2105 .qe (intr_test_flds_we[0]),
2106 .q (reg2hw.intr_test.classa.q),
2107 .ds (),
2108 .qs ()
2109 );
2110 1/1 assign reg2hw.intr_test.classa.qe = intr_test_qe;
Tests: T37 T43 T33
2111
2112 // F[classb]: 1:1
2113 prim_subreg_ext #(
2114 .DW (1)
2115 ) u_intr_test_classb (
2116 .re (1'b0),
2117 .we (intr_test_we),
2118 .wd (intr_test_classb_wd),
2119 .d ('0),
2120 .qre (),
2121 .qe (intr_test_flds_we[1]),
2122 .q (reg2hw.intr_test.classb.q),
2123 .ds (),
2124 .qs ()
2125 );
2126 1/1 assign reg2hw.intr_test.classb.qe = intr_test_qe;
Tests: T37 T43 T33
2127
2128 // F[classc]: 2:2
2129 prim_subreg_ext #(
2130 .DW (1)
2131 ) u_intr_test_classc (
2132 .re (1'b0),
2133 .we (intr_test_we),
2134 .wd (intr_test_classc_wd),
2135 .d ('0),
2136 .qre (),
2137 .qe (intr_test_flds_we[2]),
2138 .q (reg2hw.intr_test.classc.q),
2139 .ds (),
2140 .qs ()
2141 );
2142 1/1 assign reg2hw.intr_test.classc.qe = intr_test_qe;
Tests: T37 T43 T33
2143
2144 // F[classd]: 3:3
2145 prim_subreg_ext #(
2146 .DW (1)
2147 ) u_intr_test_classd (
2148 .re (1'b0),
2149 .we (intr_test_we),
2150 .wd (intr_test_classd_wd),
2151 .d ('0),
2152 .qre (),
2153 .qe (intr_test_flds_we[3]),
2154 .q (reg2hw.intr_test.classd.q),
2155 .ds (),
2156 .qs ()
2157 );
2158 1/1 assign reg2hw.intr_test.classd.qe = intr_test_qe;
Tests: T37 T43 T33
2159
2160
2161 // R[ping_timer_regwen]: V(False)
2162 prim_subreg #(
2163 .DW (1),
2164 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2165 .RESVAL (1'h1),
2166 .Mubi (1'b0)
2167 ) u_ping_timer_regwen (
2168 .clk_i (clk_i),
2169 .rst_ni (rst_ni),
2170
2171 // from register interface
2172 .we (ping_timer_regwen_we),
2173 .wd (ping_timer_regwen_wd),
2174
2175 // from internal hardware
2176 .de (1'b0),
2177 .d ('0),
2178
2179 // to internal hardware
2180 .qe (),
2181 .q (),
2182 .ds (),
2183
2184 // to register interface (read)
2185 .qs (ping_timer_regwen_qs)
2186 );
2187
2188
2189 // R[ping_timeout_cyc_shadowed]: V(False)
2190 // Create REGWEN-gated WE signal
2191 logic ping_timeout_cyc_shadowed_gated_we;
2192 1/1 assign ping_timeout_cyc_shadowed_gated_we = ping_timeout_cyc_shadowed_we & ping_timer_regwen_qs;
Tests: T1 T2 T3
2193 prim_subreg_shadow #(
2194 .DW (16),
2195 .SwAccess(prim_subreg_pkg::SwAccessRW),
2196 .RESVAL (16'h100),
2197 .Mubi (1'b0)
2198 ) u_ping_timeout_cyc_shadowed (
2199 .clk_i (clk_i),
2200 .rst_ni (rst_ni),
2201 .rst_shadowed_ni (rst_shadowed_ni),
2202
2203 // from register interface
2204 .re (ping_timeout_cyc_shadowed_re),
2205 .we (ping_timeout_cyc_shadowed_gated_we),
2206 .wd (ping_timeout_cyc_shadowed_wd),
2207
2208 // from internal hardware
2209 .de (1'b0),
2210 .d ('0),
2211
2212 // to internal hardware
2213 .qe (),
2214 .q (reg2hw.ping_timeout_cyc_shadowed.q),
2215 .ds (),
2216
2217 // to register interface (read)
2218 .qs (ping_timeout_cyc_shadowed_qs),
2219
2220 // Shadow register phase. Relevant for hwext only.
2221 .phase (),
2222
2223 // Shadow register error conditions
2224 .err_update (ping_timeout_cyc_shadowed_update_err),
2225 .err_storage (ping_timeout_cyc_shadowed_storage_err)
2226 );
2227
2228
2229 // R[ping_timer_en_shadowed]: V(False)
2230 // Create REGWEN-gated WE signal
2231 logic ping_timer_en_shadowed_gated_we;
2232 1/1 assign ping_timer_en_shadowed_gated_we = ping_timer_en_shadowed_we & ping_timer_regwen_qs;
Tests: T1 T2 T3
2233 prim_subreg_shadow #(
2234 .DW (1),
2235 .SwAccess(prim_subreg_pkg::SwAccessW1S),
2236 .RESVAL (1'h0),
2237 .Mubi (1'b0)
2238 ) u_ping_timer_en_shadowed (
2239 .clk_i (clk_i),
2240 .rst_ni (rst_ni),
2241 .rst_shadowed_ni (rst_shadowed_ni),
2242
2243 // from register interface
2244 .re (ping_timer_en_shadowed_re),
2245 .we (ping_timer_en_shadowed_gated_we),
2246 .wd (ping_timer_en_shadowed_wd),
2247
2248 // from internal hardware
2249 .de (1'b0),
2250 .d ('0),
2251
2252 // to internal hardware
2253 .qe (),
2254 .q (reg2hw.ping_timer_en_shadowed.q),
2255 .ds (),
2256
2257 // to register interface (read)
2258 .qs (ping_timer_en_shadowed_qs),
2259
2260 // Shadow register phase. Relevant for hwext only.
2261 .phase (),
2262
2263 // Shadow register error conditions
2264 .err_update (ping_timer_en_shadowed_update_err),
2265 .err_storage (ping_timer_en_shadowed_storage_err)
2266 );
2267
2268
2269 // Subregister 0 of Multireg alert_regwen
2270 // R[alert_regwen_0]: V(False)
2271 prim_subreg #(
2272 .DW (1),
2273 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2274 .RESVAL (1'h1),
2275 .Mubi (1'b0)
2276 ) u_alert_regwen_0 (
2277 .clk_i (clk_i),
2278 .rst_ni (rst_ni),
2279
2280 // from register interface
2281 .we (alert_regwen_0_we),
2282 .wd (alert_regwen_0_wd),
2283
2284 // from internal hardware
2285 .de (1'b0),
2286 .d ('0),
2287
2288 // to internal hardware
2289 .qe (),
2290 .q (reg2hw.alert_regwen[0].q),
2291 .ds (),
2292
2293 // to register interface (read)
2294 .qs (alert_regwen_0_qs)
2295 );
2296
2297
2298 // Subregister 1 of Multireg alert_regwen
2299 // R[alert_regwen_1]: V(False)
2300 prim_subreg #(
2301 .DW (1),
2302 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2303 .RESVAL (1'h1),
2304 .Mubi (1'b0)
2305 ) u_alert_regwen_1 (
2306 .clk_i (clk_i),
2307 .rst_ni (rst_ni),
2308
2309 // from register interface
2310 .we (alert_regwen_1_we),
2311 .wd (alert_regwen_1_wd),
2312
2313 // from internal hardware
2314 .de (1'b0),
2315 .d ('0),
2316
2317 // to internal hardware
2318 .qe (),
2319 .q (reg2hw.alert_regwen[1].q),
2320 .ds (),
2321
2322 // to register interface (read)
2323 .qs (alert_regwen_1_qs)
2324 );
2325
2326
2327 // Subregister 2 of Multireg alert_regwen
2328 // R[alert_regwen_2]: V(False)
2329 prim_subreg #(
2330 .DW (1),
2331 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2332 .RESVAL (1'h1),
2333 .Mubi (1'b0)
2334 ) u_alert_regwen_2 (
2335 .clk_i (clk_i),
2336 .rst_ni (rst_ni),
2337
2338 // from register interface
2339 .we (alert_regwen_2_we),
2340 .wd (alert_regwen_2_wd),
2341
2342 // from internal hardware
2343 .de (1'b0),
2344 .d ('0),
2345
2346 // to internal hardware
2347 .qe (),
2348 .q (reg2hw.alert_regwen[2].q),
2349 .ds (),
2350
2351 // to register interface (read)
2352 .qs (alert_regwen_2_qs)
2353 );
2354
2355
2356 // Subregister 3 of Multireg alert_regwen
2357 // R[alert_regwen_3]: V(False)
2358 prim_subreg #(
2359 .DW (1),
2360 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2361 .RESVAL (1'h1),
2362 .Mubi (1'b0)
2363 ) u_alert_regwen_3 (
2364 .clk_i (clk_i),
2365 .rst_ni (rst_ni),
2366
2367 // from register interface
2368 .we (alert_regwen_3_we),
2369 .wd (alert_regwen_3_wd),
2370
2371 // from internal hardware
2372 .de (1'b0),
2373 .d ('0),
2374
2375 // to internal hardware
2376 .qe (),
2377 .q (reg2hw.alert_regwen[3].q),
2378 .ds (),
2379
2380 // to register interface (read)
2381 .qs (alert_regwen_3_qs)
2382 );
2383
2384
2385 // Subregister 4 of Multireg alert_regwen
2386 // R[alert_regwen_4]: V(False)
2387 prim_subreg #(
2388 .DW (1),
2389 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2390 .RESVAL (1'h1),
2391 .Mubi (1'b0)
2392 ) u_alert_regwen_4 (
2393 .clk_i (clk_i),
2394 .rst_ni (rst_ni),
2395
2396 // from register interface
2397 .we (alert_regwen_4_we),
2398 .wd (alert_regwen_4_wd),
2399
2400 // from internal hardware
2401 .de (1'b0),
2402 .d ('0),
2403
2404 // to internal hardware
2405 .qe (),
2406 .q (reg2hw.alert_regwen[4].q),
2407 .ds (),
2408
2409 // to register interface (read)
2410 .qs (alert_regwen_4_qs)
2411 );
2412
2413
2414 // Subregister 5 of Multireg alert_regwen
2415 // R[alert_regwen_5]: V(False)
2416 prim_subreg #(
2417 .DW (1),
2418 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2419 .RESVAL (1'h1),
2420 .Mubi (1'b0)
2421 ) u_alert_regwen_5 (
2422 .clk_i (clk_i),
2423 .rst_ni (rst_ni),
2424
2425 // from register interface
2426 .we (alert_regwen_5_we),
2427 .wd (alert_regwen_5_wd),
2428
2429 // from internal hardware
2430 .de (1'b0),
2431 .d ('0),
2432
2433 // to internal hardware
2434 .qe (),
2435 .q (reg2hw.alert_regwen[5].q),
2436 .ds (),
2437
2438 // to register interface (read)
2439 .qs (alert_regwen_5_qs)
2440 );
2441
2442
2443 // Subregister 6 of Multireg alert_regwen
2444 // R[alert_regwen_6]: V(False)
2445 prim_subreg #(
2446 .DW (1),
2447 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2448 .RESVAL (1'h1),
2449 .Mubi (1'b0)
2450 ) u_alert_regwen_6 (
2451 .clk_i (clk_i),
2452 .rst_ni (rst_ni),
2453
2454 // from register interface
2455 .we (alert_regwen_6_we),
2456 .wd (alert_regwen_6_wd),
2457
2458 // from internal hardware
2459 .de (1'b0),
2460 .d ('0),
2461
2462 // to internal hardware
2463 .qe (),
2464 .q (reg2hw.alert_regwen[6].q),
2465 .ds (),
2466
2467 // to register interface (read)
2468 .qs (alert_regwen_6_qs)
2469 );
2470
2471
2472 // Subregister 7 of Multireg alert_regwen
2473 // R[alert_regwen_7]: V(False)
2474 prim_subreg #(
2475 .DW (1),
2476 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2477 .RESVAL (1'h1),
2478 .Mubi (1'b0)
2479 ) u_alert_regwen_7 (
2480 .clk_i (clk_i),
2481 .rst_ni (rst_ni),
2482
2483 // from register interface
2484 .we (alert_regwen_7_we),
2485 .wd (alert_regwen_7_wd),
2486
2487 // from internal hardware
2488 .de (1'b0),
2489 .d ('0),
2490
2491 // to internal hardware
2492 .qe (),
2493 .q (reg2hw.alert_regwen[7].q),
2494 .ds (),
2495
2496 // to register interface (read)
2497 .qs (alert_regwen_7_qs)
2498 );
2499
2500
2501 // Subregister 8 of Multireg alert_regwen
2502 // R[alert_regwen_8]: V(False)
2503 prim_subreg #(
2504 .DW (1),
2505 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2506 .RESVAL (1'h1),
2507 .Mubi (1'b0)
2508 ) u_alert_regwen_8 (
2509 .clk_i (clk_i),
2510 .rst_ni (rst_ni),
2511
2512 // from register interface
2513 .we (alert_regwen_8_we),
2514 .wd (alert_regwen_8_wd),
2515
2516 // from internal hardware
2517 .de (1'b0),
2518 .d ('0),
2519
2520 // to internal hardware
2521 .qe (),
2522 .q (reg2hw.alert_regwen[8].q),
2523 .ds (),
2524
2525 // to register interface (read)
2526 .qs (alert_regwen_8_qs)
2527 );
2528
2529
2530 // Subregister 9 of Multireg alert_regwen
2531 // R[alert_regwen_9]: V(False)
2532 prim_subreg #(
2533 .DW (1),
2534 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2535 .RESVAL (1'h1),
2536 .Mubi (1'b0)
2537 ) u_alert_regwen_9 (
2538 .clk_i (clk_i),
2539 .rst_ni (rst_ni),
2540
2541 // from register interface
2542 .we (alert_regwen_9_we),
2543 .wd (alert_regwen_9_wd),
2544
2545 // from internal hardware
2546 .de (1'b0),
2547 .d ('0),
2548
2549 // to internal hardware
2550 .qe (),
2551 .q (reg2hw.alert_regwen[9].q),
2552 .ds (),
2553
2554 // to register interface (read)
2555 .qs (alert_regwen_9_qs)
2556 );
2557
2558
2559 // Subregister 10 of Multireg alert_regwen
2560 // R[alert_regwen_10]: V(False)
2561 prim_subreg #(
2562 .DW (1),
2563 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2564 .RESVAL (1'h1),
2565 .Mubi (1'b0)
2566 ) u_alert_regwen_10 (
2567 .clk_i (clk_i),
2568 .rst_ni (rst_ni),
2569
2570 // from register interface
2571 .we (alert_regwen_10_we),
2572 .wd (alert_regwen_10_wd),
2573
2574 // from internal hardware
2575 .de (1'b0),
2576 .d ('0),
2577
2578 // to internal hardware
2579 .qe (),
2580 .q (reg2hw.alert_regwen[10].q),
2581 .ds (),
2582
2583 // to register interface (read)
2584 .qs (alert_regwen_10_qs)
2585 );
2586
2587
2588 // Subregister 11 of Multireg alert_regwen
2589 // R[alert_regwen_11]: V(False)
2590 prim_subreg #(
2591 .DW (1),
2592 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2593 .RESVAL (1'h1),
2594 .Mubi (1'b0)
2595 ) u_alert_regwen_11 (
2596 .clk_i (clk_i),
2597 .rst_ni (rst_ni),
2598
2599 // from register interface
2600 .we (alert_regwen_11_we),
2601 .wd (alert_regwen_11_wd),
2602
2603 // from internal hardware
2604 .de (1'b0),
2605 .d ('0),
2606
2607 // to internal hardware
2608 .qe (),
2609 .q (reg2hw.alert_regwen[11].q),
2610 .ds (),
2611
2612 // to register interface (read)
2613 .qs (alert_regwen_11_qs)
2614 );
2615
2616
2617 // Subregister 12 of Multireg alert_regwen
2618 // R[alert_regwen_12]: V(False)
2619 prim_subreg #(
2620 .DW (1),
2621 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2622 .RESVAL (1'h1),
2623 .Mubi (1'b0)
2624 ) u_alert_regwen_12 (
2625 .clk_i (clk_i),
2626 .rst_ni (rst_ni),
2627
2628 // from register interface
2629 .we (alert_regwen_12_we),
2630 .wd (alert_regwen_12_wd),
2631
2632 // from internal hardware
2633 .de (1'b0),
2634 .d ('0),
2635
2636 // to internal hardware
2637 .qe (),
2638 .q (reg2hw.alert_regwen[12].q),
2639 .ds (),
2640
2641 // to register interface (read)
2642 .qs (alert_regwen_12_qs)
2643 );
2644
2645
2646 // Subregister 13 of Multireg alert_regwen
2647 // R[alert_regwen_13]: V(False)
2648 prim_subreg #(
2649 .DW (1),
2650 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2651 .RESVAL (1'h1),
2652 .Mubi (1'b0)
2653 ) u_alert_regwen_13 (
2654 .clk_i (clk_i),
2655 .rst_ni (rst_ni),
2656
2657 // from register interface
2658 .we (alert_regwen_13_we),
2659 .wd (alert_regwen_13_wd),
2660
2661 // from internal hardware
2662 .de (1'b0),
2663 .d ('0),
2664
2665 // to internal hardware
2666 .qe (),
2667 .q (reg2hw.alert_regwen[13].q),
2668 .ds (),
2669
2670 // to register interface (read)
2671 .qs (alert_regwen_13_qs)
2672 );
2673
2674
2675 // Subregister 14 of Multireg alert_regwen
2676 // R[alert_regwen_14]: V(False)
2677 prim_subreg #(
2678 .DW (1),
2679 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2680 .RESVAL (1'h1),
2681 .Mubi (1'b0)
2682 ) u_alert_regwen_14 (
2683 .clk_i (clk_i),
2684 .rst_ni (rst_ni),
2685
2686 // from register interface
2687 .we (alert_regwen_14_we),
2688 .wd (alert_regwen_14_wd),
2689
2690 // from internal hardware
2691 .de (1'b0),
2692 .d ('0),
2693
2694 // to internal hardware
2695 .qe (),
2696 .q (reg2hw.alert_regwen[14].q),
2697 .ds (),
2698
2699 // to register interface (read)
2700 .qs (alert_regwen_14_qs)
2701 );
2702
2703
2704 // Subregister 15 of Multireg alert_regwen
2705 // R[alert_regwen_15]: V(False)
2706 prim_subreg #(
2707 .DW (1),
2708 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2709 .RESVAL (1'h1),
2710 .Mubi (1'b0)
2711 ) u_alert_regwen_15 (
2712 .clk_i (clk_i),
2713 .rst_ni (rst_ni),
2714
2715 // from register interface
2716 .we (alert_regwen_15_we),
2717 .wd (alert_regwen_15_wd),
2718
2719 // from internal hardware
2720 .de (1'b0),
2721 .d ('0),
2722
2723 // to internal hardware
2724 .qe (),
2725 .q (reg2hw.alert_regwen[15].q),
2726 .ds (),
2727
2728 // to register interface (read)
2729 .qs (alert_regwen_15_qs)
2730 );
2731
2732
2733 // Subregister 16 of Multireg alert_regwen
2734 // R[alert_regwen_16]: V(False)
2735 prim_subreg #(
2736 .DW (1),
2737 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2738 .RESVAL (1'h1),
2739 .Mubi (1'b0)
2740 ) u_alert_regwen_16 (
2741 .clk_i (clk_i),
2742 .rst_ni (rst_ni),
2743
2744 // from register interface
2745 .we (alert_regwen_16_we),
2746 .wd (alert_regwen_16_wd),
2747
2748 // from internal hardware
2749 .de (1'b0),
2750 .d ('0),
2751
2752 // to internal hardware
2753 .qe (),
2754 .q (reg2hw.alert_regwen[16].q),
2755 .ds (),
2756
2757 // to register interface (read)
2758 .qs (alert_regwen_16_qs)
2759 );
2760
2761
2762 // Subregister 17 of Multireg alert_regwen
2763 // R[alert_regwen_17]: V(False)
2764 prim_subreg #(
2765 .DW (1),
2766 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2767 .RESVAL (1'h1),
2768 .Mubi (1'b0)
2769 ) u_alert_regwen_17 (
2770 .clk_i (clk_i),
2771 .rst_ni (rst_ni),
2772
2773 // from register interface
2774 .we (alert_regwen_17_we),
2775 .wd (alert_regwen_17_wd),
2776
2777 // from internal hardware
2778 .de (1'b0),
2779 .d ('0),
2780
2781 // to internal hardware
2782 .qe (),
2783 .q (reg2hw.alert_regwen[17].q),
2784 .ds (),
2785
2786 // to register interface (read)
2787 .qs (alert_regwen_17_qs)
2788 );
2789
2790
2791 // Subregister 18 of Multireg alert_regwen
2792 // R[alert_regwen_18]: V(False)
2793 prim_subreg #(
2794 .DW (1),
2795 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2796 .RESVAL (1'h1),
2797 .Mubi (1'b0)
2798 ) u_alert_regwen_18 (
2799 .clk_i (clk_i),
2800 .rst_ni (rst_ni),
2801
2802 // from register interface
2803 .we (alert_regwen_18_we),
2804 .wd (alert_regwen_18_wd),
2805
2806 // from internal hardware
2807 .de (1'b0),
2808 .d ('0),
2809
2810 // to internal hardware
2811 .qe (),
2812 .q (reg2hw.alert_regwen[18].q),
2813 .ds (),
2814
2815 // to register interface (read)
2816 .qs (alert_regwen_18_qs)
2817 );
2818
2819
2820 // Subregister 19 of Multireg alert_regwen
2821 // R[alert_regwen_19]: V(False)
2822 prim_subreg #(
2823 .DW (1),
2824 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2825 .RESVAL (1'h1),
2826 .Mubi (1'b0)
2827 ) u_alert_regwen_19 (
2828 .clk_i (clk_i),
2829 .rst_ni (rst_ni),
2830
2831 // from register interface
2832 .we (alert_regwen_19_we),
2833 .wd (alert_regwen_19_wd),
2834
2835 // from internal hardware
2836 .de (1'b0),
2837 .d ('0),
2838
2839 // to internal hardware
2840 .qe (),
2841 .q (reg2hw.alert_regwen[19].q),
2842 .ds (),
2843
2844 // to register interface (read)
2845 .qs (alert_regwen_19_qs)
2846 );
2847
2848
2849 // Subregister 20 of Multireg alert_regwen
2850 // R[alert_regwen_20]: V(False)
2851 prim_subreg #(
2852 .DW (1),
2853 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2854 .RESVAL (1'h1),
2855 .Mubi (1'b0)
2856 ) u_alert_regwen_20 (
2857 .clk_i (clk_i),
2858 .rst_ni (rst_ni),
2859
2860 // from register interface
2861 .we (alert_regwen_20_we),
2862 .wd (alert_regwen_20_wd),
2863
2864 // from internal hardware
2865 .de (1'b0),
2866 .d ('0),
2867
2868 // to internal hardware
2869 .qe (),
2870 .q (reg2hw.alert_regwen[20].q),
2871 .ds (),
2872
2873 // to register interface (read)
2874 .qs (alert_regwen_20_qs)
2875 );
2876
2877
2878 // Subregister 21 of Multireg alert_regwen
2879 // R[alert_regwen_21]: V(False)
2880 prim_subreg #(
2881 .DW (1),
2882 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2883 .RESVAL (1'h1),
2884 .Mubi (1'b0)
2885 ) u_alert_regwen_21 (
2886 .clk_i (clk_i),
2887 .rst_ni (rst_ni),
2888
2889 // from register interface
2890 .we (alert_regwen_21_we),
2891 .wd (alert_regwen_21_wd),
2892
2893 // from internal hardware
2894 .de (1'b0),
2895 .d ('0),
2896
2897 // to internal hardware
2898 .qe (),
2899 .q (reg2hw.alert_regwen[21].q),
2900 .ds (),
2901
2902 // to register interface (read)
2903 .qs (alert_regwen_21_qs)
2904 );
2905
2906
2907 // Subregister 22 of Multireg alert_regwen
2908 // R[alert_regwen_22]: V(False)
2909 prim_subreg #(
2910 .DW (1),
2911 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2912 .RESVAL (1'h1),
2913 .Mubi (1'b0)
2914 ) u_alert_regwen_22 (
2915 .clk_i (clk_i),
2916 .rst_ni (rst_ni),
2917
2918 // from register interface
2919 .we (alert_regwen_22_we),
2920 .wd (alert_regwen_22_wd),
2921
2922 // from internal hardware
2923 .de (1'b0),
2924 .d ('0),
2925
2926 // to internal hardware
2927 .qe (),
2928 .q (reg2hw.alert_regwen[22].q),
2929 .ds (),
2930
2931 // to register interface (read)
2932 .qs (alert_regwen_22_qs)
2933 );
2934
2935
2936 // Subregister 23 of Multireg alert_regwen
2937 // R[alert_regwen_23]: V(False)
2938 prim_subreg #(
2939 .DW (1),
2940 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2941 .RESVAL (1'h1),
2942 .Mubi (1'b0)
2943 ) u_alert_regwen_23 (
2944 .clk_i (clk_i),
2945 .rst_ni (rst_ni),
2946
2947 // from register interface
2948 .we (alert_regwen_23_we),
2949 .wd (alert_regwen_23_wd),
2950
2951 // from internal hardware
2952 .de (1'b0),
2953 .d ('0),
2954
2955 // to internal hardware
2956 .qe (),
2957 .q (reg2hw.alert_regwen[23].q),
2958 .ds (),
2959
2960 // to register interface (read)
2961 .qs (alert_regwen_23_qs)
2962 );
2963
2964
2965 // Subregister 24 of Multireg alert_regwen
2966 // R[alert_regwen_24]: V(False)
2967 prim_subreg #(
2968 .DW (1),
2969 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2970 .RESVAL (1'h1),
2971 .Mubi (1'b0)
2972 ) u_alert_regwen_24 (
2973 .clk_i (clk_i),
2974 .rst_ni (rst_ni),
2975
2976 // from register interface
2977 .we (alert_regwen_24_we),
2978 .wd (alert_regwen_24_wd),
2979
2980 // from internal hardware
2981 .de (1'b0),
2982 .d ('0),
2983
2984 // to internal hardware
2985 .qe (),
2986 .q (reg2hw.alert_regwen[24].q),
2987 .ds (),
2988
2989 // to register interface (read)
2990 .qs (alert_regwen_24_qs)
2991 );
2992
2993
2994 // Subregister 25 of Multireg alert_regwen
2995 // R[alert_regwen_25]: V(False)
2996 prim_subreg #(
2997 .DW (1),
2998 .SwAccess(prim_subreg_pkg::SwAccessW0C),
2999 .RESVAL (1'h1),
3000 .Mubi (1'b0)
3001 ) u_alert_regwen_25 (
3002 .clk_i (clk_i),
3003 .rst_ni (rst_ni),
3004
3005 // from register interface
3006 .we (alert_regwen_25_we),
3007 .wd (alert_regwen_25_wd),
3008
3009 // from internal hardware
3010 .de (1'b0),
3011 .d ('0),
3012
3013 // to internal hardware
3014 .qe (),
3015 .q (reg2hw.alert_regwen[25].q),
3016 .ds (),
3017
3018 // to register interface (read)
3019 .qs (alert_regwen_25_qs)
3020 );
3021
3022
3023 // Subregister 26 of Multireg alert_regwen
3024 // R[alert_regwen_26]: V(False)
3025 prim_subreg #(
3026 .DW (1),
3027 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3028 .RESVAL (1'h1),
3029 .Mubi (1'b0)
3030 ) u_alert_regwen_26 (
3031 .clk_i (clk_i),
3032 .rst_ni (rst_ni),
3033
3034 // from register interface
3035 .we (alert_regwen_26_we),
3036 .wd (alert_regwen_26_wd),
3037
3038 // from internal hardware
3039 .de (1'b0),
3040 .d ('0),
3041
3042 // to internal hardware
3043 .qe (),
3044 .q (reg2hw.alert_regwen[26].q),
3045 .ds (),
3046
3047 // to register interface (read)
3048 .qs (alert_regwen_26_qs)
3049 );
3050
3051
3052 // Subregister 27 of Multireg alert_regwen
3053 // R[alert_regwen_27]: V(False)
3054 prim_subreg #(
3055 .DW (1),
3056 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3057 .RESVAL (1'h1),
3058 .Mubi (1'b0)
3059 ) u_alert_regwen_27 (
3060 .clk_i (clk_i),
3061 .rst_ni (rst_ni),
3062
3063 // from register interface
3064 .we (alert_regwen_27_we),
3065 .wd (alert_regwen_27_wd),
3066
3067 // from internal hardware
3068 .de (1'b0),
3069 .d ('0),
3070
3071 // to internal hardware
3072 .qe (),
3073 .q (reg2hw.alert_regwen[27].q),
3074 .ds (),
3075
3076 // to register interface (read)
3077 .qs (alert_regwen_27_qs)
3078 );
3079
3080
3081 // Subregister 28 of Multireg alert_regwen
3082 // R[alert_regwen_28]: V(False)
3083 prim_subreg #(
3084 .DW (1),
3085 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3086 .RESVAL (1'h1),
3087 .Mubi (1'b0)
3088 ) u_alert_regwen_28 (
3089 .clk_i (clk_i),
3090 .rst_ni (rst_ni),
3091
3092 // from register interface
3093 .we (alert_regwen_28_we),
3094 .wd (alert_regwen_28_wd),
3095
3096 // from internal hardware
3097 .de (1'b0),
3098 .d ('0),
3099
3100 // to internal hardware
3101 .qe (),
3102 .q (reg2hw.alert_regwen[28].q),
3103 .ds (),
3104
3105 // to register interface (read)
3106 .qs (alert_regwen_28_qs)
3107 );
3108
3109
3110 // Subregister 29 of Multireg alert_regwen
3111 // R[alert_regwen_29]: V(False)
3112 prim_subreg #(
3113 .DW (1),
3114 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3115 .RESVAL (1'h1),
3116 .Mubi (1'b0)
3117 ) u_alert_regwen_29 (
3118 .clk_i (clk_i),
3119 .rst_ni (rst_ni),
3120
3121 // from register interface
3122 .we (alert_regwen_29_we),
3123 .wd (alert_regwen_29_wd),
3124
3125 // from internal hardware
3126 .de (1'b0),
3127 .d ('0),
3128
3129 // to internal hardware
3130 .qe (),
3131 .q (reg2hw.alert_regwen[29].q),
3132 .ds (),
3133
3134 // to register interface (read)
3135 .qs (alert_regwen_29_qs)
3136 );
3137
3138
3139 // Subregister 30 of Multireg alert_regwen
3140 // R[alert_regwen_30]: V(False)
3141 prim_subreg #(
3142 .DW (1),
3143 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3144 .RESVAL (1'h1),
3145 .Mubi (1'b0)
3146 ) u_alert_regwen_30 (
3147 .clk_i (clk_i),
3148 .rst_ni (rst_ni),
3149
3150 // from register interface
3151 .we (alert_regwen_30_we),
3152 .wd (alert_regwen_30_wd),
3153
3154 // from internal hardware
3155 .de (1'b0),
3156 .d ('0),
3157
3158 // to internal hardware
3159 .qe (),
3160 .q (reg2hw.alert_regwen[30].q),
3161 .ds (),
3162
3163 // to register interface (read)
3164 .qs (alert_regwen_30_qs)
3165 );
3166
3167
3168 // Subregister 31 of Multireg alert_regwen
3169 // R[alert_regwen_31]: V(False)
3170 prim_subreg #(
3171 .DW (1),
3172 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3173 .RESVAL (1'h1),
3174 .Mubi (1'b0)
3175 ) u_alert_regwen_31 (
3176 .clk_i (clk_i),
3177 .rst_ni (rst_ni),
3178
3179 // from register interface
3180 .we (alert_regwen_31_we),
3181 .wd (alert_regwen_31_wd),
3182
3183 // from internal hardware
3184 .de (1'b0),
3185 .d ('0),
3186
3187 // to internal hardware
3188 .qe (),
3189 .q (reg2hw.alert_regwen[31].q),
3190 .ds (),
3191
3192 // to register interface (read)
3193 .qs (alert_regwen_31_qs)
3194 );
3195
3196
3197 // Subregister 32 of Multireg alert_regwen
3198 // R[alert_regwen_32]: V(False)
3199 prim_subreg #(
3200 .DW (1),
3201 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3202 .RESVAL (1'h1),
3203 .Mubi (1'b0)
3204 ) u_alert_regwen_32 (
3205 .clk_i (clk_i),
3206 .rst_ni (rst_ni),
3207
3208 // from register interface
3209 .we (alert_regwen_32_we),
3210 .wd (alert_regwen_32_wd),
3211
3212 // from internal hardware
3213 .de (1'b0),
3214 .d ('0),
3215
3216 // to internal hardware
3217 .qe (),
3218 .q (reg2hw.alert_regwen[32].q),
3219 .ds (),
3220
3221 // to register interface (read)
3222 .qs (alert_regwen_32_qs)
3223 );
3224
3225
3226 // Subregister 33 of Multireg alert_regwen
3227 // R[alert_regwen_33]: V(False)
3228 prim_subreg #(
3229 .DW (1),
3230 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3231 .RESVAL (1'h1),
3232 .Mubi (1'b0)
3233 ) u_alert_regwen_33 (
3234 .clk_i (clk_i),
3235 .rst_ni (rst_ni),
3236
3237 // from register interface
3238 .we (alert_regwen_33_we),
3239 .wd (alert_regwen_33_wd),
3240
3241 // from internal hardware
3242 .de (1'b0),
3243 .d ('0),
3244
3245 // to internal hardware
3246 .qe (),
3247 .q (reg2hw.alert_regwen[33].q),
3248 .ds (),
3249
3250 // to register interface (read)
3251 .qs (alert_regwen_33_qs)
3252 );
3253
3254
3255 // Subregister 34 of Multireg alert_regwen
3256 // R[alert_regwen_34]: V(False)
3257 prim_subreg #(
3258 .DW (1),
3259 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3260 .RESVAL (1'h1),
3261 .Mubi (1'b0)
3262 ) u_alert_regwen_34 (
3263 .clk_i (clk_i),
3264 .rst_ni (rst_ni),
3265
3266 // from register interface
3267 .we (alert_regwen_34_we),
3268 .wd (alert_regwen_34_wd),
3269
3270 // from internal hardware
3271 .de (1'b0),
3272 .d ('0),
3273
3274 // to internal hardware
3275 .qe (),
3276 .q (reg2hw.alert_regwen[34].q),
3277 .ds (),
3278
3279 // to register interface (read)
3280 .qs (alert_regwen_34_qs)
3281 );
3282
3283
3284 // Subregister 35 of Multireg alert_regwen
3285 // R[alert_regwen_35]: V(False)
3286 prim_subreg #(
3287 .DW (1),
3288 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3289 .RESVAL (1'h1),
3290 .Mubi (1'b0)
3291 ) u_alert_regwen_35 (
3292 .clk_i (clk_i),
3293 .rst_ni (rst_ni),
3294
3295 // from register interface
3296 .we (alert_regwen_35_we),
3297 .wd (alert_regwen_35_wd),
3298
3299 // from internal hardware
3300 .de (1'b0),
3301 .d ('0),
3302
3303 // to internal hardware
3304 .qe (),
3305 .q (reg2hw.alert_regwen[35].q),
3306 .ds (),
3307
3308 // to register interface (read)
3309 .qs (alert_regwen_35_qs)
3310 );
3311
3312
3313 // Subregister 36 of Multireg alert_regwen
3314 // R[alert_regwen_36]: V(False)
3315 prim_subreg #(
3316 .DW (1),
3317 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3318 .RESVAL (1'h1),
3319 .Mubi (1'b0)
3320 ) u_alert_regwen_36 (
3321 .clk_i (clk_i),
3322 .rst_ni (rst_ni),
3323
3324 // from register interface
3325 .we (alert_regwen_36_we),
3326 .wd (alert_regwen_36_wd),
3327
3328 // from internal hardware
3329 .de (1'b0),
3330 .d ('0),
3331
3332 // to internal hardware
3333 .qe (),
3334 .q (reg2hw.alert_regwen[36].q),
3335 .ds (),
3336
3337 // to register interface (read)
3338 .qs (alert_regwen_36_qs)
3339 );
3340
3341
3342 // Subregister 37 of Multireg alert_regwen
3343 // R[alert_regwen_37]: V(False)
3344 prim_subreg #(
3345 .DW (1),
3346 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3347 .RESVAL (1'h1),
3348 .Mubi (1'b0)
3349 ) u_alert_regwen_37 (
3350 .clk_i (clk_i),
3351 .rst_ni (rst_ni),
3352
3353 // from register interface
3354 .we (alert_regwen_37_we),
3355 .wd (alert_regwen_37_wd),
3356
3357 // from internal hardware
3358 .de (1'b0),
3359 .d ('0),
3360
3361 // to internal hardware
3362 .qe (),
3363 .q (reg2hw.alert_regwen[37].q),
3364 .ds (),
3365
3366 // to register interface (read)
3367 .qs (alert_regwen_37_qs)
3368 );
3369
3370
3371 // Subregister 38 of Multireg alert_regwen
3372 // R[alert_regwen_38]: V(False)
3373 prim_subreg #(
3374 .DW (1),
3375 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3376 .RESVAL (1'h1),
3377 .Mubi (1'b0)
3378 ) u_alert_regwen_38 (
3379 .clk_i (clk_i),
3380 .rst_ni (rst_ni),
3381
3382 // from register interface
3383 .we (alert_regwen_38_we),
3384 .wd (alert_regwen_38_wd),
3385
3386 // from internal hardware
3387 .de (1'b0),
3388 .d ('0),
3389
3390 // to internal hardware
3391 .qe (),
3392 .q (reg2hw.alert_regwen[38].q),
3393 .ds (),
3394
3395 // to register interface (read)
3396 .qs (alert_regwen_38_qs)
3397 );
3398
3399
3400 // Subregister 39 of Multireg alert_regwen
3401 // R[alert_regwen_39]: V(False)
3402 prim_subreg #(
3403 .DW (1),
3404 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3405 .RESVAL (1'h1),
3406 .Mubi (1'b0)
3407 ) u_alert_regwen_39 (
3408 .clk_i (clk_i),
3409 .rst_ni (rst_ni),
3410
3411 // from register interface
3412 .we (alert_regwen_39_we),
3413 .wd (alert_regwen_39_wd),
3414
3415 // from internal hardware
3416 .de (1'b0),
3417 .d ('0),
3418
3419 // to internal hardware
3420 .qe (),
3421 .q (reg2hw.alert_regwen[39].q),
3422 .ds (),
3423
3424 // to register interface (read)
3425 .qs (alert_regwen_39_qs)
3426 );
3427
3428
3429 // Subregister 40 of Multireg alert_regwen
3430 // R[alert_regwen_40]: V(False)
3431 prim_subreg #(
3432 .DW (1),
3433 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3434 .RESVAL (1'h1),
3435 .Mubi (1'b0)
3436 ) u_alert_regwen_40 (
3437 .clk_i (clk_i),
3438 .rst_ni (rst_ni),
3439
3440 // from register interface
3441 .we (alert_regwen_40_we),
3442 .wd (alert_regwen_40_wd),
3443
3444 // from internal hardware
3445 .de (1'b0),
3446 .d ('0),
3447
3448 // to internal hardware
3449 .qe (),
3450 .q (reg2hw.alert_regwen[40].q),
3451 .ds (),
3452
3453 // to register interface (read)
3454 .qs (alert_regwen_40_qs)
3455 );
3456
3457
3458 // Subregister 41 of Multireg alert_regwen
3459 // R[alert_regwen_41]: V(False)
3460 prim_subreg #(
3461 .DW (1),
3462 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3463 .RESVAL (1'h1),
3464 .Mubi (1'b0)
3465 ) u_alert_regwen_41 (
3466 .clk_i (clk_i),
3467 .rst_ni (rst_ni),
3468
3469 // from register interface
3470 .we (alert_regwen_41_we),
3471 .wd (alert_regwen_41_wd),
3472
3473 // from internal hardware
3474 .de (1'b0),
3475 .d ('0),
3476
3477 // to internal hardware
3478 .qe (),
3479 .q (reg2hw.alert_regwen[41].q),
3480 .ds (),
3481
3482 // to register interface (read)
3483 .qs (alert_regwen_41_qs)
3484 );
3485
3486
3487 // Subregister 42 of Multireg alert_regwen
3488 // R[alert_regwen_42]: V(False)
3489 prim_subreg #(
3490 .DW (1),
3491 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3492 .RESVAL (1'h1),
3493 .Mubi (1'b0)
3494 ) u_alert_regwen_42 (
3495 .clk_i (clk_i),
3496 .rst_ni (rst_ni),
3497
3498 // from register interface
3499 .we (alert_regwen_42_we),
3500 .wd (alert_regwen_42_wd),
3501
3502 // from internal hardware
3503 .de (1'b0),
3504 .d ('0),
3505
3506 // to internal hardware
3507 .qe (),
3508 .q (reg2hw.alert_regwen[42].q),
3509 .ds (),
3510
3511 // to register interface (read)
3512 .qs (alert_regwen_42_qs)
3513 );
3514
3515
3516 // Subregister 43 of Multireg alert_regwen
3517 // R[alert_regwen_43]: V(False)
3518 prim_subreg #(
3519 .DW (1),
3520 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3521 .RESVAL (1'h1),
3522 .Mubi (1'b0)
3523 ) u_alert_regwen_43 (
3524 .clk_i (clk_i),
3525 .rst_ni (rst_ni),
3526
3527 // from register interface
3528 .we (alert_regwen_43_we),
3529 .wd (alert_regwen_43_wd),
3530
3531 // from internal hardware
3532 .de (1'b0),
3533 .d ('0),
3534
3535 // to internal hardware
3536 .qe (),
3537 .q (reg2hw.alert_regwen[43].q),
3538 .ds (),
3539
3540 // to register interface (read)
3541 .qs (alert_regwen_43_qs)
3542 );
3543
3544
3545 // Subregister 44 of Multireg alert_regwen
3546 // R[alert_regwen_44]: V(False)
3547 prim_subreg #(
3548 .DW (1),
3549 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3550 .RESVAL (1'h1),
3551 .Mubi (1'b0)
3552 ) u_alert_regwen_44 (
3553 .clk_i (clk_i),
3554 .rst_ni (rst_ni),
3555
3556 // from register interface
3557 .we (alert_regwen_44_we),
3558 .wd (alert_regwen_44_wd),
3559
3560 // from internal hardware
3561 .de (1'b0),
3562 .d ('0),
3563
3564 // to internal hardware
3565 .qe (),
3566 .q (reg2hw.alert_regwen[44].q),
3567 .ds (),
3568
3569 // to register interface (read)
3570 .qs (alert_regwen_44_qs)
3571 );
3572
3573
3574 // Subregister 45 of Multireg alert_regwen
3575 // R[alert_regwen_45]: V(False)
3576 prim_subreg #(
3577 .DW (1),
3578 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3579 .RESVAL (1'h1),
3580 .Mubi (1'b0)
3581 ) u_alert_regwen_45 (
3582 .clk_i (clk_i),
3583 .rst_ni (rst_ni),
3584
3585 // from register interface
3586 .we (alert_regwen_45_we),
3587 .wd (alert_regwen_45_wd),
3588
3589 // from internal hardware
3590 .de (1'b0),
3591 .d ('0),
3592
3593 // to internal hardware
3594 .qe (),
3595 .q (reg2hw.alert_regwen[45].q),
3596 .ds (),
3597
3598 // to register interface (read)
3599 .qs (alert_regwen_45_qs)
3600 );
3601
3602
3603 // Subregister 46 of Multireg alert_regwen
3604 // R[alert_regwen_46]: V(False)
3605 prim_subreg #(
3606 .DW (1),
3607 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3608 .RESVAL (1'h1),
3609 .Mubi (1'b0)
3610 ) u_alert_regwen_46 (
3611 .clk_i (clk_i),
3612 .rst_ni (rst_ni),
3613
3614 // from register interface
3615 .we (alert_regwen_46_we),
3616 .wd (alert_regwen_46_wd),
3617
3618 // from internal hardware
3619 .de (1'b0),
3620 .d ('0),
3621
3622 // to internal hardware
3623 .qe (),
3624 .q (reg2hw.alert_regwen[46].q),
3625 .ds (),
3626
3627 // to register interface (read)
3628 .qs (alert_regwen_46_qs)
3629 );
3630
3631
3632 // Subregister 47 of Multireg alert_regwen
3633 // R[alert_regwen_47]: V(False)
3634 prim_subreg #(
3635 .DW (1),
3636 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3637 .RESVAL (1'h1),
3638 .Mubi (1'b0)
3639 ) u_alert_regwen_47 (
3640 .clk_i (clk_i),
3641 .rst_ni (rst_ni),
3642
3643 // from register interface
3644 .we (alert_regwen_47_we),
3645 .wd (alert_regwen_47_wd),
3646
3647 // from internal hardware
3648 .de (1'b0),
3649 .d ('0),
3650
3651 // to internal hardware
3652 .qe (),
3653 .q (reg2hw.alert_regwen[47].q),
3654 .ds (),
3655
3656 // to register interface (read)
3657 .qs (alert_regwen_47_qs)
3658 );
3659
3660
3661 // Subregister 48 of Multireg alert_regwen
3662 // R[alert_regwen_48]: V(False)
3663 prim_subreg #(
3664 .DW (1),
3665 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3666 .RESVAL (1'h1),
3667 .Mubi (1'b0)
3668 ) u_alert_regwen_48 (
3669 .clk_i (clk_i),
3670 .rst_ni (rst_ni),
3671
3672 // from register interface
3673 .we (alert_regwen_48_we),
3674 .wd (alert_regwen_48_wd),
3675
3676 // from internal hardware
3677 .de (1'b0),
3678 .d ('0),
3679
3680 // to internal hardware
3681 .qe (),
3682 .q (reg2hw.alert_regwen[48].q),
3683 .ds (),
3684
3685 // to register interface (read)
3686 .qs (alert_regwen_48_qs)
3687 );
3688
3689
3690 // Subregister 49 of Multireg alert_regwen
3691 // R[alert_regwen_49]: V(False)
3692 prim_subreg #(
3693 .DW (1),
3694 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3695 .RESVAL (1'h1),
3696 .Mubi (1'b0)
3697 ) u_alert_regwen_49 (
3698 .clk_i (clk_i),
3699 .rst_ni (rst_ni),
3700
3701 // from register interface
3702 .we (alert_regwen_49_we),
3703 .wd (alert_regwen_49_wd),
3704
3705 // from internal hardware
3706 .de (1'b0),
3707 .d ('0),
3708
3709 // to internal hardware
3710 .qe (),
3711 .q (reg2hw.alert_regwen[49].q),
3712 .ds (),
3713
3714 // to register interface (read)
3715 .qs (alert_regwen_49_qs)
3716 );
3717
3718
3719 // Subregister 50 of Multireg alert_regwen
3720 // R[alert_regwen_50]: V(False)
3721 prim_subreg #(
3722 .DW (1),
3723 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3724 .RESVAL (1'h1),
3725 .Mubi (1'b0)
3726 ) u_alert_regwen_50 (
3727 .clk_i (clk_i),
3728 .rst_ni (rst_ni),
3729
3730 // from register interface
3731 .we (alert_regwen_50_we),
3732 .wd (alert_regwen_50_wd),
3733
3734 // from internal hardware
3735 .de (1'b0),
3736 .d ('0),
3737
3738 // to internal hardware
3739 .qe (),
3740 .q (reg2hw.alert_regwen[50].q),
3741 .ds (),
3742
3743 // to register interface (read)
3744 .qs (alert_regwen_50_qs)
3745 );
3746
3747
3748 // Subregister 51 of Multireg alert_regwen
3749 // R[alert_regwen_51]: V(False)
3750 prim_subreg #(
3751 .DW (1),
3752 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3753 .RESVAL (1'h1),
3754 .Mubi (1'b0)
3755 ) u_alert_regwen_51 (
3756 .clk_i (clk_i),
3757 .rst_ni (rst_ni),
3758
3759 // from register interface
3760 .we (alert_regwen_51_we),
3761 .wd (alert_regwen_51_wd),
3762
3763 // from internal hardware
3764 .de (1'b0),
3765 .d ('0),
3766
3767 // to internal hardware
3768 .qe (),
3769 .q (reg2hw.alert_regwen[51].q),
3770 .ds (),
3771
3772 // to register interface (read)
3773 .qs (alert_regwen_51_qs)
3774 );
3775
3776
3777 // Subregister 52 of Multireg alert_regwen
3778 // R[alert_regwen_52]: V(False)
3779 prim_subreg #(
3780 .DW (1),
3781 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3782 .RESVAL (1'h1),
3783 .Mubi (1'b0)
3784 ) u_alert_regwen_52 (
3785 .clk_i (clk_i),
3786 .rst_ni (rst_ni),
3787
3788 // from register interface
3789 .we (alert_regwen_52_we),
3790 .wd (alert_regwen_52_wd),
3791
3792 // from internal hardware
3793 .de (1'b0),
3794 .d ('0),
3795
3796 // to internal hardware
3797 .qe (),
3798 .q (reg2hw.alert_regwen[52].q),
3799 .ds (),
3800
3801 // to register interface (read)
3802 .qs (alert_regwen_52_qs)
3803 );
3804
3805
3806 // Subregister 53 of Multireg alert_regwen
3807 // R[alert_regwen_53]: V(False)
3808 prim_subreg #(
3809 .DW (1),
3810 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3811 .RESVAL (1'h1),
3812 .Mubi (1'b0)
3813 ) u_alert_regwen_53 (
3814 .clk_i (clk_i),
3815 .rst_ni (rst_ni),
3816
3817 // from register interface
3818 .we (alert_regwen_53_we),
3819 .wd (alert_regwen_53_wd),
3820
3821 // from internal hardware
3822 .de (1'b0),
3823 .d ('0),
3824
3825 // to internal hardware
3826 .qe (),
3827 .q (reg2hw.alert_regwen[53].q),
3828 .ds (),
3829
3830 // to register interface (read)
3831 .qs (alert_regwen_53_qs)
3832 );
3833
3834
3835 // Subregister 54 of Multireg alert_regwen
3836 // R[alert_regwen_54]: V(False)
3837 prim_subreg #(
3838 .DW (1),
3839 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3840 .RESVAL (1'h1),
3841 .Mubi (1'b0)
3842 ) u_alert_regwen_54 (
3843 .clk_i (clk_i),
3844 .rst_ni (rst_ni),
3845
3846 // from register interface
3847 .we (alert_regwen_54_we),
3848 .wd (alert_regwen_54_wd),
3849
3850 // from internal hardware
3851 .de (1'b0),
3852 .d ('0),
3853
3854 // to internal hardware
3855 .qe (),
3856 .q (reg2hw.alert_regwen[54].q),
3857 .ds (),
3858
3859 // to register interface (read)
3860 .qs (alert_regwen_54_qs)
3861 );
3862
3863
3864 // Subregister 55 of Multireg alert_regwen
3865 // R[alert_regwen_55]: V(False)
3866 prim_subreg #(
3867 .DW (1),
3868 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3869 .RESVAL (1'h1),
3870 .Mubi (1'b0)
3871 ) u_alert_regwen_55 (
3872 .clk_i (clk_i),
3873 .rst_ni (rst_ni),
3874
3875 // from register interface
3876 .we (alert_regwen_55_we),
3877 .wd (alert_regwen_55_wd),
3878
3879 // from internal hardware
3880 .de (1'b0),
3881 .d ('0),
3882
3883 // to internal hardware
3884 .qe (),
3885 .q (reg2hw.alert_regwen[55].q),
3886 .ds (),
3887
3888 // to register interface (read)
3889 .qs (alert_regwen_55_qs)
3890 );
3891
3892
3893 // Subregister 56 of Multireg alert_regwen
3894 // R[alert_regwen_56]: V(False)
3895 prim_subreg #(
3896 .DW (1),
3897 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3898 .RESVAL (1'h1),
3899 .Mubi (1'b0)
3900 ) u_alert_regwen_56 (
3901 .clk_i (clk_i),
3902 .rst_ni (rst_ni),
3903
3904 // from register interface
3905 .we (alert_regwen_56_we),
3906 .wd (alert_regwen_56_wd),
3907
3908 // from internal hardware
3909 .de (1'b0),
3910 .d ('0),
3911
3912 // to internal hardware
3913 .qe (),
3914 .q (reg2hw.alert_regwen[56].q),
3915 .ds (),
3916
3917 // to register interface (read)
3918 .qs (alert_regwen_56_qs)
3919 );
3920
3921
3922 // Subregister 57 of Multireg alert_regwen
3923 // R[alert_regwen_57]: V(False)
3924 prim_subreg #(
3925 .DW (1),
3926 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3927 .RESVAL (1'h1),
3928 .Mubi (1'b0)
3929 ) u_alert_regwen_57 (
3930 .clk_i (clk_i),
3931 .rst_ni (rst_ni),
3932
3933 // from register interface
3934 .we (alert_regwen_57_we),
3935 .wd (alert_regwen_57_wd),
3936
3937 // from internal hardware
3938 .de (1'b0),
3939 .d ('0),
3940
3941 // to internal hardware
3942 .qe (),
3943 .q (reg2hw.alert_regwen[57].q),
3944 .ds (),
3945
3946 // to register interface (read)
3947 .qs (alert_regwen_57_qs)
3948 );
3949
3950
3951 // Subregister 58 of Multireg alert_regwen
3952 // R[alert_regwen_58]: V(False)
3953 prim_subreg #(
3954 .DW (1),
3955 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3956 .RESVAL (1'h1),
3957 .Mubi (1'b0)
3958 ) u_alert_regwen_58 (
3959 .clk_i (clk_i),
3960 .rst_ni (rst_ni),
3961
3962 // from register interface
3963 .we (alert_regwen_58_we),
3964 .wd (alert_regwen_58_wd),
3965
3966 // from internal hardware
3967 .de (1'b0),
3968 .d ('0),
3969
3970 // to internal hardware
3971 .qe (),
3972 .q (reg2hw.alert_regwen[58].q),
3973 .ds (),
3974
3975 // to register interface (read)
3976 .qs (alert_regwen_58_qs)
3977 );
3978
3979
3980 // Subregister 59 of Multireg alert_regwen
3981 // R[alert_regwen_59]: V(False)
3982 prim_subreg #(
3983 .DW (1),
3984 .SwAccess(prim_subreg_pkg::SwAccessW0C),
3985 .RESVAL (1'h1),
3986 .Mubi (1'b0)
3987 ) u_alert_regwen_59 (
3988 .clk_i (clk_i),
3989 .rst_ni (rst_ni),
3990
3991 // from register interface
3992 .we (alert_regwen_59_we),
3993 .wd (alert_regwen_59_wd),
3994
3995 // from internal hardware
3996 .de (1'b0),
3997 .d ('0),
3998
3999 // to internal hardware
4000 .qe (),
4001 .q (reg2hw.alert_regwen[59].q),
4002 .ds (),
4003
4004 // to register interface (read)
4005 .qs (alert_regwen_59_qs)
4006 );
4007
4008
4009 // Subregister 60 of Multireg alert_regwen
4010 // R[alert_regwen_60]: V(False)
4011 prim_subreg #(
4012 .DW (1),
4013 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4014 .RESVAL (1'h1),
4015 .Mubi (1'b0)
4016 ) u_alert_regwen_60 (
4017 .clk_i (clk_i),
4018 .rst_ni (rst_ni),
4019
4020 // from register interface
4021 .we (alert_regwen_60_we),
4022 .wd (alert_regwen_60_wd),
4023
4024 // from internal hardware
4025 .de (1'b0),
4026 .d ('0),
4027
4028 // to internal hardware
4029 .qe (),
4030 .q (reg2hw.alert_regwen[60].q),
4031 .ds (),
4032
4033 // to register interface (read)
4034 .qs (alert_regwen_60_qs)
4035 );
4036
4037
4038 // Subregister 61 of Multireg alert_regwen
4039 // R[alert_regwen_61]: V(False)
4040 prim_subreg #(
4041 .DW (1),
4042 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4043 .RESVAL (1'h1),
4044 .Mubi (1'b0)
4045 ) u_alert_regwen_61 (
4046 .clk_i (clk_i),
4047 .rst_ni (rst_ni),
4048
4049 // from register interface
4050 .we (alert_regwen_61_we),
4051 .wd (alert_regwen_61_wd),
4052
4053 // from internal hardware
4054 .de (1'b0),
4055 .d ('0),
4056
4057 // to internal hardware
4058 .qe (),
4059 .q (reg2hw.alert_regwen[61].q),
4060 .ds (),
4061
4062 // to register interface (read)
4063 .qs (alert_regwen_61_qs)
4064 );
4065
4066
4067 // Subregister 62 of Multireg alert_regwen
4068 // R[alert_regwen_62]: V(False)
4069 prim_subreg #(
4070 .DW (1),
4071 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4072 .RESVAL (1'h1),
4073 .Mubi (1'b0)
4074 ) u_alert_regwen_62 (
4075 .clk_i (clk_i),
4076 .rst_ni (rst_ni),
4077
4078 // from register interface
4079 .we (alert_regwen_62_we),
4080 .wd (alert_regwen_62_wd),
4081
4082 // from internal hardware
4083 .de (1'b0),
4084 .d ('0),
4085
4086 // to internal hardware
4087 .qe (),
4088 .q (reg2hw.alert_regwen[62].q),
4089 .ds (),
4090
4091 // to register interface (read)
4092 .qs (alert_regwen_62_qs)
4093 );
4094
4095
4096 // Subregister 63 of Multireg alert_regwen
4097 // R[alert_regwen_63]: V(False)
4098 prim_subreg #(
4099 .DW (1),
4100 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4101 .RESVAL (1'h1),
4102 .Mubi (1'b0)
4103 ) u_alert_regwen_63 (
4104 .clk_i (clk_i),
4105 .rst_ni (rst_ni),
4106
4107 // from register interface
4108 .we (alert_regwen_63_we),
4109 .wd (alert_regwen_63_wd),
4110
4111 // from internal hardware
4112 .de (1'b0),
4113 .d ('0),
4114
4115 // to internal hardware
4116 .qe (),
4117 .q (reg2hw.alert_regwen[63].q),
4118 .ds (),
4119
4120 // to register interface (read)
4121 .qs (alert_regwen_63_qs)
4122 );
4123
4124
4125 // Subregister 64 of Multireg alert_regwen
4126 // R[alert_regwen_64]: V(False)
4127 prim_subreg #(
4128 .DW (1),
4129 .SwAccess(prim_subreg_pkg::SwAccessW0C),
4130 .RESVAL (1'h1),
4131 .Mubi (1'b0)
4132 ) u_alert_regwen_64 (
4133 .clk_i (clk_i),
4134 .rst_ni (rst_ni),
4135
4136 // from register interface
4137 .we (alert_regwen_64_we),
4138 .wd (alert_regwen_64_wd),
4139
4140 // from internal hardware
4141 .de (1'b0),
4142 .d ('0),
4143
4144 // to internal hardware
4145 .qe (),
4146 .q (reg2hw.alert_regwen[64].q),
4147 .ds (),
4148
4149 // to register interface (read)
4150 .qs (alert_regwen_64_qs)
4151 );
4152
4153
4154 // Subregister 0 of Multireg alert_en_shadowed
4155 // R[alert_en_shadowed_0]: V(False)
4156 // Create REGWEN-gated WE signal
4157 logic alert_en_shadowed_0_gated_we;
4158 1/1 assign alert_en_shadowed_0_gated_we = alert_en_shadowed_0_we & alert_regwen_0_qs;
Tests: T1 T2 T3
4159 prim_subreg_shadow #(
4160 .DW (1),
4161 .SwAccess(prim_subreg_pkg::SwAccessRW),
4162 .RESVAL (1'h0),
4163 .Mubi (1'b0)
4164 ) u_alert_en_shadowed_0 (
4165 .clk_i (clk_i),
4166 .rst_ni (rst_ni),
4167 .rst_shadowed_ni (rst_shadowed_ni),
4168
4169 // from register interface
4170 .re (alert_en_shadowed_0_re),
4171 .we (alert_en_shadowed_0_gated_we),
4172 .wd (alert_en_shadowed_0_wd),
4173
4174 // from internal hardware
4175 .de (1'b0),
4176 .d ('0),
4177
4178 // to internal hardware
4179 .qe (),
4180 .q (reg2hw.alert_en_shadowed[0].q),
4181 .ds (),
4182
4183 // to register interface (read)
4184 .qs (alert_en_shadowed_0_qs),
4185
4186 // Shadow register phase. Relevant for hwext only.
4187 .phase (),
4188
4189 // Shadow register error conditions
4190 .err_update (alert_en_shadowed_0_update_err),
4191 .err_storage (alert_en_shadowed_0_storage_err)
4192 );
4193
4194
4195 // Subregister 1 of Multireg alert_en_shadowed
4196 // R[alert_en_shadowed_1]: V(False)
4197 // Create REGWEN-gated WE signal
4198 logic alert_en_shadowed_1_gated_we;
4199 1/1 assign alert_en_shadowed_1_gated_we = alert_en_shadowed_1_we & alert_regwen_1_qs;
Tests: T1 T2 T3
4200 prim_subreg_shadow #(
4201 .DW (1),
4202 .SwAccess(prim_subreg_pkg::SwAccessRW),
4203 .RESVAL (1'h0),
4204 .Mubi (1'b0)
4205 ) u_alert_en_shadowed_1 (
4206 .clk_i (clk_i),
4207 .rst_ni (rst_ni),
4208 .rst_shadowed_ni (rst_shadowed_ni),
4209
4210 // from register interface
4211 .re (alert_en_shadowed_1_re),
4212 .we (alert_en_shadowed_1_gated_we),
4213 .wd (alert_en_shadowed_1_wd),
4214
4215 // from internal hardware
4216 .de (1'b0),
4217 .d ('0),
4218
4219 // to internal hardware
4220 .qe (),
4221 .q (reg2hw.alert_en_shadowed[1].q),
4222 .ds (),
4223
4224 // to register interface (read)
4225 .qs (alert_en_shadowed_1_qs),
4226
4227 // Shadow register phase. Relevant for hwext only.
4228 .phase (),
4229
4230 // Shadow register error conditions
4231 .err_update (alert_en_shadowed_1_update_err),
4232 .err_storage (alert_en_shadowed_1_storage_err)
4233 );
4234
4235
4236 // Subregister 2 of Multireg alert_en_shadowed
4237 // R[alert_en_shadowed_2]: V(False)
4238 // Create REGWEN-gated WE signal
4239 logic alert_en_shadowed_2_gated_we;
4240 1/1 assign alert_en_shadowed_2_gated_we = alert_en_shadowed_2_we & alert_regwen_2_qs;
Tests: T1 T2 T3
4241 prim_subreg_shadow #(
4242 .DW (1),
4243 .SwAccess(prim_subreg_pkg::SwAccessRW),
4244 .RESVAL (1'h0),
4245 .Mubi (1'b0)
4246 ) u_alert_en_shadowed_2 (
4247 .clk_i (clk_i),
4248 .rst_ni (rst_ni),
4249 .rst_shadowed_ni (rst_shadowed_ni),
4250
4251 // from register interface
4252 .re (alert_en_shadowed_2_re),
4253 .we (alert_en_shadowed_2_gated_we),
4254 .wd (alert_en_shadowed_2_wd),
4255
4256 // from internal hardware
4257 .de (1'b0),
4258 .d ('0),
4259
4260 // to internal hardware
4261 .qe (),
4262 .q (reg2hw.alert_en_shadowed[2].q),
4263 .ds (),
4264
4265 // to register interface (read)
4266 .qs (alert_en_shadowed_2_qs),
4267
4268 // Shadow register phase. Relevant for hwext only.
4269 .phase (),
4270
4271 // Shadow register error conditions
4272 .err_update (alert_en_shadowed_2_update_err),
4273 .err_storage (alert_en_shadowed_2_storage_err)
4274 );
4275
4276
4277 // Subregister 3 of Multireg alert_en_shadowed
4278 // R[alert_en_shadowed_3]: V(False)
4279 // Create REGWEN-gated WE signal
4280 logic alert_en_shadowed_3_gated_we;
4281 1/1 assign alert_en_shadowed_3_gated_we = alert_en_shadowed_3_we & alert_regwen_3_qs;
Tests: T1 T2 T3
4282 prim_subreg_shadow #(
4283 .DW (1),
4284 .SwAccess(prim_subreg_pkg::SwAccessRW),
4285 .RESVAL (1'h0),
4286 .Mubi (1'b0)
4287 ) u_alert_en_shadowed_3 (
4288 .clk_i (clk_i),
4289 .rst_ni (rst_ni),
4290 .rst_shadowed_ni (rst_shadowed_ni),
4291
4292 // from register interface
4293 .re (alert_en_shadowed_3_re),
4294 .we (alert_en_shadowed_3_gated_we),
4295 .wd (alert_en_shadowed_3_wd),
4296
4297 // from internal hardware
4298 .de (1'b0),
4299 .d ('0),
4300
4301 // to internal hardware
4302 .qe (),
4303 .q (reg2hw.alert_en_shadowed[3].q),
4304 .ds (),
4305
4306 // to register interface (read)
4307 .qs (alert_en_shadowed_3_qs),
4308
4309 // Shadow register phase. Relevant for hwext only.
4310 .phase (),
4311
4312 // Shadow register error conditions
4313 .err_update (alert_en_shadowed_3_update_err),
4314 .err_storage (alert_en_shadowed_3_storage_err)
4315 );
4316
4317
4318 // Subregister 4 of Multireg alert_en_shadowed
4319 // R[alert_en_shadowed_4]: V(False)
4320 // Create REGWEN-gated WE signal
4321 logic alert_en_shadowed_4_gated_we;
4322 1/1 assign alert_en_shadowed_4_gated_we = alert_en_shadowed_4_we & alert_regwen_4_qs;
Tests: T1 T2 T3
4323 prim_subreg_shadow #(
4324 .DW (1),
4325 .SwAccess(prim_subreg_pkg::SwAccessRW),
4326 .RESVAL (1'h0),
4327 .Mubi (1'b0)
4328 ) u_alert_en_shadowed_4 (
4329 .clk_i (clk_i),
4330 .rst_ni (rst_ni),
4331 .rst_shadowed_ni (rst_shadowed_ni),
4332
4333 // from register interface
4334 .re (alert_en_shadowed_4_re),
4335 .we (alert_en_shadowed_4_gated_we),
4336 .wd (alert_en_shadowed_4_wd),
4337
4338 // from internal hardware
4339 .de (1'b0),
4340 .d ('0),
4341
4342 // to internal hardware
4343 .qe (),
4344 .q (reg2hw.alert_en_shadowed[4].q),
4345 .ds (),
4346
4347 // to register interface (read)
4348 .qs (alert_en_shadowed_4_qs),
4349
4350 // Shadow register phase. Relevant for hwext only.
4351 .phase (),
4352
4353 // Shadow register error conditions
4354 .err_update (alert_en_shadowed_4_update_err),
4355 .err_storage (alert_en_shadowed_4_storage_err)
4356 );
4357
4358
4359 // Subregister 5 of Multireg alert_en_shadowed
4360 // R[alert_en_shadowed_5]: V(False)
4361 // Create REGWEN-gated WE signal
4362 logic alert_en_shadowed_5_gated_we;
4363 1/1 assign alert_en_shadowed_5_gated_we = alert_en_shadowed_5_we & alert_regwen_5_qs;
Tests: T1 T2 T3
4364 prim_subreg_shadow #(
4365 .DW (1),
4366 .SwAccess(prim_subreg_pkg::SwAccessRW),
4367 .RESVAL (1'h0),
4368 .Mubi (1'b0)
4369 ) u_alert_en_shadowed_5 (
4370 .clk_i (clk_i),
4371 .rst_ni (rst_ni),
4372 .rst_shadowed_ni (rst_shadowed_ni),
4373
4374 // from register interface
4375 .re (alert_en_shadowed_5_re),
4376 .we (alert_en_shadowed_5_gated_we),
4377 .wd (alert_en_shadowed_5_wd),
4378
4379 // from internal hardware
4380 .de (1'b0),
4381 .d ('0),
4382
4383 // to internal hardware
4384 .qe (),
4385 .q (reg2hw.alert_en_shadowed[5].q),
4386 .ds (),
4387
4388 // to register interface (read)
4389 .qs (alert_en_shadowed_5_qs),
4390
4391 // Shadow register phase. Relevant for hwext only.
4392 .phase (),
4393
4394 // Shadow register error conditions
4395 .err_update (alert_en_shadowed_5_update_err),
4396 .err_storage (alert_en_shadowed_5_storage_err)
4397 );
4398
4399
4400 // Subregister 6 of Multireg alert_en_shadowed
4401 // R[alert_en_shadowed_6]: V(False)
4402 // Create REGWEN-gated WE signal
4403 logic alert_en_shadowed_6_gated_we;
4404 1/1 assign alert_en_shadowed_6_gated_we = alert_en_shadowed_6_we & alert_regwen_6_qs;
Tests: T1 T2 T3
4405 prim_subreg_shadow #(
4406 .DW (1),
4407 .SwAccess(prim_subreg_pkg::SwAccessRW),
4408 .RESVAL (1'h0),
4409 .Mubi (1'b0)
4410 ) u_alert_en_shadowed_6 (
4411 .clk_i (clk_i),
4412 .rst_ni (rst_ni),
4413 .rst_shadowed_ni (rst_shadowed_ni),
4414
4415 // from register interface
4416 .re (alert_en_shadowed_6_re),
4417 .we (alert_en_shadowed_6_gated_we),
4418 .wd (alert_en_shadowed_6_wd),
4419
4420 // from internal hardware
4421 .de (1'b0),
4422 .d ('0),
4423
4424 // to internal hardware
4425 .qe (),
4426 .q (reg2hw.alert_en_shadowed[6].q),
4427 .ds (),
4428
4429 // to register interface (read)
4430 .qs (alert_en_shadowed_6_qs),
4431
4432 // Shadow register phase. Relevant for hwext only.
4433 .phase (),
4434
4435 // Shadow register error conditions
4436 .err_update (alert_en_shadowed_6_update_err),
4437 .err_storage (alert_en_shadowed_6_storage_err)
4438 );
4439
4440
4441 // Subregister 7 of Multireg alert_en_shadowed
4442 // R[alert_en_shadowed_7]: V(False)
4443 // Create REGWEN-gated WE signal
4444 logic alert_en_shadowed_7_gated_we;
4445 1/1 assign alert_en_shadowed_7_gated_we = alert_en_shadowed_7_we & alert_regwen_7_qs;
Tests: T1 T2 T3
4446 prim_subreg_shadow #(
4447 .DW (1),
4448 .SwAccess(prim_subreg_pkg::SwAccessRW),
4449 .RESVAL (1'h0),
4450 .Mubi (1'b0)
4451 ) u_alert_en_shadowed_7 (
4452 .clk_i (clk_i),
4453 .rst_ni (rst_ni),
4454 .rst_shadowed_ni (rst_shadowed_ni),
4455
4456 // from register interface
4457 .re (alert_en_shadowed_7_re),
4458 .we (alert_en_shadowed_7_gated_we),
4459 .wd (alert_en_shadowed_7_wd),
4460
4461 // from internal hardware
4462 .de (1'b0),
4463 .d ('0),
4464
4465 // to internal hardware
4466 .qe (),
4467 .q (reg2hw.alert_en_shadowed[7].q),
4468 .ds (),
4469
4470 // to register interface (read)
4471 .qs (alert_en_shadowed_7_qs),
4472
4473 // Shadow register phase. Relevant for hwext only.
4474 .phase (),
4475
4476 // Shadow register error conditions
4477 .err_update (alert_en_shadowed_7_update_err),
4478 .err_storage (alert_en_shadowed_7_storage_err)
4479 );
4480
4481
4482 // Subregister 8 of Multireg alert_en_shadowed
4483 // R[alert_en_shadowed_8]: V(False)
4484 // Create REGWEN-gated WE signal
4485 logic alert_en_shadowed_8_gated_we;
4486 1/1 assign alert_en_shadowed_8_gated_we = alert_en_shadowed_8_we & alert_regwen_8_qs;
Tests: T1 T2 T3
4487 prim_subreg_shadow #(
4488 .DW (1),
4489 .SwAccess(prim_subreg_pkg::SwAccessRW),
4490 .RESVAL (1'h0),
4491 .Mubi (1'b0)
4492 ) u_alert_en_shadowed_8 (
4493 .clk_i (clk_i),
4494 .rst_ni (rst_ni),
4495 .rst_shadowed_ni (rst_shadowed_ni),
4496
4497 // from register interface
4498 .re (alert_en_shadowed_8_re),
4499 .we (alert_en_shadowed_8_gated_we),
4500 .wd (alert_en_shadowed_8_wd),
4501
4502 // from internal hardware
4503 .de (1'b0),
4504 .d ('0),
4505
4506 // to internal hardware
4507 .qe (),
4508 .q (reg2hw.alert_en_shadowed[8].q),
4509 .ds (),
4510
4511 // to register interface (read)
4512 .qs (alert_en_shadowed_8_qs),
4513
4514 // Shadow register phase. Relevant for hwext only.
4515 .phase (),
4516
4517 // Shadow register error conditions
4518 .err_update (alert_en_shadowed_8_update_err),
4519 .err_storage (alert_en_shadowed_8_storage_err)
4520 );
4521
4522
4523 // Subregister 9 of Multireg alert_en_shadowed
4524 // R[alert_en_shadowed_9]: V(False)
4525 // Create REGWEN-gated WE signal
4526 logic alert_en_shadowed_9_gated_we;
4527 1/1 assign alert_en_shadowed_9_gated_we = alert_en_shadowed_9_we & alert_regwen_9_qs;
Tests: T1 T2 T3
4528 prim_subreg_shadow #(
4529 .DW (1),
4530 .SwAccess(prim_subreg_pkg::SwAccessRW),
4531 .RESVAL (1'h0),
4532 .Mubi (1'b0)
4533 ) u_alert_en_shadowed_9 (
4534 .clk_i (clk_i),
4535 .rst_ni (rst_ni),
4536 .rst_shadowed_ni (rst_shadowed_ni),
4537
4538 // from register interface
4539 .re (alert_en_shadowed_9_re),
4540 .we (alert_en_shadowed_9_gated_we),
4541 .wd (alert_en_shadowed_9_wd),
4542
4543 // from internal hardware
4544 .de (1'b0),
4545 .d ('0),
4546
4547 // to internal hardware
4548 .qe (),
4549 .q (reg2hw.alert_en_shadowed[9].q),
4550 .ds (),
4551
4552 // to register interface (read)
4553 .qs (alert_en_shadowed_9_qs),
4554
4555 // Shadow register phase. Relevant for hwext only.
4556 .phase (),
4557
4558 // Shadow register error conditions
4559 .err_update (alert_en_shadowed_9_update_err),
4560 .err_storage (alert_en_shadowed_9_storage_err)
4561 );
4562
4563
4564 // Subregister 10 of Multireg alert_en_shadowed
4565 // R[alert_en_shadowed_10]: V(False)
4566 // Create REGWEN-gated WE signal
4567 logic alert_en_shadowed_10_gated_we;
4568 1/1 assign alert_en_shadowed_10_gated_we = alert_en_shadowed_10_we & alert_regwen_10_qs;
Tests: T1 T2 T3
4569 prim_subreg_shadow #(
4570 .DW (1),
4571 .SwAccess(prim_subreg_pkg::SwAccessRW),
4572 .RESVAL (1'h0),
4573 .Mubi (1'b0)
4574 ) u_alert_en_shadowed_10 (
4575 .clk_i (clk_i),
4576 .rst_ni (rst_ni),
4577 .rst_shadowed_ni (rst_shadowed_ni),
4578
4579 // from register interface
4580 .re (alert_en_shadowed_10_re),
4581 .we (alert_en_shadowed_10_gated_we),
4582 .wd (alert_en_shadowed_10_wd),
4583
4584 // from internal hardware
4585 .de (1'b0),
4586 .d ('0),
4587
4588 // to internal hardware
4589 .qe (),
4590 .q (reg2hw.alert_en_shadowed[10].q),
4591 .ds (),
4592
4593 // to register interface (read)
4594 .qs (alert_en_shadowed_10_qs),
4595
4596 // Shadow register phase. Relevant for hwext only.
4597 .phase (),
4598
4599 // Shadow register error conditions
4600 .err_update (alert_en_shadowed_10_update_err),
4601 .err_storage (alert_en_shadowed_10_storage_err)
4602 );
4603
4604
4605 // Subregister 11 of Multireg alert_en_shadowed
4606 // R[alert_en_shadowed_11]: V(False)
4607 // Create REGWEN-gated WE signal
4608 logic alert_en_shadowed_11_gated_we;
4609 1/1 assign alert_en_shadowed_11_gated_we = alert_en_shadowed_11_we & alert_regwen_11_qs;
Tests: T1 T2 T3
4610 prim_subreg_shadow #(
4611 .DW (1),
4612 .SwAccess(prim_subreg_pkg::SwAccessRW),
4613 .RESVAL (1'h0),
4614 .Mubi (1'b0)
4615 ) u_alert_en_shadowed_11 (
4616 .clk_i (clk_i),
4617 .rst_ni (rst_ni),
4618 .rst_shadowed_ni (rst_shadowed_ni),
4619
4620 // from register interface
4621 .re (alert_en_shadowed_11_re),
4622 .we (alert_en_shadowed_11_gated_we),
4623 .wd (alert_en_shadowed_11_wd),
4624
4625 // from internal hardware
4626 .de (1'b0),
4627 .d ('0),
4628
4629 // to internal hardware
4630 .qe (),
4631 .q (reg2hw.alert_en_shadowed[11].q),
4632 .ds (),
4633
4634 // to register interface (read)
4635 .qs (alert_en_shadowed_11_qs),
4636
4637 // Shadow register phase. Relevant for hwext only.
4638 .phase (),
4639
4640 // Shadow register error conditions
4641 .err_update (alert_en_shadowed_11_update_err),
4642 .err_storage (alert_en_shadowed_11_storage_err)
4643 );
4644
4645
4646 // Subregister 12 of Multireg alert_en_shadowed
4647 // R[alert_en_shadowed_12]: V(False)
4648 // Create REGWEN-gated WE signal
4649 logic alert_en_shadowed_12_gated_we;
4650 1/1 assign alert_en_shadowed_12_gated_we = alert_en_shadowed_12_we & alert_regwen_12_qs;
Tests: T1 T2 T3
4651 prim_subreg_shadow #(
4652 .DW (1),
4653 .SwAccess(prim_subreg_pkg::SwAccessRW),
4654 .RESVAL (1'h0),
4655 .Mubi (1'b0)
4656 ) u_alert_en_shadowed_12 (
4657 .clk_i (clk_i),
4658 .rst_ni (rst_ni),
4659 .rst_shadowed_ni (rst_shadowed_ni),
4660
4661 // from register interface
4662 .re (alert_en_shadowed_12_re),
4663 .we (alert_en_shadowed_12_gated_we),
4664 .wd (alert_en_shadowed_12_wd),
4665
4666 // from internal hardware
4667 .de (1'b0),
4668 .d ('0),
4669
4670 // to internal hardware
4671 .qe (),
4672 .q (reg2hw.alert_en_shadowed[12].q),
4673 .ds (),
4674
4675 // to register interface (read)
4676 .qs (alert_en_shadowed_12_qs),
4677
4678 // Shadow register phase. Relevant for hwext only.
4679 .phase (),
4680
4681 // Shadow register error conditions
4682 .err_update (alert_en_shadowed_12_update_err),
4683 .err_storage (alert_en_shadowed_12_storage_err)
4684 );
4685
4686
4687 // Subregister 13 of Multireg alert_en_shadowed
4688 // R[alert_en_shadowed_13]: V(False)
4689 // Create REGWEN-gated WE signal
4690 logic alert_en_shadowed_13_gated_we;
4691 1/1 assign alert_en_shadowed_13_gated_we = alert_en_shadowed_13_we & alert_regwen_13_qs;
Tests: T1 T2 T3
4692 prim_subreg_shadow #(
4693 .DW (1),
4694 .SwAccess(prim_subreg_pkg::SwAccessRW),
4695 .RESVAL (1'h0),
4696 .Mubi (1'b0)
4697 ) u_alert_en_shadowed_13 (
4698 .clk_i (clk_i),
4699 .rst_ni (rst_ni),
4700 .rst_shadowed_ni (rst_shadowed_ni),
4701
4702 // from register interface
4703 .re (alert_en_shadowed_13_re),
4704 .we (alert_en_shadowed_13_gated_we),
4705 .wd (alert_en_shadowed_13_wd),
4706
4707 // from internal hardware
4708 .de (1'b0),
4709 .d ('0),
4710
4711 // to internal hardware
4712 .qe (),
4713 .q (reg2hw.alert_en_shadowed[13].q),
4714 .ds (),
4715
4716 // to register interface (read)
4717 .qs (alert_en_shadowed_13_qs),
4718
4719 // Shadow register phase. Relevant for hwext only.
4720 .phase (),
4721
4722 // Shadow register error conditions
4723 .err_update (alert_en_shadowed_13_update_err),
4724 .err_storage (alert_en_shadowed_13_storage_err)
4725 );
4726
4727
4728 // Subregister 14 of Multireg alert_en_shadowed
4729 // R[alert_en_shadowed_14]: V(False)
4730 // Create REGWEN-gated WE signal
4731 logic alert_en_shadowed_14_gated_we;
4732 1/1 assign alert_en_shadowed_14_gated_we = alert_en_shadowed_14_we & alert_regwen_14_qs;
Tests: T1 T2 T3
4733 prim_subreg_shadow #(
4734 .DW (1),
4735 .SwAccess(prim_subreg_pkg::SwAccessRW),
4736 .RESVAL (1'h0),
4737 .Mubi (1'b0)
4738 ) u_alert_en_shadowed_14 (
4739 .clk_i (clk_i),
4740 .rst_ni (rst_ni),
4741 .rst_shadowed_ni (rst_shadowed_ni),
4742
4743 // from register interface
4744 .re (alert_en_shadowed_14_re),
4745 .we (alert_en_shadowed_14_gated_we),
4746 .wd (alert_en_shadowed_14_wd),
4747
4748 // from internal hardware
4749 .de (1'b0),
4750 .d ('0),
4751
4752 // to internal hardware
4753 .qe (),
4754 .q (reg2hw.alert_en_shadowed[14].q),
4755 .ds (),
4756
4757 // to register interface (read)
4758 .qs (alert_en_shadowed_14_qs),
4759
4760 // Shadow register phase. Relevant for hwext only.
4761 .phase (),
4762
4763 // Shadow register error conditions
4764 .err_update (alert_en_shadowed_14_update_err),
4765 .err_storage (alert_en_shadowed_14_storage_err)
4766 );
4767
4768
4769 // Subregister 15 of Multireg alert_en_shadowed
4770 // R[alert_en_shadowed_15]: V(False)
4771 // Create REGWEN-gated WE signal
4772 logic alert_en_shadowed_15_gated_we;
4773 1/1 assign alert_en_shadowed_15_gated_we = alert_en_shadowed_15_we & alert_regwen_15_qs;
Tests: T1 T2 T3
4774 prim_subreg_shadow #(
4775 .DW (1),
4776 .SwAccess(prim_subreg_pkg::SwAccessRW),
4777 .RESVAL (1'h0),
4778 .Mubi (1'b0)
4779 ) u_alert_en_shadowed_15 (
4780 .clk_i (clk_i),
4781 .rst_ni (rst_ni),
4782 .rst_shadowed_ni (rst_shadowed_ni),
4783
4784 // from register interface
4785 .re (alert_en_shadowed_15_re),
4786 .we (alert_en_shadowed_15_gated_we),
4787 .wd (alert_en_shadowed_15_wd),
4788
4789 // from internal hardware
4790 .de (1'b0),
4791 .d ('0),
4792
4793 // to internal hardware
4794 .qe (),
4795 .q (reg2hw.alert_en_shadowed[15].q),
4796 .ds (),
4797
4798 // to register interface (read)
4799 .qs (alert_en_shadowed_15_qs),
4800
4801 // Shadow register phase. Relevant for hwext only.
4802 .phase (),
4803
4804 // Shadow register error conditions
4805 .err_update (alert_en_shadowed_15_update_err),
4806 .err_storage (alert_en_shadowed_15_storage_err)
4807 );
4808
4809
4810 // Subregister 16 of Multireg alert_en_shadowed
4811 // R[alert_en_shadowed_16]: V(False)
4812 // Create REGWEN-gated WE signal
4813 logic alert_en_shadowed_16_gated_we;
4814 1/1 assign alert_en_shadowed_16_gated_we = alert_en_shadowed_16_we & alert_regwen_16_qs;
Tests: T1 T2 T3
4815 prim_subreg_shadow #(
4816 .DW (1),
4817 .SwAccess(prim_subreg_pkg::SwAccessRW),
4818 .RESVAL (1'h0),
4819 .Mubi (1'b0)
4820 ) u_alert_en_shadowed_16 (
4821 .clk_i (clk_i),
4822 .rst_ni (rst_ni),
4823 .rst_shadowed_ni (rst_shadowed_ni),
4824
4825 // from register interface
4826 .re (alert_en_shadowed_16_re),
4827 .we (alert_en_shadowed_16_gated_we),
4828 .wd (alert_en_shadowed_16_wd),
4829
4830 // from internal hardware
4831 .de (1'b0),
4832 .d ('0),
4833
4834 // to internal hardware
4835 .qe (),
4836 .q (reg2hw.alert_en_shadowed[16].q),
4837 .ds (),
4838
4839 // to register interface (read)
4840 .qs (alert_en_shadowed_16_qs),
4841
4842 // Shadow register phase. Relevant for hwext only.
4843 .phase (),
4844
4845 // Shadow register error conditions
4846 .err_update (alert_en_shadowed_16_update_err),
4847 .err_storage (alert_en_shadowed_16_storage_err)
4848 );
4849
4850
4851 // Subregister 17 of Multireg alert_en_shadowed
4852 // R[alert_en_shadowed_17]: V(False)
4853 // Create REGWEN-gated WE signal
4854 logic alert_en_shadowed_17_gated_we;
4855 1/1 assign alert_en_shadowed_17_gated_we = alert_en_shadowed_17_we & alert_regwen_17_qs;
Tests: T1 T2 T3
4856 prim_subreg_shadow #(
4857 .DW (1),
4858 .SwAccess(prim_subreg_pkg::SwAccessRW),
4859 .RESVAL (1'h0),
4860 .Mubi (1'b0)
4861 ) u_alert_en_shadowed_17 (
4862 .clk_i (clk_i),
4863 .rst_ni (rst_ni),
4864 .rst_shadowed_ni (rst_shadowed_ni),
4865
4866 // from register interface
4867 .re (alert_en_shadowed_17_re),
4868 .we (alert_en_shadowed_17_gated_we),
4869 .wd (alert_en_shadowed_17_wd),
4870
4871 // from internal hardware
4872 .de (1'b0),
4873 .d ('0),
4874
4875 // to internal hardware
4876 .qe (),
4877 .q (reg2hw.alert_en_shadowed[17].q),
4878 .ds (),
4879
4880 // to register interface (read)
4881 .qs (alert_en_shadowed_17_qs),
4882
4883 // Shadow register phase. Relevant for hwext only.
4884 .phase (),
4885
4886 // Shadow register error conditions
4887 .err_update (alert_en_shadowed_17_update_err),
4888 .err_storage (alert_en_shadowed_17_storage_err)
4889 );
4890
4891
4892 // Subregister 18 of Multireg alert_en_shadowed
4893 // R[alert_en_shadowed_18]: V(False)
4894 // Create REGWEN-gated WE signal
4895 logic alert_en_shadowed_18_gated_we;
4896 1/1 assign alert_en_shadowed_18_gated_we = alert_en_shadowed_18_we & alert_regwen_18_qs;
Tests: T1 T2 T3
4897 prim_subreg_shadow #(
4898 .DW (1),
4899 .SwAccess(prim_subreg_pkg::SwAccessRW),
4900 .RESVAL (1'h0),
4901 .Mubi (1'b0)
4902 ) u_alert_en_shadowed_18 (
4903 .clk_i (clk_i),
4904 .rst_ni (rst_ni),
4905 .rst_shadowed_ni (rst_shadowed_ni),
4906
4907 // from register interface
4908 .re (alert_en_shadowed_18_re),
4909 .we (alert_en_shadowed_18_gated_we),
4910 .wd (alert_en_shadowed_18_wd),
4911
4912 // from internal hardware
4913 .de (1'b0),
4914 .d ('0),
4915
4916 // to internal hardware
4917 .qe (),
4918 .q (reg2hw.alert_en_shadowed[18].q),
4919 .ds (),
4920
4921 // to register interface (read)
4922 .qs (alert_en_shadowed_18_qs),
4923
4924 // Shadow register phase. Relevant for hwext only.
4925 .phase (),
4926
4927 // Shadow register error conditions
4928 .err_update (alert_en_shadowed_18_update_err),
4929 .err_storage (alert_en_shadowed_18_storage_err)
4930 );
4931
4932
4933 // Subregister 19 of Multireg alert_en_shadowed
4934 // R[alert_en_shadowed_19]: V(False)
4935 // Create REGWEN-gated WE signal
4936 logic alert_en_shadowed_19_gated_we;
4937 1/1 assign alert_en_shadowed_19_gated_we = alert_en_shadowed_19_we & alert_regwen_19_qs;
Tests: T1 T2 T3
4938 prim_subreg_shadow #(
4939 .DW (1),
4940 .SwAccess(prim_subreg_pkg::SwAccessRW),
4941 .RESVAL (1'h0),
4942 .Mubi (1'b0)
4943 ) u_alert_en_shadowed_19 (
4944 .clk_i (clk_i),
4945 .rst_ni (rst_ni),
4946 .rst_shadowed_ni (rst_shadowed_ni),
4947
4948 // from register interface
4949 .re (alert_en_shadowed_19_re),
4950 .we (alert_en_shadowed_19_gated_we),
4951 .wd (alert_en_shadowed_19_wd),
4952
4953 // from internal hardware
4954 .de (1'b0),
4955 .d ('0),
4956
4957 // to internal hardware
4958 .qe (),
4959 .q (reg2hw.alert_en_shadowed[19].q),
4960 .ds (),
4961
4962 // to register interface (read)
4963 .qs (alert_en_shadowed_19_qs),
4964
4965 // Shadow register phase. Relevant for hwext only.
4966 .phase (),
4967
4968 // Shadow register error conditions
4969 .err_update (alert_en_shadowed_19_update_err),
4970 .err_storage (alert_en_shadowed_19_storage_err)
4971 );
4972
4973
4974 // Subregister 20 of Multireg alert_en_shadowed
4975 // R[alert_en_shadowed_20]: V(False)
4976 // Create REGWEN-gated WE signal
4977 logic alert_en_shadowed_20_gated_we;
4978 1/1 assign alert_en_shadowed_20_gated_we = alert_en_shadowed_20_we & alert_regwen_20_qs;
Tests: T1 T2 T3
4979 prim_subreg_shadow #(
4980 .DW (1),
4981 .SwAccess(prim_subreg_pkg::SwAccessRW),
4982 .RESVAL (1'h0),
4983 .Mubi (1'b0)
4984 ) u_alert_en_shadowed_20 (
4985 .clk_i (clk_i),
4986 .rst_ni (rst_ni),
4987 .rst_shadowed_ni (rst_shadowed_ni),
4988
4989 // from register interface
4990 .re (alert_en_shadowed_20_re),
4991 .we (alert_en_shadowed_20_gated_we),
4992 .wd (alert_en_shadowed_20_wd),
4993
4994 // from internal hardware
4995 .de (1'b0),
4996 .d ('0),
4997
4998 // to internal hardware
4999 .qe (),
5000 .q (reg2hw.alert_en_shadowed[20].q),
5001 .ds (),
5002
5003 // to register interface (read)
5004 .qs (alert_en_shadowed_20_qs),
5005
5006 // Shadow register phase. Relevant for hwext only.
5007 .phase (),
5008
5009 // Shadow register error conditions
5010 .err_update (alert_en_shadowed_20_update_err),
5011 .err_storage (alert_en_shadowed_20_storage_err)
5012 );
5013
5014
5015 // Subregister 21 of Multireg alert_en_shadowed
5016 // R[alert_en_shadowed_21]: V(False)
5017 // Create REGWEN-gated WE signal
5018 logic alert_en_shadowed_21_gated_we;
5019 1/1 assign alert_en_shadowed_21_gated_we = alert_en_shadowed_21_we & alert_regwen_21_qs;
Tests: T1 T2 T3
5020 prim_subreg_shadow #(
5021 .DW (1),
5022 .SwAccess(prim_subreg_pkg::SwAccessRW),
5023 .RESVAL (1'h0),
5024 .Mubi (1'b0)
5025 ) u_alert_en_shadowed_21 (
5026 .clk_i (clk_i),
5027 .rst_ni (rst_ni),
5028 .rst_shadowed_ni (rst_shadowed_ni),
5029
5030 // from register interface
5031 .re (alert_en_shadowed_21_re),
5032 .we (alert_en_shadowed_21_gated_we),
5033 .wd (alert_en_shadowed_21_wd),
5034
5035 // from internal hardware
5036 .de (1'b0),
5037 .d ('0),
5038
5039 // to internal hardware
5040 .qe (),
5041 .q (reg2hw.alert_en_shadowed[21].q),
5042 .ds (),
5043
5044 // to register interface (read)
5045 .qs (alert_en_shadowed_21_qs),
5046
5047 // Shadow register phase. Relevant for hwext only.
5048 .phase (),
5049
5050 // Shadow register error conditions
5051 .err_update (alert_en_shadowed_21_update_err),
5052 .err_storage (alert_en_shadowed_21_storage_err)
5053 );
5054
5055
5056 // Subregister 22 of Multireg alert_en_shadowed
5057 // R[alert_en_shadowed_22]: V(False)
5058 // Create REGWEN-gated WE signal
5059 logic alert_en_shadowed_22_gated_we;
5060 1/1 assign alert_en_shadowed_22_gated_we = alert_en_shadowed_22_we & alert_regwen_22_qs;
Tests: T1 T2 T3
5061 prim_subreg_shadow #(
5062 .DW (1),
5063 .SwAccess(prim_subreg_pkg::SwAccessRW),
5064 .RESVAL (1'h0),
5065 .Mubi (1'b0)
5066 ) u_alert_en_shadowed_22 (
5067 .clk_i (clk_i),
5068 .rst_ni (rst_ni),
5069 .rst_shadowed_ni (rst_shadowed_ni),
5070
5071 // from register interface
5072 .re (alert_en_shadowed_22_re),
5073 .we (alert_en_shadowed_22_gated_we),
5074 .wd (alert_en_shadowed_22_wd),
5075
5076 // from internal hardware
5077 .de (1'b0),
5078 .d ('0),
5079
5080 // to internal hardware
5081 .qe (),
5082 .q (reg2hw.alert_en_shadowed[22].q),
5083 .ds (),
5084
5085 // to register interface (read)
5086 .qs (alert_en_shadowed_22_qs),
5087
5088 // Shadow register phase. Relevant for hwext only.
5089 .phase (),
5090
5091 // Shadow register error conditions
5092 .err_update (alert_en_shadowed_22_update_err),
5093 .err_storage (alert_en_shadowed_22_storage_err)
5094 );
5095
5096
5097 // Subregister 23 of Multireg alert_en_shadowed
5098 // R[alert_en_shadowed_23]: V(False)
5099 // Create REGWEN-gated WE signal
5100 logic alert_en_shadowed_23_gated_we;
5101 1/1 assign alert_en_shadowed_23_gated_we = alert_en_shadowed_23_we & alert_regwen_23_qs;
Tests: T1 T2 T3
5102 prim_subreg_shadow #(
5103 .DW (1),
5104 .SwAccess(prim_subreg_pkg::SwAccessRW),
5105 .RESVAL (1'h0),
5106 .Mubi (1'b0)
5107 ) u_alert_en_shadowed_23 (
5108 .clk_i (clk_i),
5109 .rst_ni (rst_ni),
5110 .rst_shadowed_ni (rst_shadowed_ni),
5111
5112 // from register interface
5113 .re (alert_en_shadowed_23_re),
5114 .we (alert_en_shadowed_23_gated_we),
5115 .wd (alert_en_shadowed_23_wd),
5116
5117 // from internal hardware
5118 .de (1'b0),
5119 .d ('0),
5120
5121 // to internal hardware
5122 .qe (),
5123 .q (reg2hw.alert_en_shadowed[23].q),
5124 .ds (),
5125
5126 // to register interface (read)
5127 .qs (alert_en_shadowed_23_qs),
5128
5129 // Shadow register phase. Relevant for hwext only.
5130 .phase (),
5131
5132 // Shadow register error conditions
5133 .err_update (alert_en_shadowed_23_update_err),
5134 .err_storage (alert_en_shadowed_23_storage_err)
5135 );
5136
5137
5138 // Subregister 24 of Multireg alert_en_shadowed
5139 // R[alert_en_shadowed_24]: V(False)
5140 // Create REGWEN-gated WE signal
5141 logic alert_en_shadowed_24_gated_we;
5142 1/1 assign alert_en_shadowed_24_gated_we = alert_en_shadowed_24_we & alert_regwen_24_qs;
Tests: T1 T2 T3
5143 prim_subreg_shadow #(
5144 .DW (1),
5145 .SwAccess(prim_subreg_pkg::SwAccessRW),
5146 .RESVAL (1'h0),
5147 .Mubi (1'b0)
5148 ) u_alert_en_shadowed_24 (
5149 .clk_i (clk_i),
5150 .rst_ni (rst_ni),
5151 .rst_shadowed_ni (rst_shadowed_ni),
5152
5153 // from register interface
5154 .re (alert_en_shadowed_24_re),
5155 .we (alert_en_shadowed_24_gated_we),
5156 .wd (alert_en_shadowed_24_wd),
5157
5158 // from internal hardware
5159 .de (1'b0),
5160 .d ('0),
5161
5162 // to internal hardware
5163 .qe (),
5164 .q (reg2hw.alert_en_shadowed[24].q),
5165 .ds (),
5166
5167 // to register interface (read)
5168 .qs (alert_en_shadowed_24_qs),
5169
5170 // Shadow register phase. Relevant for hwext only.
5171 .phase (),
5172
5173 // Shadow register error conditions
5174 .err_update (alert_en_shadowed_24_update_err),
5175 .err_storage (alert_en_shadowed_24_storage_err)
5176 );
5177
5178
5179 // Subregister 25 of Multireg alert_en_shadowed
5180 // R[alert_en_shadowed_25]: V(False)
5181 // Create REGWEN-gated WE signal
5182 logic alert_en_shadowed_25_gated_we;
5183 1/1 assign alert_en_shadowed_25_gated_we = alert_en_shadowed_25_we & alert_regwen_25_qs;
Tests: T1 T2 T3
5184 prim_subreg_shadow #(
5185 .DW (1),
5186 .SwAccess(prim_subreg_pkg::SwAccessRW),
5187 .RESVAL (1'h0),
5188 .Mubi (1'b0)
5189 ) u_alert_en_shadowed_25 (
5190 .clk_i (clk_i),
5191 .rst_ni (rst_ni),
5192 .rst_shadowed_ni (rst_shadowed_ni),
5193
5194 // from register interface
5195 .re (alert_en_shadowed_25_re),
5196 .we (alert_en_shadowed_25_gated_we),
5197 .wd (alert_en_shadowed_25_wd),
5198
5199 // from internal hardware
5200 .de (1'b0),
5201 .d ('0),
5202
5203 // to internal hardware
5204 .qe (),
5205 .q (reg2hw.alert_en_shadowed[25].q),
5206 .ds (),
5207
5208 // to register interface (read)
5209 .qs (alert_en_shadowed_25_qs),
5210
5211 // Shadow register phase. Relevant for hwext only.
5212 .phase (),
5213
5214 // Shadow register error conditions
5215 .err_update (alert_en_shadowed_25_update_err),
5216 .err_storage (alert_en_shadowed_25_storage_err)
5217 );
5218
5219
5220 // Subregister 26 of Multireg alert_en_shadowed
5221 // R[alert_en_shadowed_26]: V(False)
5222 // Create REGWEN-gated WE signal
5223 logic alert_en_shadowed_26_gated_we;
5224 1/1 assign alert_en_shadowed_26_gated_we = alert_en_shadowed_26_we & alert_regwen_26_qs;
Tests: T1 T2 T3
5225 prim_subreg_shadow #(
5226 .DW (1),
5227 .SwAccess(prim_subreg_pkg::SwAccessRW),
5228 .RESVAL (1'h0),
5229 .Mubi (1'b0)
5230 ) u_alert_en_shadowed_26 (
5231 .clk_i (clk_i),
5232 .rst_ni (rst_ni),
5233 .rst_shadowed_ni (rst_shadowed_ni),
5234
5235 // from register interface
5236 .re (alert_en_shadowed_26_re),
5237 .we (alert_en_shadowed_26_gated_we),
5238 .wd (alert_en_shadowed_26_wd),
5239
5240 // from internal hardware
5241 .de (1'b0),
5242 .d ('0),
5243
5244 // to internal hardware
5245 .qe (),
5246 .q (reg2hw.alert_en_shadowed[26].q),
5247 .ds (),
5248
5249 // to register interface (read)
5250 .qs (alert_en_shadowed_26_qs),
5251
5252 // Shadow register phase. Relevant for hwext only.
5253 .phase (),
5254
5255 // Shadow register error conditions
5256 .err_update (alert_en_shadowed_26_update_err),
5257 .err_storage (alert_en_shadowed_26_storage_err)
5258 );
5259
5260
5261 // Subregister 27 of Multireg alert_en_shadowed
5262 // R[alert_en_shadowed_27]: V(False)
5263 // Create REGWEN-gated WE signal
5264 logic alert_en_shadowed_27_gated_we;
5265 1/1 assign alert_en_shadowed_27_gated_we = alert_en_shadowed_27_we & alert_regwen_27_qs;
Tests: T1 T2 T3
5266 prim_subreg_shadow #(
5267 .DW (1),
5268 .SwAccess(prim_subreg_pkg::SwAccessRW),
5269 .RESVAL (1'h0),
5270 .Mubi (1'b0)
5271 ) u_alert_en_shadowed_27 (
5272 .clk_i (clk_i),
5273 .rst_ni (rst_ni),
5274 .rst_shadowed_ni (rst_shadowed_ni),
5275
5276 // from register interface
5277 .re (alert_en_shadowed_27_re),
5278 .we (alert_en_shadowed_27_gated_we),
5279 .wd (alert_en_shadowed_27_wd),
5280
5281 // from internal hardware
5282 .de (1'b0),
5283 .d ('0),
5284
5285 // to internal hardware
5286 .qe (),
5287 .q (reg2hw.alert_en_shadowed[27].q),
5288 .ds (),
5289
5290 // to register interface (read)
5291 .qs (alert_en_shadowed_27_qs),
5292
5293 // Shadow register phase. Relevant for hwext only.
5294 .phase (),
5295
5296 // Shadow register error conditions
5297 .err_update (alert_en_shadowed_27_update_err),
5298 .err_storage (alert_en_shadowed_27_storage_err)
5299 );
5300
5301
5302 // Subregister 28 of Multireg alert_en_shadowed
5303 // R[alert_en_shadowed_28]: V(False)
5304 // Create REGWEN-gated WE signal
5305 logic alert_en_shadowed_28_gated_we;
5306 1/1 assign alert_en_shadowed_28_gated_we = alert_en_shadowed_28_we & alert_regwen_28_qs;
Tests: T1 T2 T3
5307 prim_subreg_shadow #(
5308 .DW (1),
5309 .SwAccess(prim_subreg_pkg::SwAccessRW),
5310 .RESVAL (1'h0),
5311 .Mubi (1'b0)
5312 ) u_alert_en_shadowed_28 (
5313 .clk_i (clk_i),
5314 .rst_ni (rst_ni),
5315 .rst_shadowed_ni (rst_shadowed_ni),
5316
5317 // from register interface
5318 .re (alert_en_shadowed_28_re),
5319 .we (alert_en_shadowed_28_gated_we),
5320 .wd (alert_en_shadowed_28_wd),
5321
5322 // from internal hardware
5323 .de (1'b0),
5324 .d ('0),
5325
5326 // to internal hardware
5327 .qe (),
5328 .q (reg2hw.alert_en_shadowed[28].q),
5329 .ds (),
5330
5331 // to register interface (read)
5332 .qs (alert_en_shadowed_28_qs),
5333
5334 // Shadow register phase. Relevant for hwext only.
5335 .phase (),
5336
5337 // Shadow register error conditions
5338 .err_update (alert_en_shadowed_28_update_err),
5339 .err_storage (alert_en_shadowed_28_storage_err)
5340 );
5341
5342
5343 // Subregister 29 of Multireg alert_en_shadowed
5344 // R[alert_en_shadowed_29]: V(False)
5345 // Create REGWEN-gated WE signal
5346 logic alert_en_shadowed_29_gated_we;
5347 1/1 assign alert_en_shadowed_29_gated_we = alert_en_shadowed_29_we & alert_regwen_29_qs;
Tests: T1 T2 T3
5348 prim_subreg_shadow #(
5349 .DW (1),
5350 .SwAccess(prim_subreg_pkg::SwAccessRW),
5351 .RESVAL (1'h0),
5352 .Mubi (1'b0)
5353 ) u_alert_en_shadowed_29 (
5354 .clk_i (clk_i),
5355 .rst_ni (rst_ni),
5356 .rst_shadowed_ni (rst_shadowed_ni),
5357
5358 // from register interface
5359 .re (alert_en_shadowed_29_re),
5360 .we (alert_en_shadowed_29_gated_we),
5361 .wd (alert_en_shadowed_29_wd),
5362
5363 // from internal hardware
5364 .de (1'b0),
5365 .d ('0),
5366
5367 // to internal hardware
5368 .qe (),
5369 .q (reg2hw.alert_en_shadowed[29].q),
5370 .ds (),
5371
5372 // to register interface (read)
5373 .qs (alert_en_shadowed_29_qs),
5374
5375 // Shadow register phase. Relevant for hwext only.
5376 .phase (),
5377
5378 // Shadow register error conditions
5379 .err_update (alert_en_shadowed_29_update_err),
5380 .err_storage (alert_en_shadowed_29_storage_err)
5381 );
5382
5383
5384 // Subregister 30 of Multireg alert_en_shadowed
5385 // R[alert_en_shadowed_30]: V(False)
5386 // Create REGWEN-gated WE signal
5387 logic alert_en_shadowed_30_gated_we;
5388 1/1 assign alert_en_shadowed_30_gated_we = alert_en_shadowed_30_we & alert_regwen_30_qs;
Tests: T1 T2 T3
5389 prim_subreg_shadow #(
5390 .DW (1),
5391 .SwAccess(prim_subreg_pkg::SwAccessRW),
5392 .RESVAL (1'h0),
5393 .Mubi (1'b0)
5394 ) u_alert_en_shadowed_30 (
5395 .clk_i (clk_i),
5396 .rst_ni (rst_ni),
5397 .rst_shadowed_ni (rst_shadowed_ni),
5398
5399 // from register interface
5400 .re (alert_en_shadowed_30_re),
5401 .we (alert_en_shadowed_30_gated_we),
5402 .wd (alert_en_shadowed_30_wd),
5403
5404 // from internal hardware
5405 .de (1'b0),
5406 .d ('0),
5407
5408 // to internal hardware
5409 .qe (),
5410 .q (reg2hw.alert_en_shadowed[30].q),
5411 .ds (),
5412
5413 // to register interface (read)
5414 .qs (alert_en_shadowed_30_qs),
5415
5416 // Shadow register phase. Relevant for hwext only.
5417 .phase (),
5418
5419 // Shadow register error conditions
5420 .err_update (alert_en_shadowed_30_update_err),
5421 .err_storage (alert_en_shadowed_30_storage_err)
5422 );
5423
5424
5425 // Subregister 31 of Multireg alert_en_shadowed
5426 // R[alert_en_shadowed_31]: V(False)
5427 // Create REGWEN-gated WE signal
5428 logic alert_en_shadowed_31_gated_we;
5429 1/1 assign alert_en_shadowed_31_gated_we = alert_en_shadowed_31_we & alert_regwen_31_qs;
Tests: T1 T2 T3
5430 prim_subreg_shadow #(
5431 .DW (1),
5432 .SwAccess(prim_subreg_pkg::SwAccessRW),
5433 .RESVAL (1'h0),
5434 .Mubi (1'b0)
5435 ) u_alert_en_shadowed_31 (
5436 .clk_i (clk_i),
5437 .rst_ni (rst_ni),
5438 .rst_shadowed_ni (rst_shadowed_ni),
5439
5440 // from register interface
5441 .re (alert_en_shadowed_31_re),
5442 .we (alert_en_shadowed_31_gated_we),
5443 .wd (alert_en_shadowed_31_wd),
5444
5445 // from internal hardware
5446 .de (1'b0),
5447 .d ('0),
5448
5449 // to internal hardware
5450 .qe (),
5451 .q (reg2hw.alert_en_shadowed[31].q),
5452 .ds (),
5453
5454 // to register interface (read)
5455 .qs (alert_en_shadowed_31_qs),
5456
5457 // Shadow register phase. Relevant for hwext only.
5458 .phase (),
5459
5460 // Shadow register error conditions
5461 .err_update (alert_en_shadowed_31_update_err),
5462 .err_storage (alert_en_shadowed_31_storage_err)
5463 );
5464
5465
5466 // Subregister 32 of Multireg alert_en_shadowed
5467 // R[alert_en_shadowed_32]: V(False)
5468 // Create REGWEN-gated WE signal
5469 logic alert_en_shadowed_32_gated_we;
5470 1/1 assign alert_en_shadowed_32_gated_we = alert_en_shadowed_32_we & alert_regwen_32_qs;
Tests: T1 T2 T3
5471 prim_subreg_shadow #(
5472 .DW (1),
5473 .SwAccess(prim_subreg_pkg::SwAccessRW),
5474 .RESVAL (1'h0),
5475 .Mubi (1'b0)
5476 ) u_alert_en_shadowed_32 (
5477 .clk_i (clk_i),
5478 .rst_ni (rst_ni),
5479 .rst_shadowed_ni (rst_shadowed_ni),
5480
5481 // from register interface
5482 .re (alert_en_shadowed_32_re),
5483 .we (alert_en_shadowed_32_gated_we),
5484 .wd (alert_en_shadowed_32_wd),
5485
5486 // from internal hardware
5487 .de (1'b0),
5488 .d ('0),
5489
5490 // to internal hardware
5491 .qe (),
5492 .q (reg2hw.alert_en_shadowed[32].q),
5493 .ds (),
5494
5495 // to register interface (read)
5496 .qs (alert_en_shadowed_32_qs),
5497
5498 // Shadow register phase. Relevant for hwext only.
5499 .phase (),
5500
5501 // Shadow register error conditions
5502 .err_update (alert_en_shadowed_32_update_err),
5503 .err_storage (alert_en_shadowed_32_storage_err)
5504 );
5505
5506
5507 // Subregister 33 of Multireg alert_en_shadowed
5508 // R[alert_en_shadowed_33]: V(False)
5509 // Create REGWEN-gated WE signal
5510 logic alert_en_shadowed_33_gated_we;
5511 1/1 assign alert_en_shadowed_33_gated_we = alert_en_shadowed_33_we & alert_regwen_33_qs;
Tests: T1 T2 T3
5512 prim_subreg_shadow #(
5513 .DW (1),
5514 .SwAccess(prim_subreg_pkg::SwAccessRW),
5515 .RESVAL (1'h0),
5516 .Mubi (1'b0)
5517 ) u_alert_en_shadowed_33 (
5518 .clk_i (clk_i),
5519 .rst_ni (rst_ni),
5520 .rst_shadowed_ni (rst_shadowed_ni),
5521
5522 // from register interface
5523 .re (alert_en_shadowed_33_re),
5524 .we (alert_en_shadowed_33_gated_we),
5525 .wd (alert_en_shadowed_33_wd),
5526
5527 // from internal hardware
5528 .de (1'b0),
5529 .d ('0),
5530
5531 // to internal hardware
5532 .qe (),
5533 .q (reg2hw.alert_en_shadowed[33].q),
5534 .ds (),
5535
5536 // to register interface (read)
5537 .qs (alert_en_shadowed_33_qs),
5538
5539 // Shadow register phase. Relevant for hwext only.
5540 .phase (),
5541
5542 // Shadow register error conditions
5543 .err_update (alert_en_shadowed_33_update_err),
5544 .err_storage (alert_en_shadowed_33_storage_err)
5545 );
5546
5547
5548 // Subregister 34 of Multireg alert_en_shadowed
5549 // R[alert_en_shadowed_34]: V(False)
5550 // Create REGWEN-gated WE signal
5551 logic alert_en_shadowed_34_gated_we;
5552 1/1 assign alert_en_shadowed_34_gated_we = alert_en_shadowed_34_we & alert_regwen_34_qs;
Tests: T1 T2 T3
5553 prim_subreg_shadow #(
5554 .DW (1),
5555 .SwAccess(prim_subreg_pkg::SwAccessRW),
5556 .RESVAL (1'h0),
5557 .Mubi (1'b0)
5558 ) u_alert_en_shadowed_34 (
5559 .clk_i (clk_i),
5560 .rst_ni (rst_ni),
5561 .rst_shadowed_ni (rst_shadowed_ni),
5562
5563 // from register interface
5564 .re (alert_en_shadowed_34_re),
5565 .we (alert_en_shadowed_34_gated_we),
5566 .wd (alert_en_shadowed_34_wd),
5567
5568 // from internal hardware
5569 .de (1'b0),
5570 .d ('0),
5571
5572 // to internal hardware
5573 .qe (),
5574 .q (reg2hw.alert_en_shadowed[34].q),
5575 .ds (),
5576
5577 // to register interface (read)
5578 .qs (alert_en_shadowed_34_qs),
5579
5580 // Shadow register phase. Relevant for hwext only.
5581 .phase (),
5582
5583 // Shadow register error conditions
5584 .err_update (alert_en_shadowed_34_update_err),
5585 .err_storage (alert_en_shadowed_34_storage_err)
5586 );
5587
5588
5589 // Subregister 35 of Multireg alert_en_shadowed
5590 // R[alert_en_shadowed_35]: V(False)
5591 // Create REGWEN-gated WE signal
5592 logic alert_en_shadowed_35_gated_we;
5593 1/1 assign alert_en_shadowed_35_gated_we = alert_en_shadowed_35_we & alert_regwen_35_qs;
Tests: T1 T2 T3
5594 prim_subreg_shadow #(
5595 .DW (1),
5596 .SwAccess(prim_subreg_pkg::SwAccessRW),
5597 .RESVAL (1'h0),
5598 .Mubi (1'b0)
5599 ) u_alert_en_shadowed_35 (
5600 .clk_i (clk_i),
5601 .rst_ni (rst_ni),
5602 .rst_shadowed_ni (rst_shadowed_ni),
5603
5604 // from register interface
5605 .re (alert_en_shadowed_35_re),
5606 .we (alert_en_shadowed_35_gated_we),
5607 .wd (alert_en_shadowed_35_wd),
5608
5609 // from internal hardware
5610 .de (1'b0),
5611 .d ('0),
5612
5613 // to internal hardware
5614 .qe (),
5615 .q (reg2hw.alert_en_shadowed[35].q),
5616 .ds (),
5617
5618 // to register interface (read)
5619 .qs (alert_en_shadowed_35_qs),
5620
5621 // Shadow register phase. Relevant for hwext only.
5622 .phase (),
5623
5624 // Shadow register error conditions
5625 .err_update (alert_en_shadowed_35_update_err),
5626 .err_storage (alert_en_shadowed_35_storage_err)
5627 );
5628
5629
5630 // Subregister 36 of Multireg alert_en_shadowed
5631 // R[alert_en_shadowed_36]: V(False)
5632 // Create REGWEN-gated WE signal
5633 logic alert_en_shadowed_36_gated_we;
5634 1/1 assign alert_en_shadowed_36_gated_we = alert_en_shadowed_36_we & alert_regwen_36_qs;
Tests: T1 T2 T3
5635 prim_subreg_shadow #(
5636 .DW (1),
5637 .SwAccess(prim_subreg_pkg::SwAccessRW),
5638 .RESVAL (1'h0),
5639 .Mubi (1'b0)
5640 ) u_alert_en_shadowed_36 (
5641 .clk_i (clk_i),
5642 .rst_ni (rst_ni),
5643 .rst_shadowed_ni (rst_shadowed_ni),
5644
5645 // from register interface
5646 .re (alert_en_shadowed_36_re),
5647 .we (alert_en_shadowed_36_gated_we),
5648 .wd (alert_en_shadowed_36_wd),
5649
5650 // from internal hardware
5651 .de (1'b0),
5652 .d ('0),
5653
5654 // to internal hardware
5655 .qe (),
5656 .q (reg2hw.alert_en_shadowed[36].q),
5657 .ds (),
5658
5659 // to register interface (read)
5660 .qs (alert_en_shadowed_36_qs),
5661
5662 // Shadow register phase. Relevant for hwext only.
5663 .phase (),
5664
5665 // Shadow register error conditions
5666 .err_update (alert_en_shadowed_36_update_err),
5667 .err_storage (alert_en_shadowed_36_storage_err)
5668 );
5669
5670
5671 // Subregister 37 of Multireg alert_en_shadowed
5672 // R[alert_en_shadowed_37]: V(False)
5673 // Create REGWEN-gated WE signal
5674 logic alert_en_shadowed_37_gated_we;
5675 1/1 assign alert_en_shadowed_37_gated_we = alert_en_shadowed_37_we & alert_regwen_37_qs;
Tests: T1 T2 T3
5676 prim_subreg_shadow #(
5677 .DW (1),
5678 .SwAccess(prim_subreg_pkg::SwAccessRW),
5679 .RESVAL (1'h0),
5680 .Mubi (1'b0)
5681 ) u_alert_en_shadowed_37 (
5682 .clk_i (clk_i),
5683 .rst_ni (rst_ni),
5684 .rst_shadowed_ni (rst_shadowed_ni),
5685
5686 // from register interface
5687 .re (alert_en_shadowed_37_re),
5688 .we (alert_en_shadowed_37_gated_we),
5689 .wd (alert_en_shadowed_37_wd),
5690
5691 // from internal hardware
5692 .de (1'b0),
5693 .d ('0),
5694
5695 // to internal hardware
5696 .qe (),
5697 .q (reg2hw.alert_en_shadowed[37].q),
5698 .ds (),
5699
5700 // to register interface (read)
5701 .qs (alert_en_shadowed_37_qs),
5702
5703 // Shadow register phase. Relevant for hwext only.
5704 .phase (),
5705
5706 // Shadow register error conditions
5707 .err_update (alert_en_shadowed_37_update_err),
5708 .err_storage (alert_en_shadowed_37_storage_err)
5709 );
5710
5711
5712 // Subregister 38 of Multireg alert_en_shadowed
5713 // R[alert_en_shadowed_38]: V(False)
5714 // Create REGWEN-gated WE signal
5715 logic alert_en_shadowed_38_gated_we;
5716 1/1 assign alert_en_shadowed_38_gated_we = alert_en_shadowed_38_we & alert_regwen_38_qs;
Tests: T1 T2 T3
5717 prim_subreg_shadow #(
5718 .DW (1),
5719 .SwAccess(prim_subreg_pkg::SwAccessRW),
5720 .RESVAL (1'h0),
5721 .Mubi (1'b0)
5722 ) u_alert_en_shadowed_38 (
5723 .clk_i (clk_i),
5724 .rst_ni (rst_ni),
5725 .rst_shadowed_ni (rst_shadowed_ni),
5726
5727 // from register interface
5728 .re (alert_en_shadowed_38_re),
5729 .we (alert_en_shadowed_38_gated_we),
5730 .wd (alert_en_shadowed_38_wd),
5731
5732 // from internal hardware
5733 .de (1'b0),
5734 .d ('0),
5735
5736 // to internal hardware
5737 .qe (),
5738 .q (reg2hw.alert_en_shadowed[38].q),
5739 .ds (),
5740
5741 // to register interface (read)
5742 .qs (alert_en_shadowed_38_qs),
5743
5744 // Shadow register phase. Relevant for hwext only.
5745 .phase (),
5746
5747 // Shadow register error conditions
5748 .err_update (alert_en_shadowed_38_update_err),
5749 .err_storage (alert_en_shadowed_38_storage_err)
5750 );
5751
5752
5753 // Subregister 39 of Multireg alert_en_shadowed
5754 // R[alert_en_shadowed_39]: V(False)
5755 // Create REGWEN-gated WE signal
5756 logic alert_en_shadowed_39_gated_we;
5757 1/1 assign alert_en_shadowed_39_gated_we = alert_en_shadowed_39_we & alert_regwen_39_qs;
Tests: T1 T2 T3
5758 prim_subreg_shadow #(
5759 .DW (1),
5760 .SwAccess(prim_subreg_pkg::SwAccessRW),
5761 .RESVAL (1'h0),
5762 .Mubi (1'b0)
5763 ) u_alert_en_shadowed_39 (
5764 .clk_i (clk_i),
5765 .rst_ni (rst_ni),
5766 .rst_shadowed_ni (rst_shadowed_ni),
5767
5768 // from register interface
5769 .re (alert_en_shadowed_39_re),
5770 .we (alert_en_shadowed_39_gated_we),
5771 .wd (alert_en_shadowed_39_wd),
5772
5773 // from internal hardware
5774 .de (1'b0),
5775 .d ('0),
5776
5777 // to internal hardware
5778 .qe (),
5779 .q (reg2hw.alert_en_shadowed[39].q),
5780 .ds (),
5781
5782 // to register interface (read)
5783 .qs (alert_en_shadowed_39_qs),
5784
5785 // Shadow register phase. Relevant for hwext only.
5786 .phase (),
5787
5788 // Shadow register error conditions
5789 .err_update (alert_en_shadowed_39_update_err),
5790 .err_storage (alert_en_shadowed_39_storage_err)
5791 );
5792
5793
5794 // Subregister 40 of Multireg alert_en_shadowed
5795 // R[alert_en_shadowed_40]: V(False)
5796 // Create REGWEN-gated WE signal
5797 logic alert_en_shadowed_40_gated_we;
5798 1/1 assign alert_en_shadowed_40_gated_we = alert_en_shadowed_40_we & alert_regwen_40_qs;
Tests: T1 T2 T3
5799 prim_subreg_shadow #(
5800 .DW (1),
5801 .SwAccess(prim_subreg_pkg::SwAccessRW),
5802 .RESVAL (1'h0),
5803 .Mubi (1'b0)
5804 ) u_alert_en_shadowed_40 (
5805 .clk_i (clk_i),
5806 .rst_ni (rst_ni),
5807 .rst_shadowed_ni (rst_shadowed_ni),
5808
5809 // from register interface
5810 .re (alert_en_shadowed_40_re),
5811 .we (alert_en_shadowed_40_gated_we),
5812 .wd (alert_en_shadowed_40_wd),
5813
5814 // from internal hardware
5815 .de (1'b0),
5816 .d ('0),
5817
5818 // to internal hardware
5819 .qe (),
5820 .q (reg2hw.alert_en_shadowed[40].q),
5821 .ds (),
5822
5823 // to register interface (read)
5824 .qs (alert_en_shadowed_40_qs),
5825
5826 // Shadow register phase. Relevant for hwext only.
5827 .phase (),
5828
5829 // Shadow register error conditions
5830 .err_update (alert_en_shadowed_40_update_err),
5831 .err_storage (alert_en_shadowed_40_storage_err)
5832 );
5833
5834
5835 // Subregister 41 of Multireg alert_en_shadowed
5836 // R[alert_en_shadowed_41]: V(False)
5837 // Create REGWEN-gated WE signal
5838 logic alert_en_shadowed_41_gated_we;
5839 1/1 assign alert_en_shadowed_41_gated_we = alert_en_shadowed_41_we & alert_regwen_41_qs;
Tests: T1 T2 T3
5840 prim_subreg_shadow #(
5841 .DW (1),
5842 .SwAccess(prim_subreg_pkg::SwAccessRW),
5843 .RESVAL (1'h0),
5844 .Mubi (1'b0)
5845 ) u_alert_en_shadowed_41 (
5846 .clk_i (clk_i),
5847 .rst_ni (rst_ni),
5848 .rst_shadowed_ni (rst_shadowed_ni),
5849
5850 // from register interface
5851 .re (alert_en_shadowed_41_re),
5852 .we (alert_en_shadowed_41_gated_we),
5853 .wd (alert_en_shadowed_41_wd),
5854
5855 // from internal hardware
5856 .de (1'b0),
5857 .d ('0),
5858
5859 // to internal hardware
5860 .qe (),
5861 .q (reg2hw.alert_en_shadowed[41].q),
5862 .ds (),
5863
5864 // to register interface (read)
5865 .qs (alert_en_shadowed_41_qs),
5866
5867 // Shadow register phase. Relevant for hwext only.
5868 .phase (),
5869
5870 // Shadow register error conditions
5871 .err_update (alert_en_shadowed_41_update_err),
5872 .err_storage (alert_en_shadowed_41_storage_err)
5873 );
5874
5875
5876 // Subregister 42 of Multireg alert_en_shadowed
5877 // R[alert_en_shadowed_42]: V(False)
5878 // Create REGWEN-gated WE signal
5879 logic alert_en_shadowed_42_gated_we;
5880 1/1 assign alert_en_shadowed_42_gated_we = alert_en_shadowed_42_we & alert_regwen_42_qs;
Tests: T1 T2 T3
5881 prim_subreg_shadow #(
5882 .DW (1),
5883 .SwAccess(prim_subreg_pkg::SwAccessRW),
5884 .RESVAL (1'h0),
5885 .Mubi (1'b0)
5886 ) u_alert_en_shadowed_42 (
5887 .clk_i (clk_i),
5888 .rst_ni (rst_ni),
5889 .rst_shadowed_ni (rst_shadowed_ni),
5890
5891 // from register interface
5892 .re (alert_en_shadowed_42_re),
5893 .we (alert_en_shadowed_42_gated_we),
5894 .wd (alert_en_shadowed_42_wd),
5895
5896 // from internal hardware
5897 .de (1'b0),
5898 .d ('0),
5899
5900 // to internal hardware
5901 .qe (),
5902 .q (reg2hw.alert_en_shadowed[42].q),
5903 .ds (),
5904
5905 // to register interface (read)
5906 .qs (alert_en_shadowed_42_qs),
5907
5908 // Shadow register phase. Relevant for hwext only.
5909 .phase (),
5910
5911 // Shadow register error conditions
5912 .err_update (alert_en_shadowed_42_update_err),
5913 .err_storage (alert_en_shadowed_42_storage_err)
5914 );
5915
5916
5917 // Subregister 43 of Multireg alert_en_shadowed
5918 // R[alert_en_shadowed_43]: V(False)
5919 // Create REGWEN-gated WE signal
5920 logic alert_en_shadowed_43_gated_we;
5921 1/1 assign alert_en_shadowed_43_gated_we = alert_en_shadowed_43_we & alert_regwen_43_qs;
Tests: T1 T2 T3
5922 prim_subreg_shadow #(
5923 .DW (1),
5924 .SwAccess(prim_subreg_pkg::SwAccessRW),
5925 .RESVAL (1'h0),
5926 .Mubi (1'b0)
5927 ) u_alert_en_shadowed_43 (
5928 .clk_i (clk_i),
5929 .rst_ni (rst_ni),
5930 .rst_shadowed_ni (rst_shadowed_ni),
5931
5932 // from register interface
5933 .re (alert_en_shadowed_43_re),
5934 .we (alert_en_shadowed_43_gated_we),
5935 .wd (alert_en_shadowed_43_wd),
5936
5937 // from internal hardware
5938 .de (1'b0),
5939 .d ('0),
5940
5941 // to internal hardware
5942 .qe (),
5943 .q (reg2hw.alert_en_shadowed[43].q),
5944 .ds (),
5945
5946 // to register interface (read)
5947 .qs (alert_en_shadowed_43_qs),
5948
5949 // Shadow register phase. Relevant for hwext only.
5950 .phase (),
5951
5952 // Shadow register error conditions
5953 .err_update (alert_en_shadowed_43_update_err),
5954 .err_storage (alert_en_shadowed_43_storage_err)
5955 );
5956
5957
5958 // Subregister 44 of Multireg alert_en_shadowed
5959 // R[alert_en_shadowed_44]: V(False)
5960 // Create REGWEN-gated WE signal
5961 logic alert_en_shadowed_44_gated_we;
5962 1/1 assign alert_en_shadowed_44_gated_we = alert_en_shadowed_44_we & alert_regwen_44_qs;
Tests: T1 T2 T3
5963 prim_subreg_shadow #(
5964 .DW (1),
5965 .SwAccess(prim_subreg_pkg::SwAccessRW),
5966 .RESVAL (1'h0),
5967 .Mubi (1'b0)
5968 ) u_alert_en_shadowed_44 (
5969 .clk_i (clk_i),
5970 .rst_ni (rst_ni),
5971 .rst_shadowed_ni (rst_shadowed_ni),
5972
5973 // from register interface
5974 .re (alert_en_shadowed_44_re),
5975 .we (alert_en_shadowed_44_gated_we),
5976 .wd (alert_en_shadowed_44_wd),
5977
5978 // from internal hardware
5979 .de (1'b0),
5980 .d ('0),
5981
5982 // to internal hardware
5983 .qe (),
5984 .q (reg2hw.alert_en_shadowed[44].q),
5985 .ds (),
5986
5987 // to register interface (read)
5988 .qs (alert_en_shadowed_44_qs),
5989
5990 // Shadow register phase. Relevant for hwext only.
5991 .phase (),
5992
5993 // Shadow register error conditions
5994 .err_update (alert_en_shadowed_44_update_err),
5995 .err_storage (alert_en_shadowed_44_storage_err)
5996 );
5997
5998
5999 // Subregister 45 of Multireg alert_en_shadowed
6000 // R[alert_en_shadowed_45]: V(False)
6001 // Create REGWEN-gated WE signal
6002 logic alert_en_shadowed_45_gated_we;
6003 1/1 assign alert_en_shadowed_45_gated_we = alert_en_shadowed_45_we & alert_regwen_45_qs;
Tests: T1 T2 T3
6004 prim_subreg_shadow #(
6005 .DW (1),
6006 .SwAccess(prim_subreg_pkg::SwAccessRW),
6007 .RESVAL (1'h0),
6008 .Mubi (1'b0)
6009 ) u_alert_en_shadowed_45 (
6010 .clk_i (clk_i),
6011 .rst_ni (rst_ni),
6012 .rst_shadowed_ni (rst_shadowed_ni),
6013
6014 // from register interface
6015 .re (alert_en_shadowed_45_re),
6016 .we (alert_en_shadowed_45_gated_we),
6017 .wd (alert_en_shadowed_45_wd),
6018
6019 // from internal hardware
6020 .de (1'b0),
6021 .d ('0),
6022
6023 // to internal hardware
6024 .qe (),
6025 .q (reg2hw.alert_en_shadowed[45].q),
6026 .ds (),
6027
6028 // to register interface (read)
6029 .qs (alert_en_shadowed_45_qs),
6030
6031 // Shadow register phase. Relevant for hwext only.
6032 .phase (),
6033
6034 // Shadow register error conditions
6035 .err_update (alert_en_shadowed_45_update_err),
6036 .err_storage (alert_en_shadowed_45_storage_err)
6037 );
6038
6039
6040 // Subregister 46 of Multireg alert_en_shadowed
6041 // R[alert_en_shadowed_46]: V(False)
6042 // Create REGWEN-gated WE signal
6043 logic alert_en_shadowed_46_gated_we;
6044 1/1 assign alert_en_shadowed_46_gated_we = alert_en_shadowed_46_we & alert_regwen_46_qs;
Tests: T1 T2 T3
6045 prim_subreg_shadow #(
6046 .DW (1),
6047 .SwAccess(prim_subreg_pkg::SwAccessRW),
6048 .RESVAL (1'h0),
6049 .Mubi (1'b0)
6050 ) u_alert_en_shadowed_46 (
6051 .clk_i (clk_i),
6052 .rst_ni (rst_ni),
6053 .rst_shadowed_ni (rst_shadowed_ni),
6054
6055 // from register interface
6056 .re (alert_en_shadowed_46_re),
6057 .we (alert_en_shadowed_46_gated_we),
6058 .wd (alert_en_shadowed_46_wd),
6059
6060 // from internal hardware
6061 .de (1'b0),
6062 .d ('0),
6063
6064 // to internal hardware
6065 .qe (),
6066 .q (reg2hw.alert_en_shadowed[46].q),
6067 .ds (),
6068
6069 // to register interface (read)
6070 .qs (alert_en_shadowed_46_qs),
6071
6072 // Shadow register phase. Relevant for hwext only.
6073 .phase (),
6074
6075 // Shadow register error conditions
6076 .err_update (alert_en_shadowed_46_update_err),
6077 .err_storage (alert_en_shadowed_46_storage_err)
6078 );
6079
6080
6081 // Subregister 47 of Multireg alert_en_shadowed
6082 // R[alert_en_shadowed_47]: V(False)
6083 // Create REGWEN-gated WE signal
6084 logic alert_en_shadowed_47_gated_we;
6085 1/1 assign alert_en_shadowed_47_gated_we = alert_en_shadowed_47_we & alert_regwen_47_qs;
Tests: T1 T2 T3
6086 prim_subreg_shadow #(
6087 .DW (1),
6088 .SwAccess(prim_subreg_pkg::SwAccessRW),
6089 .RESVAL (1'h0),
6090 .Mubi (1'b0)
6091 ) u_alert_en_shadowed_47 (
6092 .clk_i (clk_i),
6093 .rst_ni (rst_ni),
6094 .rst_shadowed_ni (rst_shadowed_ni),
6095
6096 // from register interface
6097 .re (alert_en_shadowed_47_re),
6098 .we (alert_en_shadowed_47_gated_we),
6099 .wd (alert_en_shadowed_47_wd),
6100
6101 // from internal hardware
6102 .de (1'b0),
6103 .d ('0),
6104
6105 // to internal hardware
6106 .qe (),
6107 .q (reg2hw.alert_en_shadowed[47].q),
6108 .ds (),
6109
6110 // to register interface (read)
6111 .qs (alert_en_shadowed_47_qs),
6112
6113 // Shadow register phase. Relevant for hwext only.
6114 .phase (),
6115
6116 // Shadow register error conditions
6117 .err_update (alert_en_shadowed_47_update_err),
6118 .err_storage (alert_en_shadowed_47_storage_err)
6119 );
6120
6121
6122 // Subregister 48 of Multireg alert_en_shadowed
6123 // R[alert_en_shadowed_48]: V(False)
6124 // Create REGWEN-gated WE signal
6125 logic alert_en_shadowed_48_gated_we;
6126 1/1 assign alert_en_shadowed_48_gated_we = alert_en_shadowed_48_we & alert_regwen_48_qs;
Tests: T1 T2 T3
6127 prim_subreg_shadow #(
6128 .DW (1),
6129 .SwAccess(prim_subreg_pkg::SwAccessRW),
6130 .RESVAL (1'h0),
6131 .Mubi (1'b0)
6132 ) u_alert_en_shadowed_48 (
6133 .clk_i (clk_i),
6134 .rst_ni (rst_ni),
6135 .rst_shadowed_ni (rst_shadowed_ni),
6136
6137 // from register interface
6138 .re (alert_en_shadowed_48_re),
6139 .we (alert_en_shadowed_48_gated_we),
6140 .wd (alert_en_shadowed_48_wd),
6141
6142 // from internal hardware
6143 .de (1'b0),
6144 .d ('0),
6145
6146 // to internal hardware
6147 .qe (),
6148 .q (reg2hw.alert_en_shadowed[48].q),
6149 .ds (),
6150
6151 // to register interface (read)
6152 .qs (alert_en_shadowed_48_qs),
6153
6154 // Shadow register phase. Relevant for hwext only.
6155 .phase (),
6156
6157 // Shadow register error conditions
6158 .err_update (alert_en_shadowed_48_update_err),
6159 .err_storage (alert_en_shadowed_48_storage_err)
6160 );
6161
6162
6163 // Subregister 49 of Multireg alert_en_shadowed
6164 // R[alert_en_shadowed_49]: V(False)
6165 // Create REGWEN-gated WE signal
6166 logic alert_en_shadowed_49_gated_we;
6167 1/1 assign alert_en_shadowed_49_gated_we = alert_en_shadowed_49_we & alert_regwen_49_qs;
Tests: T1 T2 T3
6168 prim_subreg_shadow #(
6169 .DW (1),
6170 .SwAccess(prim_subreg_pkg::SwAccessRW),
6171 .RESVAL (1'h0),
6172 .Mubi (1'b0)
6173 ) u_alert_en_shadowed_49 (
6174 .clk_i (clk_i),
6175 .rst_ni (rst_ni),
6176 .rst_shadowed_ni (rst_shadowed_ni),
6177
6178 // from register interface
6179 .re (alert_en_shadowed_49_re),
6180 .we (alert_en_shadowed_49_gated_we),
6181 .wd (alert_en_shadowed_49_wd),
6182
6183 // from internal hardware
6184 .de (1'b0),
6185 .d ('0),
6186
6187 // to internal hardware
6188 .qe (),
6189 .q (reg2hw.alert_en_shadowed[49].q),
6190 .ds (),
6191
6192 // to register interface (read)
6193 .qs (alert_en_shadowed_49_qs),
6194
6195 // Shadow register phase. Relevant for hwext only.
6196 .phase (),
6197
6198 // Shadow register error conditions
6199 .err_update (alert_en_shadowed_49_update_err),
6200 .err_storage (alert_en_shadowed_49_storage_err)
6201 );
6202
6203
6204 // Subregister 50 of Multireg alert_en_shadowed
6205 // R[alert_en_shadowed_50]: V(False)
6206 // Create REGWEN-gated WE signal
6207 logic alert_en_shadowed_50_gated_we;
6208 1/1 assign alert_en_shadowed_50_gated_we = alert_en_shadowed_50_we & alert_regwen_50_qs;
Tests: T1 T2 T3
6209 prim_subreg_shadow #(
6210 .DW (1),
6211 .SwAccess(prim_subreg_pkg::SwAccessRW),
6212 .RESVAL (1'h0),
6213 .Mubi (1'b0)
6214 ) u_alert_en_shadowed_50 (
6215 .clk_i (clk_i),
6216 .rst_ni (rst_ni),
6217 .rst_shadowed_ni (rst_shadowed_ni),
6218
6219 // from register interface
6220 .re (alert_en_shadowed_50_re),
6221 .we (alert_en_shadowed_50_gated_we),
6222 .wd (alert_en_shadowed_50_wd),
6223
6224 // from internal hardware
6225 .de (1'b0),
6226 .d ('0),
6227
6228 // to internal hardware
6229 .qe (),
6230 .q (reg2hw.alert_en_shadowed[50].q),
6231 .ds (),
6232
6233 // to register interface (read)
6234 .qs (alert_en_shadowed_50_qs),
6235
6236 // Shadow register phase. Relevant for hwext only.
6237 .phase (),
6238
6239 // Shadow register error conditions
6240 .err_update (alert_en_shadowed_50_update_err),
6241 .err_storage (alert_en_shadowed_50_storage_err)
6242 );
6243
6244
6245 // Subregister 51 of Multireg alert_en_shadowed
6246 // R[alert_en_shadowed_51]: V(False)
6247 // Create REGWEN-gated WE signal
6248 logic alert_en_shadowed_51_gated_we;
6249 1/1 assign alert_en_shadowed_51_gated_we = alert_en_shadowed_51_we & alert_regwen_51_qs;
Tests: T1 T2 T3
6250 prim_subreg_shadow #(
6251 .DW (1),
6252 .SwAccess(prim_subreg_pkg::SwAccessRW),
6253 .RESVAL (1'h0),
6254 .Mubi (1'b0)
6255 ) u_alert_en_shadowed_51 (
6256 .clk_i (clk_i),
6257 .rst_ni (rst_ni),
6258 .rst_shadowed_ni (rst_shadowed_ni),
6259
6260 // from register interface
6261 .re (alert_en_shadowed_51_re),
6262 .we (alert_en_shadowed_51_gated_we),
6263 .wd (alert_en_shadowed_51_wd),
6264
6265 // from internal hardware
6266 .de (1'b0),
6267 .d ('0),
6268
6269 // to internal hardware
6270 .qe (),
6271 .q (reg2hw.alert_en_shadowed[51].q),
6272 .ds (),
6273
6274 // to register interface (read)
6275 .qs (alert_en_shadowed_51_qs),
6276
6277 // Shadow register phase. Relevant for hwext only.
6278 .phase (),
6279
6280 // Shadow register error conditions
6281 .err_update (alert_en_shadowed_51_update_err),
6282 .err_storage (alert_en_shadowed_51_storage_err)
6283 );
6284
6285
6286 // Subregister 52 of Multireg alert_en_shadowed
6287 // R[alert_en_shadowed_52]: V(False)
6288 // Create REGWEN-gated WE signal
6289 logic alert_en_shadowed_52_gated_we;
6290 1/1 assign alert_en_shadowed_52_gated_we = alert_en_shadowed_52_we & alert_regwen_52_qs;
Tests: T1 T2 T3
6291 prim_subreg_shadow #(
6292 .DW (1),
6293 .SwAccess(prim_subreg_pkg::SwAccessRW),
6294 .RESVAL (1'h0),
6295 .Mubi (1'b0)
6296 ) u_alert_en_shadowed_52 (
6297 .clk_i (clk_i),
6298 .rst_ni (rst_ni),
6299 .rst_shadowed_ni (rst_shadowed_ni),
6300
6301 // from register interface
6302 .re (alert_en_shadowed_52_re),
6303 .we (alert_en_shadowed_52_gated_we),
6304 .wd (alert_en_shadowed_52_wd),
6305
6306 // from internal hardware
6307 .de (1'b0),
6308 .d ('0),
6309
6310 // to internal hardware
6311 .qe (),
6312 .q (reg2hw.alert_en_shadowed[52].q),
6313 .ds (),
6314
6315 // to register interface (read)
6316 .qs (alert_en_shadowed_52_qs),
6317
6318 // Shadow register phase. Relevant for hwext only.
6319 .phase (),
6320
6321 // Shadow register error conditions
6322 .err_update (alert_en_shadowed_52_update_err),
6323 .err_storage (alert_en_shadowed_52_storage_err)
6324 );
6325
6326
6327 // Subregister 53 of Multireg alert_en_shadowed
6328 // R[alert_en_shadowed_53]: V(False)
6329 // Create REGWEN-gated WE signal
6330 logic alert_en_shadowed_53_gated_we;
6331 1/1 assign alert_en_shadowed_53_gated_we = alert_en_shadowed_53_we & alert_regwen_53_qs;
Tests: T1 T2 T3
6332 prim_subreg_shadow #(
6333 .DW (1),
6334 .SwAccess(prim_subreg_pkg::SwAccessRW),
6335 .RESVAL (1'h0),
6336 .Mubi (1'b0)
6337 ) u_alert_en_shadowed_53 (
6338 .clk_i (clk_i),
6339 .rst_ni (rst_ni),
6340 .rst_shadowed_ni (rst_shadowed_ni),
6341
6342 // from register interface
6343 .re (alert_en_shadowed_53_re),
6344 .we (alert_en_shadowed_53_gated_we),
6345 .wd (alert_en_shadowed_53_wd),
6346
6347 // from internal hardware
6348 .de (1'b0),
6349 .d ('0),
6350
6351 // to internal hardware
6352 .qe (),
6353 .q (reg2hw.alert_en_shadowed[53].q),
6354 .ds (),
6355
6356 // to register interface (read)
6357 .qs (alert_en_shadowed_53_qs),
6358
6359 // Shadow register phase. Relevant for hwext only.
6360 .phase (),
6361
6362 // Shadow register error conditions
6363 .err_update (alert_en_shadowed_53_update_err),
6364 .err_storage (alert_en_shadowed_53_storage_err)
6365 );
6366
6367
6368 // Subregister 54 of Multireg alert_en_shadowed
6369 // R[alert_en_shadowed_54]: V(False)
6370 // Create REGWEN-gated WE signal
6371 logic alert_en_shadowed_54_gated_we;
6372 1/1 assign alert_en_shadowed_54_gated_we = alert_en_shadowed_54_we & alert_regwen_54_qs;
Tests: T1 T2 T3
6373 prim_subreg_shadow #(
6374 .DW (1),
6375 .SwAccess(prim_subreg_pkg::SwAccessRW),
6376 .RESVAL (1'h0),
6377 .Mubi (1'b0)
6378 ) u_alert_en_shadowed_54 (
6379 .clk_i (clk_i),
6380 .rst_ni (rst_ni),
6381 .rst_shadowed_ni (rst_shadowed_ni),
6382
6383 // from register interface
6384 .re (alert_en_shadowed_54_re),
6385 .we (alert_en_shadowed_54_gated_we),
6386 .wd (alert_en_shadowed_54_wd),
6387
6388 // from internal hardware
6389 .de (1'b0),
6390 .d ('0),
6391
6392 // to internal hardware
6393 .qe (),
6394 .q (reg2hw.alert_en_shadowed[54].q),
6395 .ds (),
6396
6397 // to register interface (read)
6398 .qs (alert_en_shadowed_54_qs),
6399
6400 // Shadow register phase. Relevant for hwext only.
6401 .phase (),
6402
6403 // Shadow register error conditions
6404 .err_update (alert_en_shadowed_54_update_err),
6405 .err_storage (alert_en_shadowed_54_storage_err)
6406 );
6407
6408
6409 // Subregister 55 of Multireg alert_en_shadowed
6410 // R[alert_en_shadowed_55]: V(False)
6411 // Create REGWEN-gated WE signal
6412 logic alert_en_shadowed_55_gated_we;
6413 1/1 assign alert_en_shadowed_55_gated_we = alert_en_shadowed_55_we & alert_regwen_55_qs;
Tests: T1 T2 T3
6414 prim_subreg_shadow #(
6415 .DW (1),
6416 .SwAccess(prim_subreg_pkg::SwAccessRW),
6417 .RESVAL (1'h0),
6418 .Mubi (1'b0)
6419 ) u_alert_en_shadowed_55 (
6420 .clk_i (clk_i),
6421 .rst_ni (rst_ni),
6422 .rst_shadowed_ni (rst_shadowed_ni),
6423
6424 // from register interface
6425 .re (alert_en_shadowed_55_re),
6426 .we (alert_en_shadowed_55_gated_we),
6427 .wd (alert_en_shadowed_55_wd),
6428
6429 // from internal hardware
6430 .de (1'b0),
6431 .d ('0),
6432
6433 // to internal hardware
6434 .qe (),
6435 .q (reg2hw.alert_en_shadowed[55].q),
6436 .ds (),
6437
6438 // to register interface (read)
6439 .qs (alert_en_shadowed_55_qs),
6440
6441 // Shadow register phase. Relevant for hwext only.
6442 .phase (),
6443
6444 // Shadow register error conditions
6445 .err_update (alert_en_shadowed_55_update_err),
6446 .err_storage (alert_en_shadowed_55_storage_err)
6447 );
6448
6449
6450 // Subregister 56 of Multireg alert_en_shadowed
6451 // R[alert_en_shadowed_56]: V(False)
6452 // Create REGWEN-gated WE signal
6453 logic alert_en_shadowed_56_gated_we;
6454 1/1 assign alert_en_shadowed_56_gated_we = alert_en_shadowed_56_we & alert_regwen_56_qs;
Tests: T1 T2 T3
6455 prim_subreg_shadow #(
6456 .DW (1),
6457 .SwAccess(prim_subreg_pkg::SwAccessRW),
6458 .RESVAL (1'h0),
6459 .Mubi (1'b0)
6460 ) u_alert_en_shadowed_56 (
6461 .clk_i (clk_i),
6462 .rst_ni (rst_ni),
6463 .rst_shadowed_ni (rst_shadowed_ni),
6464
6465 // from register interface
6466 .re (alert_en_shadowed_56_re),
6467 .we (alert_en_shadowed_56_gated_we),
6468 .wd (alert_en_shadowed_56_wd),
6469
6470 // from internal hardware
6471 .de (1'b0),
6472 .d ('0),
6473
6474 // to internal hardware
6475 .qe (),
6476 .q (reg2hw.alert_en_shadowed[56].q),
6477 .ds (),
6478
6479 // to register interface (read)
6480 .qs (alert_en_shadowed_56_qs),
6481
6482 // Shadow register phase. Relevant for hwext only.
6483 .phase (),
6484
6485 // Shadow register error conditions
6486 .err_update (alert_en_shadowed_56_update_err),
6487 .err_storage (alert_en_shadowed_56_storage_err)
6488 );
6489
6490
6491 // Subregister 57 of Multireg alert_en_shadowed
6492 // R[alert_en_shadowed_57]: V(False)
6493 // Create REGWEN-gated WE signal
6494 logic alert_en_shadowed_57_gated_we;
6495 1/1 assign alert_en_shadowed_57_gated_we = alert_en_shadowed_57_we & alert_regwen_57_qs;
Tests: T1 T2 T3
6496 prim_subreg_shadow #(
6497 .DW (1),
6498 .SwAccess(prim_subreg_pkg::SwAccessRW),
6499 .RESVAL (1'h0),
6500 .Mubi (1'b0)
6501 ) u_alert_en_shadowed_57 (
6502 .clk_i (clk_i),
6503 .rst_ni (rst_ni),
6504 .rst_shadowed_ni (rst_shadowed_ni),
6505
6506 // from register interface
6507 .re (alert_en_shadowed_57_re),
6508 .we (alert_en_shadowed_57_gated_we),
6509 .wd (alert_en_shadowed_57_wd),
6510
6511 // from internal hardware
6512 .de (1'b0),
6513 .d ('0),
6514
6515 // to internal hardware
6516 .qe (),
6517 .q (reg2hw.alert_en_shadowed[57].q),
6518 .ds (),
6519
6520 // to register interface (read)
6521 .qs (alert_en_shadowed_57_qs),
6522
6523 // Shadow register phase. Relevant for hwext only.
6524 .phase (),
6525
6526 // Shadow register error conditions
6527 .err_update (alert_en_shadowed_57_update_err),
6528 .err_storage (alert_en_shadowed_57_storage_err)
6529 );
6530
6531
6532 // Subregister 58 of Multireg alert_en_shadowed
6533 // R[alert_en_shadowed_58]: V(False)
6534 // Create REGWEN-gated WE signal
6535 logic alert_en_shadowed_58_gated_we;
6536 1/1 assign alert_en_shadowed_58_gated_we = alert_en_shadowed_58_we & alert_regwen_58_qs;
Tests: T1 T2 T3
6537 prim_subreg_shadow #(
6538 .DW (1),
6539 .SwAccess(prim_subreg_pkg::SwAccessRW),
6540 .RESVAL (1'h0),
6541 .Mubi (1'b0)
6542 ) u_alert_en_shadowed_58 (
6543 .clk_i (clk_i),
6544 .rst_ni (rst_ni),
6545 .rst_shadowed_ni (rst_shadowed_ni),
6546
6547 // from register interface
6548 .re (alert_en_shadowed_58_re),
6549 .we (alert_en_shadowed_58_gated_we),
6550 .wd (alert_en_shadowed_58_wd),
6551
6552 // from internal hardware
6553 .de (1'b0),
6554 .d ('0),
6555
6556 // to internal hardware
6557 .qe (),
6558 .q (reg2hw.alert_en_shadowed[58].q),
6559 .ds (),
6560
6561 // to register interface (read)
6562 .qs (alert_en_shadowed_58_qs),
6563
6564 // Shadow register phase. Relevant for hwext only.
6565 .phase (),
6566
6567 // Shadow register error conditions
6568 .err_update (alert_en_shadowed_58_update_err),
6569 .err_storage (alert_en_shadowed_58_storage_err)
6570 );
6571
6572
6573 // Subregister 59 of Multireg alert_en_shadowed
6574 // R[alert_en_shadowed_59]: V(False)
6575 // Create REGWEN-gated WE signal
6576 logic alert_en_shadowed_59_gated_we;
6577 1/1 assign alert_en_shadowed_59_gated_we = alert_en_shadowed_59_we & alert_regwen_59_qs;
Tests: T1 T2 T3
6578 prim_subreg_shadow #(
6579 .DW (1),
6580 .SwAccess(prim_subreg_pkg::SwAccessRW),
6581 .RESVAL (1'h0),
6582 .Mubi (1'b0)
6583 ) u_alert_en_shadowed_59 (
6584 .clk_i (clk_i),
6585 .rst_ni (rst_ni),
6586 .rst_shadowed_ni (rst_shadowed_ni),
6587
6588 // from register interface
6589 .re (alert_en_shadowed_59_re),
6590 .we (alert_en_shadowed_59_gated_we),
6591 .wd (alert_en_shadowed_59_wd),
6592
6593 // from internal hardware
6594 .de (1'b0),
6595 .d ('0),
6596
6597 // to internal hardware
6598 .qe (),
6599 .q (reg2hw.alert_en_shadowed[59].q),
6600 .ds (),
6601
6602 // to register interface (read)
6603 .qs (alert_en_shadowed_59_qs),
6604
6605 // Shadow register phase. Relevant for hwext only.
6606 .phase (),
6607
6608 // Shadow register error conditions
6609 .err_update (alert_en_shadowed_59_update_err),
6610 .err_storage (alert_en_shadowed_59_storage_err)
6611 );
6612
6613
6614 // Subregister 60 of Multireg alert_en_shadowed
6615 // R[alert_en_shadowed_60]: V(False)
6616 // Create REGWEN-gated WE signal
6617 logic alert_en_shadowed_60_gated_we;
6618 1/1 assign alert_en_shadowed_60_gated_we = alert_en_shadowed_60_we & alert_regwen_60_qs;
Tests: T1 T2 T3
6619 prim_subreg_shadow #(
6620 .DW (1),
6621 .SwAccess(prim_subreg_pkg::SwAccessRW),
6622 .RESVAL (1'h0),
6623 .Mubi (1'b0)
6624 ) u_alert_en_shadowed_60 (
6625 .clk_i (clk_i),
6626 .rst_ni (rst_ni),
6627 .rst_shadowed_ni (rst_shadowed_ni),
6628
6629 // from register interface
6630 .re (alert_en_shadowed_60_re),
6631 .we (alert_en_shadowed_60_gated_we),
6632 .wd (alert_en_shadowed_60_wd),
6633
6634 // from internal hardware
6635 .de (1'b0),
6636 .d ('0),
6637
6638 // to internal hardware
6639 .qe (),
6640 .q (reg2hw.alert_en_shadowed[60].q),
6641 .ds (),
6642
6643 // to register interface (read)
6644 .qs (alert_en_shadowed_60_qs),
6645
6646 // Shadow register phase. Relevant for hwext only.
6647 .phase (),
6648
6649 // Shadow register error conditions
6650 .err_update (alert_en_shadowed_60_update_err),
6651 .err_storage (alert_en_shadowed_60_storage_err)
6652 );
6653
6654
6655 // Subregister 61 of Multireg alert_en_shadowed
6656 // R[alert_en_shadowed_61]: V(False)
6657 // Create REGWEN-gated WE signal
6658 logic alert_en_shadowed_61_gated_we;
6659 1/1 assign alert_en_shadowed_61_gated_we = alert_en_shadowed_61_we & alert_regwen_61_qs;
Tests: T1 T2 T3
6660 prim_subreg_shadow #(
6661 .DW (1),
6662 .SwAccess(prim_subreg_pkg::SwAccessRW),
6663 .RESVAL (1'h0),
6664 .Mubi (1'b0)
6665 ) u_alert_en_shadowed_61 (
6666 .clk_i (clk_i),
6667 .rst_ni (rst_ni),
6668 .rst_shadowed_ni (rst_shadowed_ni),
6669
6670 // from register interface
6671 .re (alert_en_shadowed_61_re),
6672 .we (alert_en_shadowed_61_gated_we),
6673 .wd (alert_en_shadowed_61_wd),
6674
6675 // from internal hardware
6676 .de (1'b0),
6677 .d ('0),
6678
6679 // to internal hardware
6680 .qe (),
6681 .q (reg2hw.alert_en_shadowed[61].q),
6682 .ds (),
6683
6684 // to register interface (read)
6685 .qs (alert_en_shadowed_61_qs),
6686
6687 // Shadow register phase. Relevant for hwext only.
6688 .phase (),
6689
6690 // Shadow register error conditions
6691 .err_update (alert_en_shadowed_61_update_err),
6692 .err_storage (alert_en_shadowed_61_storage_err)
6693 );
6694
6695
6696 // Subregister 62 of Multireg alert_en_shadowed
6697 // R[alert_en_shadowed_62]: V(False)
6698 // Create REGWEN-gated WE signal
6699 logic alert_en_shadowed_62_gated_we;
6700 1/1 assign alert_en_shadowed_62_gated_we = alert_en_shadowed_62_we & alert_regwen_62_qs;
Tests: T1 T2 T3
6701 prim_subreg_shadow #(
6702 .DW (1),
6703 .SwAccess(prim_subreg_pkg::SwAccessRW),
6704 .RESVAL (1'h0),
6705 .Mubi (1'b0)
6706 ) u_alert_en_shadowed_62 (
6707 .clk_i (clk_i),
6708 .rst_ni (rst_ni),
6709 .rst_shadowed_ni (rst_shadowed_ni),
6710
6711 // from register interface
6712 .re (alert_en_shadowed_62_re),
6713 .we (alert_en_shadowed_62_gated_we),
6714 .wd (alert_en_shadowed_62_wd),
6715
6716 // from internal hardware
6717 .de (1'b0),
6718 .d ('0),
6719
6720 // to internal hardware
6721 .qe (),
6722 .q (reg2hw.alert_en_shadowed[62].q),
6723 .ds (),
6724
6725 // to register interface (read)
6726 .qs (alert_en_shadowed_62_qs),
6727
6728 // Shadow register phase. Relevant for hwext only.
6729 .phase (),
6730
6731 // Shadow register error conditions
6732 .err_update (alert_en_shadowed_62_update_err),
6733 .err_storage (alert_en_shadowed_62_storage_err)
6734 );
6735
6736
6737 // Subregister 63 of Multireg alert_en_shadowed
6738 // R[alert_en_shadowed_63]: V(False)
6739 // Create REGWEN-gated WE signal
6740 logic alert_en_shadowed_63_gated_we;
6741 1/1 assign alert_en_shadowed_63_gated_we = alert_en_shadowed_63_we & alert_regwen_63_qs;
Tests: T1 T2 T3
6742 prim_subreg_shadow #(
6743 .DW (1),
6744 .SwAccess(prim_subreg_pkg::SwAccessRW),
6745 .RESVAL (1'h0),
6746 .Mubi (1'b0)
6747 ) u_alert_en_shadowed_63 (
6748 .clk_i (clk_i),
6749 .rst_ni (rst_ni),
6750 .rst_shadowed_ni (rst_shadowed_ni),
6751
6752 // from register interface
6753 .re (alert_en_shadowed_63_re),
6754 .we (alert_en_shadowed_63_gated_we),
6755 .wd (alert_en_shadowed_63_wd),
6756
6757 // from internal hardware
6758 .de (1'b0),
6759 .d ('0),
6760
6761 // to internal hardware
6762 .qe (),
6763 .q (reg2hw.alert_en_shadowed[63].q),
6764 .ds (),
6765
6766 // to register interface (read)
6767 .qs (alert_en_shadowed_63_qs),
6768
6769 // Shadow register phase. Relevant for hwext only.
6770 .phase (),
6771
6772 // Shadow register error conditions
6773 .err_update (alert_en_shadowed_63_update_err),
6774 .err_storage (alert_en_shadowed_63_storage_err)
6775 );
6776
6777
6778 // Subregister 64 of Multireg alert_en_shadowed
6779 // R[alert_en_shadowed_64]: V(False)
6780 // Create REGWEN-gated WE signal
6781 logic alert_en_shadowed_64_gated_we;
6782 1/1 assign alert_en_shadowed_64_gated_we = alert_en_shadowed_64_we & alert_regwen_64_qs;
Tests: T1 T2 T3
6783 prim_subreg_shadow #(
6784 .DW (1),
6785 .SwAccess(prim_subreg_pkg::SwAccessRW),
6786 .RESVAL (1'h0),
6787 .Mubi (1'b0)
6788 ) u_alert_en_shadowed_64 (
6789 .clk_i (clk_i),
6790 .rst_ni (rst_ni),
6791 .rst_shadowed_ni (rst_shadowed_ni),
6792
6793 // from register interface
6794 .re (alert_en_shadowed_64_re),
6795 .we (alert_en_shadowed_64_gated_we),
6796 .wd (alert_en_shadowed_64_wd),
6797
6798 // from internal hardware
6799 .de (1'b0),
6800 .d ('0),
6801
6802 // to internal hardware
6803 .qe (),
6804 .q (reg2hw.alert_en_shadowed[64].q),
6805 .ds (),
6806
6807 // to register interface (read)
6808 .qs (alert_en_shadowed_64_qs),
6809
6810 // Shadow register phase. Relevant for hwext only.
6811 .phase (),
6812
6813 // Shadow register error conditions
6814 .err_update (alert_en_shadowed_64_update_err),
6815 .err_storage (alert_en_shadowed_64_storage_err)
6816 );
6817
6818
6819 // Subregister 0 of Multireg alert_class_shadowed
6820 // R[alert_class_shadowed_0]: V(False)
6821 // Create REGWEN-gated WE signal
6822 logic alert_class_shadowed_0_gated_we;
6823 1/1 assign alert_class_shadowed_0_gated_we = alert_class_shadowed_0_we & alert_regwen_0_qs;
Tests: T1 T2 T3
6824 prim_subreg_shadow #(
6825 .DW (2),
6826 .SwAccess(prim_subreg_pkg::SwAccessRW),
6827 .RESVAL (2'h0),
6828 .Mubi (1'b0)
6829 ) u_alert_class_shadowed_0 (
6830 .clk_i (clk_i),
6831 .rst_ni (rst_ni),
6832 .rst_shadowed_ni (rst_shadowed_ni),
6833
6834 // from register interface
6835 .re (alert_class_shadowed_0_re),
6836 .we (alert_class_shadowed_0_gated_we),
6837 .wd (alert_class_shadowed_0_wd),
6838
6839 // from internal hardware
6840 .de (1'b0),
6841 .d ('0),
6842
6843 // to internal hardware
6844 .qe (),
6845 .q (reg2hw.alert_class_shadowed[0].q),
6846 .ds (),
6847
6848 // to register interface (read)
6849 .qs (alert_class_shadowed_0_qs),
6850
6851 // Shadow register phase. Relevant for hwext only.
6852 .phase (),
6853
6854 // Shadow register error conditions
6855 .err_update (alert_class_shadowed_0_update_err),
6856 .err_storage (alert_class_shadowed_0_storage_err)
6857 );
6858
6859
6860 // Subregister 1 of Multireg alert_class_shadowed
6861 // R[alert_class_shadowed_1]: V(False)
6862 // Create REGWEN-gated WE signal
6863 logic alert_class_shadowed_1_gated_we;
6864 1/1 assign alert_class_shadowed_1_gated_we = alert_class_shadowed_1_we & alert_regwen_1_qs;
Tests: T1 T2 T3
6865 prim_subreg_shadow #(
6866 .DW (2),
6867 .SwAccess(prim_subreg_pkg::SwAccessRW),
6868 .RESVAL (2'h0),
6869 .Mubi (1'b0)
6870 ) u_alert_class_shadowed_1 (
6871 .clk_i (clk_i),
6872 .rst_ni (rst_ni),
6873 .rst_shadowed_ni (rst_shadowed_ni),
6874
6875 // from register interface
6876 .re (alert_class_shadowed_1_re),
6877 .we (alert_class_shadowed_1_gated_we),
6878 .wd (alert_class_shadowed_1_wd),
6879
6880 // from internal hardware
6881 .de (1'b0),
6882 .d ('0),
6883
6884 // to internal hardware
6885 .qe (),
6886 .q (reg2hw.alert_class_shadowed[1].q),
6887 .ds (),
6888
6889 // to register interface (read)
6890 .qs (alert_class_shadowed_1_qs),
6891
6892 // Shadow register phase. Relevant for hwext only.
6893 .phase (),
6894
6895 // Shadow register error conditions
6896 .err_update (alert_class_shadowed_1_update_err),
6897 .err_storage (alert_class_shadowed_1_storage_err)
6898 );
6899
6900
6901 // Subregister 2 of Multireg alert_class_shadowed
6902 // R[alert_class_shadowed_2]: V(False)
6903 // Create REGWEN-gated WE signal
6904 logic alert_class_shadowed_2_gated_we;
6905 1/1 assign alert_class_shadowed_2_gated_we = alert_class_shadowed_2_we & alert_regwen_2_qs;
Tests: T1 T2 T3
6906 prim_subreg_shadow #(
6907 .DW (2),
6908 .SwAccess(prim_subreg_pkg::SwAccessRW),
6909 .RESVAL (2'h0),
6910 .Mubi (1'b0)
6911 ) u_alert_class_shadowed_2 (
6912 .clk_i (clk_i),
6913 .rst_ni (rst_ni),
6914 .rst_shadowed_ni (rst_shadowed_ni),
6915
6916 // from register interface
6917 .re (alert_class_shadowed_2_re),
6918 .we (alert_class_shadowed_2_gated_we),
6919 .wd (alert_class_shadowed_2_wd),
6920
6921 // from internal hardware
6922 .de (1'b0),
6923 .d ('0),
6924
6925 // to internal hardware
6926 .qe (),
6927 .q (reg2hw.alert_class_shadowed[2].q),
6928 .ds (),
6929
6930 // to register interface (read)
6931 .qs (alert_class_shadowed_2_qs),
6932
6933 // Shadow register phase. Relevant for hwext only.
6934 .phase (),
6935
6936 // Shadow register error conditions
6937 .err_update (alert_class_shadowed_2_update_err),
6938 .err_storage (alert_class_shadowed_2_storage_err)
6939 );
6940
6941
6942 // Subregister 3 of Multireg alert_class_shadowed
6943 // R[alert_class_shadowed_3]: V(False)
6944 // Create REGWEN-gated WE signal
6945 logic alert_class_shadowed_3_gated_we;
6946 1/1 assign alert_class_shadowed_3_gated_we = alert_class_shadowed_3_we & alert_regwen_3_qs;
Tests: T1 T2 T3
6947 prim_subreg_shadow #(
6948 .DW (2),
6949 .SwAccess(prim_subreg_pkg::SwAccessRW),
6950 .RESVAL (2'h0),
6951 .Mubi (1'b0)
6952 ) u_alert_class_shadowed_3 (
6953 .clk_i (clk_i),
6954 .rst_ni (rst_ni),
6955 .rst_shadowed_ni (rst_shadowed_ni),
6956
6957 // from register interface
6958 .re (alert_class_shadowed_3_re),
6959 .we (alert_class_shadowed_3_gated_we),
6960 .wd (alert_class_shadowed_3_wd),
6961
6962 // from internal hardware
6963 .de (1'b0),
6964 .d ('0),
6965
6966 // to internal hardware
6967 .qe (),
6968 .q (reg2hw.alert_class_shadowed[3].q),
6969 .ds (),
6970
6971 // to register interface (read)
6972 .qs (alert_class_shadowed_3_qs),
6973
6974 // Shadow register phase. Relevant for hwext only.
6975 .phase (),
6976
6977 // Shadow register error conditions
6978 .err_update (alert_class_shadowed_3_update_err),
6979 .err_storage (alert_class_shadowed_3_storage_err)
6980 );
6981
6982
6983 // Subregister 4 of Multireg alert_class_shadowed
6984 // R[alert_class_shadowed_4]: V(False)
6985 // Create REGWEN-gated WE signal
6986 logic alert_class_shadowed_4_gated_we;
6987 1/1 assign alert_class_shadowed_4_gated_we = alert_class_shadowed_4_we & alert_regwen_4_qs;
Tests: T1 T2 T3
6988 prim_subreg_shadow #(
6989 .DW (2),
6990 .SwAccess(prim_subreg_pkg::SwAccessRW),
6991 .RESVAL (2'h0),
6992 .Mubi (1'b0)
6993 ) u_alert_class_shadowed_4 (
6994 .clk_i (clk_i),
6995 .rst_ni (rst_ni),
6996 .rst_shadowed_ni (rst_shadowed_ni),
6997
6998 // from register interface
6999 .re (alert_class_shadowed_4_re),
7000 .we (alert_class_shadowed_4_gated_we),
7001 .wd (alert_class_shadowed_4_wd),
7002
7003 // from internal hardware
7004 .de (1'b0),
7005 .d ('0),
7006
7007 // to internal hardware
7008 .qe (),
7009 .q (reg2hw.alert_class_shadowed[4].q),
7010 .ds (),
7011
7012 // to register interface (read)
7013 .qs (alert_class_shadowed_4_qs),
7014
7015 // Shadow register phase. Relevant for hwext only.
7016 .phase (),
7017
7018 // Shadow register error conditions
7019 .err_update (alert_class_shadowed_4_update_err),
7020 .err_storage (alert_class_shadowed_4_storage_err)
7021 );
7022
7023
7024 // Subregister 5 of Multireg alert_class_shadowed
7025 // R[alert_class_shadowed_5]: V(False)
7026 // Create REGWEN-gated WE signal
7027 logic alert_class_shadowed_5_gated_we;
7028 1/1 assign alert_class_shadowed_5_gated_we = alert_class_shadowed_5_we & alert_regwen_5_qs;
Tests: T1 T2 T3
7029 prim_subreg_shadow #(
7030 .DW (2),
7031 .SwAccess(prim_subreg_pkg::SwAccessRW),
7032 .RESVAL (2'h0),
7033 .Mubi (1'b0)
7034 ) u_alert_class_shadowed_5 (
7035 .clk_i (clk_i),
7036 .rst_ni (rst_ni),
7037 .rst_shadowed_ni (rst_shadowed_ni),
7038
7039 // from register interface
7040 .re (alert_class_shadowed_5_re),
7041 .we (alert_class_shadowed_5_gated_we),
7042 .wd (alert_class_shadowed_5_wd),
7043
7044 // from internal hardware
7045 .de (1'b0),
7046 .d ('0),
7047
7048 // to internal hardware
7049 .qe (),
7050 .q (reg2hw.alert_class_shadowed[5].q),
7051 .ds (),
7052
7053 // to register interface (read)
7054 .qs (alert_class_shadowed_5_qs),
7055
7056 // Shadow register phase. Relevant for hwext only.
7057 .phase (),
7058
7059 // Shadow register error conditions
7060 .err_update (alert_class_shadowed_5_update_err),
7061 .err_storage (alert_class_shadowed_5_storage_err)
7062 );
7063
7064
7065 // Subregister 6 of Multireg alert_class_shadowed
7066 // R[alert_class_shadowed_6]: V(False)
7067 // Create REGWEN-gated WE signal
7068 logic alert_class_shadowed_6_gated_we;
7069 1/1 assign alert_class_shadowed_6_gated_we = alert_class_shadowed_6_we & alert_regwen_6_qs;
Tests: T1 T2 T3
7070 prim_subreg_shadow #(
7071 .DW (2),
7072 .SwAccess(prim_subreg_pkg::SwAccessRW),
7073 .RESVAL (2'h0),
7074 .Mubi (1'b0)
7075 ) u_alert_class_shadowed_6 (
7076 .clk_i (clk_i),
7077 .rst_ni (rst_ni),
7078 .rst_shadowed_ni (rst_shadowed_ni),
7079
7080 // from register interface
7081 .re (alert_class_shadowed_6_re),
7082 .we (alert_class_shadowed_6_gated_we),
7083 .wd (alert_class_shadowed_6_wd),
7084
7085 // from internal hardware
7086 .de (1'b0),
7087 .d ('0),
7088
7089 // to internal hardware
7090 .qe (),
7091 .q (reg2hw.alert_class_shadowed[6].q),
7092 .ds (),
7093
7094 // to register interface (read)
7095 .qs (alert_class_shadowed_6_qs),
7096
7097 // Shadow register phase. Relevant for hwext only.
7098 .phase (),
7099
7100 // Shadow register error conditions
7101 .err_update (alert_class_shadowed_6_update_err),
7102 .err_storage (alert_class_shadowed_6_storage_err)
7103 );
7104
7105
7106 // Subregister 7 of Multireg alert_class_shadowed
7107 // R[alert_class_shadowed_7]: V(False)
7108 // Create REGWEN-gated WE signal
7109 logic alert_class_shadowed_7_gated_we;
7110 1/1 assign alert_class_shadowed_7_gated_we = alert_class_shadowed_7_we & alert_regwen_7_qs;
Tests: T1 T2 T3
7111 prim_subreg_shadow #(
7112 .DW (2),
7113 .SwAccess(prim_subreg_pkg::SwAccessRW),
7114 .RESVAL (2'h0),
7115 .Mubi (1'b0)
7116 ) u_alert_class_shadowed_7 (
7117 .clk_i (clk_i),
7118 .rst_ni (rst_ni),
7119 .rst_shadowed_ni (rst_shadowed_ni),
7120
7121 // from register interface
7122 .re (alert_class_shadowed_7_re),
7123 .we (alert_class_shadowed_7_gated_we),
7124 .wd (alert_class_shadowed_7_wd),
7125
7126 // from internal hardware
7127 .de (1'b0),
7128 .d ('0),
7129
7130 // to internal hardware
7131 .qe (),
7132 .q (reg2hw.alert_class_shadowed[7].q),
7133 .ds (),
7134
7135 // to register interface (read)
7136 .qs (alert_class_shadowed_7_qs),
7137
7138 // Shadow register phase. Relevant for hwext only.
7139 .phase (),
7140
7141 // Shadow register error conditions
7142 .err_update (alert_class_shadowed_7_update_err),
7143 .err_storage (alert_class_shadowed_7_storage_err)
7144 );
7145
7146
7147 // Subregister 8 of Multireg alert_class_shadowed
7148 // R[alert_class_shadowed_8]: V(False)
7149 // Create REGWEN-gated WE signal
7150 logic alert_class_shadowed_8_gated_we;
7151 1/1 assign alert_class_shadowed_8_gated_we = alert_class_shadowed_8_we & alert_regwen_8_qs;
Tests: T1 T2 T3
7152 prim_subreg_shadow #(
7153 .DW (2),
7154 .SwAccess(prim_subreg_pkg::SwAccessRW),
7155 .RESVAL (2'h0),
7156 .Mubi (1'b0)
7157 ) u_alert_class_shadowed_8 (
7158 .clk_i (clk_i),
7159 .rst_ni (rst_ni),
7160 .rst_shadowed_ni (rst_shadowed_ni),
7161
7162 // from register interface
7163 .re (alert_class_shadowed_8_re),
7164 .we (alert_class_shadowed_8_gated_we),
7165 .wd (alert_class_shadowed_8_wd),
7166
7167 // from internal hardware
7168 .de (1'b0),
7169 .d ('0),
7170
7171 // to internal hardware
7172 .qe (),
7173 .q (reg2hw.alert_class_shadowed[8].q),
7174 .ds (),
7175
7176 // to register interface (read)
7177 .qs (alert_class_shadowed_8_qs),
7178
7179 // Shadow register phase. Relevant for hwext only.
7180 .phase (),
7181
7182 // Shadow register error conditions
7183 .err_update (alert_class_shadowed_8_update_err),
7184 .err_storage (alert_class_shadowed_8_storage_err)
7185 );
7186
7187
7188 // Subregister 9 of Multireg alert_class_shadowed
7189 // R[alert_class_shadowed_9]: V(False)
7190 // Create REGWEN-gated WE signal
7191 logic alert_class_shadowed_9_gated_we;
7192 1/1 assign alert_class_shadowed_9_gated_we = alert_class_shadowed_9_we & alert_regwen_9_qs;
Tests: T1 T2 T3
7193 prim_subreg_shadow #(
7194 .DW (2),
7195 .SwAccess(prim_subreg_pkg::SwAccessRW),
7196 .RESVAL (2'h0),
7197 .Mubi (1'b0)
7198 ) u_alert_class_shadowed_9 (
7199 .clk_i (clk_i),
7200 .rst_ni (rst_ni),
7201 .rst_shadowed_ni (rst_shadowed_ni),
7202
7203 // from register interface
7204 .re (alert_class_shadowed_9_re),
7205 .we (alert_class_shadowed_9_gated_we),
7206 .wd (alert_class_shadowed_9_wd),
7207
7208 // from internal hardware
7209 .de (1'b0),
7210 .d ('0),
7211
7212 // to internal hardware
7213 .qe (),
7214 .q (reg2hw.alert_class_shadowed[9].q),
7215 .ds (),
7216
7217 // to register interface (read)
7218 .qs (alert_class_shadowed_9_qs),
7219
7220 // Shadow register phase. Relevant for hwext only.
7221 .phase (),
7222
7223 // Shadow register error conditions
7224 .err_update (alert_class_shadowed_9_update_err),
7225 .err_storage (alert_class_shadowed_9_storage_err)
7226 );
7227
7228
7229 // Subregister 10 of Multireg alert_class_shadowed
7230 // R[alert_class_shadowed_10]: V(False)
7231 // Create REGWEN-gated WE signal
7232 logic alert_class_shadowed_10_gated_we;
7233 1/1 assign alert_class_shadowed_10_gated_we = alert_class_shadowed_10_we & alert_regwen_10_qs;
Tests: T1 T2 T3
7234 prim_subreg_shadow #(
7235 .DW (2),
7236 .SwAccess(prim_subreg_pkg::SwAccessRW),
7237 .RESVAL (2'h0),
7238 .Mubi (1'b0)
7239 ) u_alert_class_shadowed_10 (
7240 .clk_i (clk_i),
7241 .rst_ni (rst_ni),
7242 .rst_shadowed_ni (rst_shadowed_ni),
7243
7244 // from register interface
7245 .re (alert_class_shadowed_10_re),
7246 .we (alert_class_shadowed_10_gated_we),
7247 .wd (alert_class_shadowed_10_wd),
7248
7249 // from internal hardware
7250 .de (1'b0),
7251 .d ('0),
7252
7253 // to internal hardware
7254 .qe (),
7255 .q (reg2hw.alert_class_shadowed[10].q),
7256 .ds (),
7257
7258 // to register interface (read)
7259 .qs (alert_class_shadowed_10_qs),
7260
7261 // Shadow register phase. Relevant for hwext only.
7262 .phase (),
7263
7264 // Shadow register error conditions
7265 .err_update (alert_class_shadowed_10_update_err),
7266 .err_storage (alert_class_shadowed_10_storage_err)
7267 );
7268
7269
7270 // Subregister 11 of Multireg alert_class_shadowed
7271 // R[alert_class_shadowed_11]: V(False)
7272 // Create REGWEN-gated WE signal
7273 logic alert_class_shadowed_11_gated_we;
7274 1/1 assign alert_class_shadowed_11_gated_we = alert_class_shadowed_11_we & alert_regwen_11_qs;
Tests: T1 T2 T3
7275 prim_subreg_shadow #(
7276 .DW (2),
7277 .SwAccess(prim_subreg_pkg::SwAccessRW),
7278 .RESVAL (2'h0),
7279 .Mubi (1'b0)
7280 ) u_alert_class_shadowed_11 (
7281 .clk_i (clk_i),
7282 .rst_ni (rst_ni),
7283 .rst_shadowed_ni (rst_shadowed_ni),
7284
7285 // from register interface
7286 .re (alert_class_shadowed_11_re),
7287 .we (alert_class_shadowed_11_gated_we),
7288 .wd (alert_class_shadowed_11_wd),
7289
7290 // from internal hardware
7291 .de (1'b0),
7292 .d ('0),
7293
7294 // to internal hardware
7295 .qe (),
7296 .q (reg2hw.alert_class_shadowed[11].q),
7297 .ds (),
7298
7299 // to register interface (read)
7300 .qs (alert_class_shadowed_11_qs),
7301
7302 // Shadow register phase. Relevant for hwext only.
7303 .phase (),
7304
7305 // Shadow register error conditions
7306 .err_update (alert_class_shadowed_11_update_err),
7307 .err_storage (alert_class_shadowed_11_storage_err)
7308 );
7309
7310
7311 // Subregister 12 of Multireg alert_class_shadowed
7312 // R[alert_class_shadowed_12]: V(False)
7313 // Create REGWEN-gated WE signal
7314 logic alert_class_shadowed_12_gated_we;
7315 1/1 assign alert_class_shadowed_12_gated_we = alert_class_shadowed_12_we & alert_regwen_12_qs;
Tests: T1 T2 T3
7316 prim_subreg_shadow #(
7317 .DW (2),
7318 .SwAccess(prim_subreg_pkg::SwAccessRW),
7319 .RESVAL (2'h0),
7320 .Mubi (1'b0)
7321 ) u_alert_class_shadowed_12 (
7322 .clk_i (clk_i),
7323 .rst_ni (rst_ni),
7324 .rst_shadowed_ni (rst_shadowed_ni),
7325
7326 // from register interface
7327 .re (alert_class_shadowed_12_re),
7328 .we (alert_class_shadowed_12_gated_we),
7329 .wd (alert_class_shadowed_12_wd),
7330
7331 // from internal hardware
7332 .de (1'b0),
7333 .d ('0),
7334
7335 // to internal hardware
7336 .qe (),
7337 .q (reg2hw.alert_class_shadowed[12].q),
7338 .ds (),
7339
7340 // to register interface (read)
7341 .qs (alert_class_shadowed_12_qs),
7342
7343 // Shadow register phase. Relevant for hwext only.
7344 .phase (),
7345
7346 // Shadow register error conditions
7347 .err_update (alert_class_shadowed_12_update_err),
7348 .err_storage (alert_class_shadowed_12_storage_err)
7349 );
7350
7351
7352 // Subregister 13 of Multireg alert_class_shadowed
7353 // R[alert_class_shadowed_13]: V(False)
7354 // Create REGWEN-gated WE signal
7355 logic alert_class_shadowed_13_gated_we;
7356 1/1 assign alert_class_shadowed_13_gated_we = alert_class_shadowed_13_we & alert_regwen_13_qs;
Tests: T1 T2 T3
7357 prim_subreg_shadow #(
7358 .DW (2),
7359 .SwAccess(prim_subreg_pkg::SwAccessRW),
7360 .RESVAL (2'h0),
7361 .Mubi (1'b0)
7362 ) u_alert_class_shadowed_13 (
7363 .clk_i (clk_i),
7364 .rst_ni (rst_ni),
7365 .rst_shadowed_ni (rst_shadowed_ni),
7366
7367 // from register interface
7368 .re (alert_class_shadowed_13_re),
7369 .we (alert_class_shadowed_13_gated_we),
7370 .wd (alert_class_shadowed_13_wd),
7371
7372 // from internal hardware
7373 .de (1'b0),
7374 .d ('0),
7375
7376 // to internal hardware
7377 .qe (),
7378 .q (reg2hw.alert_class_shadowed[13].q),
7379 .ds (),
7380
7381 // to register interface (read)
7382 .qs (alert_class_shadowed_13_qs),
7383
7384 // Shadow register phase. Relevant for hwext only.
7385 .phase (),
7386
7387 // Shadow register error conditions
7388 .err_update (alert_class_shadowed_13_update_err),
7389 .err_storage (alert_class_shadowed_13_storage_err)
7390 );
7391
7392
7393 // Subregister 14 of Multireg alert_class_shadowed
7394 // R[alert_class_shadowed_14]: V(False)
7395 // Create REGWEN-gated WE signal
7396 logic alert_class_shadowed_14_gated_we;
7397 1/1 assign alert_class_shadowed_14_gated_we = alert_class_shadowed_14_we & alert_regwen_14_qs;
Tests: T1 T2 T3
7398 prim_subreg_shadow #(
7399 .DW (2),
7400 .SwAccess(prim_subreg_pkg::SwAccessRW),
7401 .RESVAL (2'h0),
7402 .Mubi (1'b0)
7403 ) u_alert_class_shadowed_14 (
7404 .clk_i (clk_i),
7405 .rst_ni (rst_ni),
7406 .rst_shadowed_ni (rst_shadowed_ni),
7407
7408 // from register interface
7409 .re (alert_class_shadowed_14_re),
7410 .we (alert_class_shadowed_14_gated_we),
7411 .wd (alert_class_shadowed_14_wd),
7412
7413 // from internal hardware
7414 .de (1'b0),
7415 .d ('0),
7416
7417 // to internal hardware
7418 .qe (),
7419 .q (reg2hw.alert_class_shadowed[14].q),
7420 .ds (),
7421
7422 // to register interface (read)
7423 .qs (alert_class_shadowed_14_qs),
7424
7425 // Shadow register phase. Relevant for hwext only.
7426 .phase (),
7427
7428 // Shadow register error conditions
7429 .err_update (alert_class_shadowed_14_update_err),
7430 .err_storage (alert_class_shadowed_14_storage_err)
7431 );
7432
7433
7434 // Subregister 15 of Multireg alert_class_shadowed
7435 // R[alert_class_shadowed_15]: V(False)
7436 // Create REGWEN-gated WE signal
7437 logic alert_class_shadowed_15_gated_we;
7438 1/1 assign alert_class_shadowed_15_gated_we = alert_class_shadowed_15_we & alert_regwen_15_qs;
Tests: T1 T2 T3
7439 prim_subreg_shadow #(
7440 .DW (2),
7441 .SwAccess(prim_subreg_pkg::SwAccessRW),
7442 .RESVAL (2'h0),
7443 .Mubi (1'b0)
7444 ) u_alert_class_shadowed_15 (
7445 .clk_i (clk_i),
7446 .rst_ni (rst_ni),
7447 .rst_shadowed_ni (rst_shadowed_ni),
7448
7449 // from register interface
7450 .re (alert_class_shadowed_15_re),
7451 .we (alert_class_shadowed_15_gated_we),
7452 .wd (alert_class_shadowed_15_wd),
7453
7454 // from internal hardware
7455 .de (1'b0),
7456 .d ('0),
7457
7458 // to internal hardware
7459 .qe (),
7460 .q (reg2hw.alert_class_shadowed[15].q),
7461 .ds (),
7462
7463 // to register interface (read)
7464 .qs (alert_class_shadowed_15_qs),
7465
7466 // Shadow register phase. Relevant for hwext only.
7467 .phase (),
7468
7469 // Shadow register error conditions
7470 .err_update (alert_class_shadowed_15_update_err),
7471 .err_storage (alert_class_shadowed_15_storage_err)
7472 );
7473
7474
7475 // Subregister 16 of Multireg alert_class_shadowed
7476 // R[alert_class_shadowed_16]: V(False)
7477 // Create REGWEN-gated WE signal
7478 logic alert_class_shadowed_16_gated_we;
7479 1/1 assign alert_class_shadowed_16_gated_we = alert_class_shadowed_16_we & alert_regwen_16_qs;
Tests: T1 T2 T3
7480 prim_subreg_shadow #(
7481 .DW (2),
7482 .SwAccess(prim_subreg_pkg::SwAccessRW),
7483 .RESVAL (2'h0),
7484 .Mubi (1'b0)
7485 ) u_alert_class_shadowed_16 (
7486 .clk_i (clk_i),
7487 .rst_ni (rst_ni),
7488 .rst_shadowed_ni (rst_shadowed_ni),
7489
7490 // from register interface
7491 .re (alert_class_shadowed_16_re),
7492 .we (alert_class_shadowed_16_gated_we),
7493 .wd (alert_class_shadowed_16_wd),
7494
7495 // from internal hardware
7496 .de (1'b0),
7497 .d ('0),
7498
7499 // to internal hardware
7500 .qe (),
7501 .q (reg2hw.alert_class_shadowed[16].q),
7502 .ds (),
7503
7504 // to register interface (read)
7505 .qs (alert_class_shadowed_16_qs),
7506
7507 // Shadow register phase. Relevant for hwext only.
7508 .phase (),
7509
7510 // Shadow register error conditions
7511 .err_update (alert_class_shadowed_16_update_err),
7512 .err_storage (alert_class_shadowed_16_storage_err)
7513 );
7514
7515
7516 // Subregister 17 of Multireg alert_class_shadowed
7517 // R[alert_class_shadowed_17]: V(False)
7518 // Create REGWEN-gated WE signal
7519 logic alert_class_shadowed_17_gated_we;
7520 1/1 assign alert_class_shadowed_17_gated_we = alert_class_shadowed_17_we & alert_regwen_17_qs;
Tests: T1 T2 T3
7521 prim_subreg_shadow #(
7522 .DW (2),
7523 .SwAccess(prim_subreg_pkg::SwAccessRW),
7524 .RESVAL (2'h0),
7525 .Mubi (1'b0)
7526 ) u_alert_class_shadowed_17 (
7527 .clk_i (clk_i),
7528 .rst_ni (rst_ni),
7529 .rst_shadowed_ni (rst_shadowed_ni),
7530
7531 // from register interface
7532 .re (alert_class_shadowed_17_re),
7533 .we (alert_class_shadowed_17_gated_we),
7534 .wd (alert_class_shadowed_17_wd),
7535
7536 // from internal hardware
7537 .de (1'b0),
7538 .d ('0),
7539
7540 // to internal hardware
7541 .qe (),
7542 .q (reg2hw.alert_class_shadowed[17].q),
7543 .ds (),
7544
7545 // to register interface (read)
7546 .qs (alert_class_shadowed_17_qs),
7547
7548 // Shadow register phase. Relevant for hwext only.
7549 .phase (),
7550
7551 // Shadow register error conditions
7552 .err_update (alert_class_shadowed_17_update_err),
7553 .err_storage (alert_class_shadowed_17_storage_err)
7554 );
7555
7556
7557 // Subregister 18 of Multireg alert_class_shadowed
7558 // R[alert_class_shadowed_18]: V(False)
7559 // Create REGWEN-gated WE signal
7560 logic alert_class_shadowed_18_gated_we;
7561 1/1 assign alert_class_shadowed_18_gated_we = alert_class_shadowed_18_we & alert_regwen_18_qs;
Tests: T1 T2 T3
7562 prim_subreg_shadow #(
7563 .DW (2),
7564 .SwAccess(prim_subreg_pkg::SwAccessRW),
7565 .RESVAL (2'h0),
7566 .Mubi (1'b0)
7567 ) u_alert_class_shadowed_18 (
7568 .clk_i (clk_i),
7569 .rst_ni (rst_ni),
7570 .rst_shadowed_ni (rst_shadowed_ni),
7571
7572 // from register interface
7573 .re (alert_class_shadowed_18_re),
7574 .we (alert_class_shadowed_18_gated_we),
7575 .wd (alert_class_shadowed_18_wd),
7576
7577 // from internal hardware
7578 .de (1'b0),
7579 .d ('0),
7580
7581 // to internal hardware
7582 .qe (),
7583 .q (reg2hw.alert_class_shadowed[18].q),
7584 .ds (),
7585
7586 // to register interface (read)
7587 .qs (alert_class_shadowed_18_qs),
7588
7589 // Shadow register phase. Relevant for hwext only.
7590 .phase (),
7591
7592 // Shadow register error conditions
7593 .err_update (alert_class_shadowed_18_update_err),
7594 .err_storage (alert_class_shadowed_18_storage_err)
7595 );
7596
7597
7598 // Subregister 19 of Multireg alert_class_shadowed
7599 // R[alert_class_shadowed_19]: V(False)
7600 // Create REGWEN-gated WE signal
7601 logic alert_class_shadowed_19_gated_we;
7602 1/1 assign alert_class_shadowed_19_gated_we = alert_class_shadowed_19_we & alert_regwen_19_qs;
Tests: T1 T2 T3
7603 prim_subreg_shadow #(
7604 .DW (2),
7605 .SwAccess(prim_subreg_pkg::SwAccessRW),
7606 .RESVAL (2'h0),
7607 .Mubi (1'b0)
7608 ) u_alert_class_shadowed_19 (
7609 .clk_i (clk_i),
7610 .rst_ni (rst_ni),
7611 .rst_shadowed_ni (rst_shadowed_ni),
7612
7613 // from register interface
7614 .re (alert_class_shadowed_19_re),
7615 .we (alert_class_shadowed_19_gated_we),
7616 .wd (alert_class_shadowed_19_wd),
7617
7618 // from internal hardware
7619 .de (1'b0),
7620 .d ('0),
7621
7622 // to internal hardware
7623 .qe (),
7624 .q (reg2hw.alert_class_shadowed[19].q),
7625 .ds (),
7626
7627 // to register interface (read)
7628 .qs (alert_class_shadowed_19_qs),
7629
7630 // Shadow register phase. Relevant for hwext only.
7631 .phase (),
7632
7633 // Shadow register error conditions
7634 .err_update (alert_class_shadowed_19_update_err),
7635 .err_storage (alert_class_shadowed_19_storage_err)
7636 );
7637
7638
7639 // Subregister 20 of Multireg alert_class_shadowed
7640 // R[alert_class_shadowed_20]: V(False)
7641 // Create REGWEN-gated WE signal
7642 logic alert_class_shadowed_20_gated_we;
7643 1/1 assign alert_class_shadowed_20_gated_we = alert_class_shadowed_20_we & alert_regwen_20_qs;
Tests: T1 T2 T3
7644 prim_subreg_shadow #(
7645 .DW (2),
7646 .SwAccess(prim_subreg_pkg::SwAccessRW),
7647 .RESVAL (2'h0),
7648 .Mubi (1'b0)
7649 ) u_alert_class_shadowed_20 (
7650 .clk_i (clk_i),
7651 .rst_ni (rst_ni),
7652 .rst_shadowed_ni (rst_shadowed_ni),
7653
7654 // from register interface
7655 .re (alert_class_shadowed_20_re),
7656 .we (alert_class_shadowed_20_gated_we),
7657 .wd (alert_class_shadowed_20_wd),
7658
7659 // from internal hardware
7660 .de (1'b0),
7661 .d ('0),
7662
7663 // to internal hardware
7664 .qe (),
7665 .q (reg2hw.alert_class_shadowed[20].q),
7666 .ds (),
7667
7668 // to register interface (read)
7669 .qs (alert_class_shadowed_20_qs),
7670
7671 // Shadow register phase. Relevant for hwext only.
7672 .phase (),
7673
7674 // Shadow register error conditions
7675 .err_update (alert_class_shadowed_20_update_err),
7676 .err_storage (alert_class_shadowed_20_storage_err)
7677 );
7678
7679
7680 // Subregister 21 of Multireg alert_class_shadowed
7681 // R[alert_class_shadowed_21]: V(False)
7682 // Create REGWEN-gated WE signal
7683 logic alert_class_shadowed_21_gated_we;
7684 1/1 assign alert_class_shadowed_21_gated_we = alert_class_shadowed_21_we & alert_regwen_21_qs;
Tests: T1 T2 T3
7685 prim_subreg_shadow #(
7686 .DW (2),
7687 .SwAccess(prim_subreg_pkg::SwAccessRW),
7688 .RESVAL (2'h0),
7689 .Mubi (1'b0)
7690 ) u_alert_class_shadowed_21 (
7691 .clk_i (clk_i),
7692 .rst_ni (rst_ni),
7693 .rst_shadowed_ni (rst_shadowed_ni),
7694
7695 // from register interface
7696 .re (alert_class_shadowed_21_re),
7697 .we (alert_class_shadowed_21_gated_we),
7698 .wd (alert_class_shadowed_21_wd),
7699
7700 // from internal hardware
7701 .de (1'b0),
7702 .d ('0),
7703
7704 // to internal hardware
7705 .qe (),
7706 .q (reg2hw.alert_class_shadowed[21].q),
7707 .ds (),
7708
7709 // to register interface (read)
7710 .qs (alert_class_shadowed_21_qs),
7711
7712 // Shadow register phase. Relevant for hwext only.
7713 .phase (),
7714
7715 // Shadow register error conditions
7716 .err_update (alert_class_shadowed_21_update_err),
7717 .err_storage (alert_class_shadowed_21_storage_err)
7718 );
7719
7720
7721 // Subregister 22 of Multireg alert_class_shadowed
7722 // R[alert_class_shadowed_22]: V(False)
7723 // Create REGWEN-gated WE signal
7724 logic alert_class_shadowed_22_gated_we;
7725 1/1 assign alert_class_shadowed_22_gated_we = alert_class_shadowed_22_we & alert_regwen_22_qs;
Tests: T1 T2 T3
7726 prim_subreg_shadow #(
7727 .DW (2),
7728 .SwAccess(prim_subreg_pkg::SwAccessRW),
7729 .RESVAL (2'h0),
7730 .Mubi (1'b0)
7731 ) u_alert_class_shadowed_22 (
7732 .clk_i (clk_i),
7733 .rst_ni (rst_ni),
7734 .rst_shadowed_ni (rst_shadowed_ni),
7735
7736 // from register interface
7737 .re (alert_class_shadowed_22_re),
7738 .we (alert_class_shadowed_22_gated_we),
7739 .wd (alert_class_shadowed_22_wd),
7740
7741 // from internal hardware
7742 .de (1'b0),
7743 .d ('0),
7744
7745 // to internal hardware
7746 .qe (),
7747 .q (reg2hw.alert_class_shadowed[22].q),
7748 .ds (),
7749
7750 // to register interface (read)
7751 .qs (alert_class_shadowed_22_qs),
7752
7753 // Shadow register phase. Relevant for hwext only.
7754 .phase (),
7755
7756 // Shadow register error conditions
7757 .err_update (alert_class_shadowed_22_update_err),
7758 .err_storage (alert_class_shadowed_22_storage_err)
7759 );
7760
7761
7762 // Subregister 23 of Multireg alert_class_shadowed
7763 // R[alert_class_shadowed_23]: V(False)
7764 // Create REGWEN-gated WE signal
7765 logic alert_class_shadowed_23_gated_we;
7766 1/1 assign alert_class_shadowed_23_gated_we = alert_class_shadowed_23_we & alert_regwen_23_qs;
Tests: T1 T2 T3
7767 prim_subreg_shadow #(
7768 .DW (2),
7769 .SwAccess(prim_subreg_pkg::SwAccessRW),
7770 .RESVAL (2'h0),
7771 .Mubi (1'b0)
7772 ) u_alert_class_shadowed_23 (
7773 .clk_i (clk_i),
7774 .rst_ni (rst_ni),
7775 .rst_shadowed_ni (rst_shadowed_ni),
7776
7777 // from register interface
7778 .re (alert_class_shadowed_23_re),
7779 .we (alert_class_shadowed_23_gated_we),
7780 .wd (alert_class_shadowed_23_wd),
7781
7782 // from internal hardware
7783 .de (1'b0),
7784 .d ('0),
7785
7786 // to internal hardware
7787 .qe (),
7788 .q (reg2hw.alert_class_shadowed[23].q),
7789 .ds (),
7790
7791 // to register interface (read)
7792 .qs (alert_class_shadowed_23_qs),
7793
7794 // Shadow register phase. Relevant for hwext only.
7795 .phase (),
7796
7797 // Shadow register error conditions
7798 .err_update (alert_class_shadowed_23_update_err),
7799 .err_storage (alert_class_shadowed_23_storage_err)
7800 );
7801
7802
7803 // Subregister 24 of Multireg alert_class_shadowed
7804 // R[alert_class_shadowed_24]: V(False)
7805 // Create REGWEN-gated WE signal
7806 logic alert_class_shadowed_24_gated_we;
7807 1/1 assign alert_class_shadowed_24_gated_we = alert_class_shadowed_24_we & alert_regwen_24_qs;
Tests: T1 T2 T3
7808 prim_subreg_shadow #(
7809 .DW (2),
7810 .SwAccess(prim_subreg_pkg::SwAccessRW),
7811 .RESVAL (2'h0),
7812 .Mubi (1'b0)
7813 ) u_alert_class_shadowed_24 (
7814 .clk_i (clk_i),
7815 .rst_ni (rst_ni),
7816 .rst_shadowed_ni (rst_shadowed_ni),
7817
7818 // from register interface
7819 .re (alert_class_shadowed_24_re),
7820 .we (alert_class_shadowed_24_gated_we),
7821 .wd (alert_class_shadowed_24_wd),
7822
7823 // from internal hardware
7824 .de (1'b0),
7825 .d ('0),
7826
7827 // to internal hardware
7828 .qe (),
7829 .q (reg2hw.alert_class_shadowed[24].q),
7830 .ds (),
7831
7832 // to register interface (read)
7833 .qs (alert_class_shadowed_24_qs),
7834
7835 // Shadow register phase. Relevant for hwext only.
7836 .phase (),
7837
7838 // Shadow register error conditions
7839 .err_update (alert_class_shadowed_24_update_err),
7840 .err_storage (alert_class_shadowed_24_storage_err)
7841 );
7842
7843
7844 // Subregister 25 of Multireg alert_class_shadowed
7845 // R[alert_class_shadowed_25]: V(False)
7846 // Create REGWEN-gated WE signal
7847 logic alert_class_shadowed_25_gated_we;
7848 1/1 assign alert_class_shadowed_25_gated_we = alert_class_shadowed_25_we & alert_regwen_25_qs;
Tests: T1 T2 T3
7849 prim_subreg_shadow #(
7850 .DW (2),
7851 .SwAccess(prim_subreg_pkg::SwAccessRW),
7852 .RESVAL (2'h0),
7853 .Mubi (1'b0)
7854 ) u_alert_class_shadowed_25 (
7855 .clk_i (clk_i),
7856 .rst_ni (rst_ni),
7857 .rst_shadowed_ni (rst_shadowed_ni),
7858
7859 // from register interface
7860 .re (alert_class_shadowed_25_re),
7861 .we (alert_class_shadowed_25_gated_we),
7862 .wd (alert_class_shadowed_25_wd),
7863
7864 // from internal hardware
7865 .de (1'b0),
7866 .d ('0),
7867
7868 // to internal hardware
7869 .qe (),
7870 .q (reg2hw.alert_class_shadowed[25].q),
7871 .ds (),
7872
7873 // to register interface (read)
7874 .qs (alert_class_shadowed_25_qs),
7875
7876 // Shadow register phase. Relevant for hwext only.
7877 .phase (),
7878
7879 // Shadow register error conditions
7880 .err_update (alert_class_shadowed_25_update_err),
7881 .err_storage (alert_class_shadowed_25_storage_err)
7882 );
7883
7884
7885 // Subregister 26 of Multireg alert_class_shadowed
7886 // R[alert_class_shadowed_26]: V(False)
7887 // Create REGWEN-gated WE signal
7888 logic alert_class_shadowed_26_gated_we;
7889 1/1 assign alert_class_shadowed_26_gated_we = alert_class_shadowed_26_we & alert_regwen_26_qs;
Tests: T1 T2 T3
7890 prim_subreg_shadow #(
7891 .DW (2),
7892 .SwAccess(prim_subreg_pkg::SwAccessRW),
7893 .RESVAL (2'h0),
7894 .Mubi (1'b0)
7895 ) u_alert_class_shadowed_26 (
7896 .clk_i (clk_i),
7897 .rst_ni (rst_ni),
7898 .rst_shadowed_ni (rst_shadowed_ni),
7899
7900 // from register interface
7901 .re (alert_class_shadowed_26_re),
7902 .we (alert_class_shadowed_26_gated_we),
7903 .wd (alert_class_shadowed_26_wd),
7904
7905 // from internal hardware
7906 .de (1'b0),
7907 .d ('0),
7908
7909 // to internal hardware
7910 .qe (),
7911 .q (reg2hw.alert_class_shadowed[26].q),
7912 .ds (),
7913
7914 // to register interface (read)
7915 .qs (alert_class_shadowed_26_qs),
7916
7917 // Shadow register phase. Relevant for hwext only.
7918 .phase (),
7919
7920 // Shadow register error conditions
7921 .err_update (alert_class_shadowed_26_update_err),
7922 .err_storage (alert_class_shadowed_26_storage_err)
7923 );
7924
7925
7926 // Subregister 27 of Multireg alert_class_shadowed
7927 // R[alert_class_shadowed_27]: V(False)
7928 // Create REGWEN-gated WE signal
7929 logic alert_class_shadowed_27_gated_we;
7930 1/1 assign alert_class_shadowed_27_gated_we = alert_class_shadowed_27_we & alert_regwen_27_qs;
Tests: T1 T2 T3
7931 prim_subreg_shadow #(
7932 .DW (2),
7933 .SwAccess(prim_subreg_pkg::SwAccessRW),
7934 .RESVAL (2'h0),
7935 .Mubi (1'b0)
7936 ) u_alert_class_shadowed_27 (
7937 .clk_i (clk_i),
7938 .rst_ni (rst_ni),
7939 .rst_shadowed_ni (rst_shadowed_ni),
7940
7941 // from register interface
7942 .re (alert_class_shadowed_27_re),
7943 .we (alert_class_shadowed_27_gated_we),
7944 .wd (alert_class_shadowed_27_wd),
7945
7946 // from internal hardware
7947 .de (1'b0),
7948 .d ('0),
7949
7950 // to internal hardware
7951 .qe (),
7952 .q (reg2hw.alert_class_shadowed[27].q),
7953 .ds (),
7954
7955 // to register interface (read)
7956 .qs (alert_class_shadowed_27_qs),
7957
7958 // Shadow register phase. Relevant for hwext only.
7959 .phase (),
7960
7961 // Shadow register error conditions
7962 .err_update (alert_class_shadowed_27_update_err),
7963 .err_storage (alert_class_shadowed_27_storage_err)
7964 );
7965
7966
7967 // Subregister 28 of Multireg alert_class_shadowed
7968 // R[alert_class_shadowed_28]: V(False)
7969 // Create REGWEN-gated WE signal
7970 logic alert_class_shadowed_28_gated_we;
7971 1/1 assign alert_class_shadowed_28_gated_we = alert_class_shadowed_28_we & alert_regwen_28_qs;
Tests: T1 T2 T3
7972 prim_subreg_shadow #(
7973 .DW (2),
7974 .SwAccess(prim_subreg_pkg::SwAccessRW),
7975 .RESVAL (2'h0),
7976 .Mubi (1'b0)
7977 ) u_alert_class_shadowed_28 (
7978 .clk_i (clk_i),
7979 .rst_ni (rst_ni),
7980 .rst_shadowed_ni (rst_shadowed_ni),
7981
7982 // from register interface
7983 .re (alert_class_shadowed_28_re),
7984 .we (alert_class_shadowed_28_gated_we),
7985 .wd (alert_class_shadowed_28_wd),
7986
7987 // from internal hardware
7988 .de (1'b0),
7989 .d ('0),
7990
7991 // to internal hardware
7992 .qe (),
7993 .q (reg2hw.alert_class_shadowed[28].q),
7994 .ds (),
7995
7996 // to register interface (read)
7997 .qs (alert_class_shadowed_28_qs),
7998
7999 // Shadow register phase. Relevant for hwext only.
8000 .phase (),
8001
8002 // Shadow register error conditions
8003 .err_update (alert_class_shadowed_28_update_err),
8004 .err_storage (alert_class_shadowed_28_storage_err)
8005 );
8006
8007
8008 // Subregister 29 of Multireg alert_class_shadowed
8009 // R[alert_class_shadowed_29]: V(False)
8010 // Create REGWEN-gated WE signal
8011 logic alert_class_shadowed_29_gated_we;
8012 1/1 assign alert_class_shadowed_29_gated_we = alert_class_shadowed_29_we & alert_regwen_29_qs;
Tests: T1 T2 T3
8013 prim_subreg_shadow #(
8014 .DW (2),
8015 .SwAccess(prim_subreg_pkg::SwAccessRW),
8016 .RESVAL (2'h0),
8017 .Mubi (1'b0)
8018 ) u_alert_class_shadowed_29 (
8019 .clk_i (clk_i),
8020 .rst_ni (rst_ni),
8021 .rst_shadowed_ni (rst_shadowed_ni),
8022
8023 // from register interface
8024 .re (alert_class_shadowed_29_re),
8025 .we (alert_class_shadowed_29_gated_we),
8026 .wd (alert_class_shadowed_29_wd),
8027
8028 // from internal hardware
8029 .de (1'b0),
8030 .d ('0),
8031
8032 // to internal hardware
8033 .qe (),
8034 .q (reg2hw.alert_class_shadowed[29].q),
8035 .ds (),
8036
8037 // to register interface (read)
8038 .qs (alert_class_shadowed_29_qs),
8039
8040 // Shadow register phase. Relevant for hwext only.
8041 .phase (),
8042
8043 // Shadow register error conditions
8044 .err_update (alert_class_shadowed_29_update_err),
8045 .err_storage (alert_class_shadowed_29_storage_err)
8046 );
8047
8048
8049 // Subregister 30 of Multireg alert_class_shadowed
8050 // R[alert_class_shadowed_30]: V(False)
8051 // Create REGWEN-gated WE signal
8052 logic alert_class_shadowed_30_gated_we;
8053 1/1 assign alert_class_shadowed_30_gated_we = alert_class_shadowed_30_we & alert_regwen_30_qs;
Tests: T1 T2 T3
8054 prim_subreg_shadow #(
8055 .DW (2),
8056 .SwAccess(prim_subreg_pkg::SwAccessRW),
8057 .RESVAL (2'h0),
8058 .Mubi (1'b0)
8059 ) u_alert_class_shadowed_30 (
8060 .clk_i (clk_i),
8061 .rst_ni (rst_ni),
8062 .rst_shadowed_ni (rst_shadowed_ni),
8063
8064 // from register interface
8065 .re (alert_class_shadowed_30_re),
8066 .we (alert_class_shadowed_30_gated_we),
8067 .wd (alert_class_shadowed_30_wd),
8068
8069 // from internal hardware
8070 .de (1'b0),
8071 .d ('0),
8072
8073 // to internal hardware
8074 .qe (),
8075 .q (reg2hw.alert_class_shadowed[30].q),
8076 .ds (),
8077
8078 // to register interface (read)
8079 .qs (alert_class_shadowed_30_qs),
8080
8081 // Shadow register phase. Relevant for hwext only.
8082 .phase (),
8083
8084 // Shadow register error conditions
8085 .err_update (alert_class_shadowed_30_update_err),
8086 .err_storage (alert_class_shadowed_30_storage_err)
8087 );
8088
8089
8090 // Subregister 31 of Multireg alert_class_shadowed
8091 // R[alert_class_shadowed_31]: V(False)
8092 // Create REGWEN-gated WE signal
8093 logic alert_class_shadowed_31_gated_we;
8094 1/1 assign alert_class_shadowed_31_gated_we = alert_class_shadowed_31_we & alert_regwen_31_qs;
Tests: T1 T2 T3
8095 prim_subreg_shadow #(
8096 .DW (2),
8097 .SwAccess(prim_subreg_pkg::SwAccessRW),
8098 .RESVAL (2'h0),
8099 .Mubi (1'b0)
8100 ) u_alert_class_shadowed_31 (
8101 .clk_i (clk_i),
8102 .rst_ni (rst_ni),
8103 .rst_shadowed_ni (rst_shadowed_ni),
8104
8105 // from register interface
8106 .re (alert_class_shadowed_31_re),
8107 .we (alert_class_shadowed_31_gated_we),
8108 .wd (alert_class_shadowed_31_wd),
8109
8110 // from internal hardware
8111 .de (1'b0),
8112 .d ('0),
8113
8114 // to internal hardware
8115 .qe (),
8116 .q (reg2hw.alert_class_shadowed[31].q),
8117 .ds (),
8118
8119 // to register interface (read)
8120 .qs (alert_class_shadowed_31_qs),
8121
8122 // Shadow register phase. Relevant for hwext only.
8123 .phase (),
8124
8125 // Shadow register error conditions
8126 .err_update (alert_class_shadowed_31_update_err),
8127 .err_storage (alert_class_shadowed_31_storage_err)
8128 );
8129
8130
8131 // Subregister 32 of Multireg alert_class_shadowed
8132 // R[alert_class_shadowed_32]: V(False)
8133 // Create REGWEN-gated WE signal
8134 logic alert_class_shadowed_32_gated_we;
8135 1/1 assign alert_class_shadowed_32_gated_we = alert_class_shadowed_32_we & alert_regwen_32_qs;
Tests: T1 T2 T3
8136 prim_subreg_shadow #(
8137 .DW (2),
8138 .SwAccess(prim_subreg_pkg::SwAccessRW),
8139 .RESVAL (2'h0),
8140 .Mubi (1'b0)
8141 ) u_alert_class_shadowed_32 (
8142 .clk_i (clk_i),
8143 .rst_ni (rst_ni),
8144 .rst_shadowed_ni (rst_shadowed_ni),
8145
8146 // from register interface
8147 .re (alert_class_shadowed_32_re),
8148 .we (alert_class_shadowed_32_gated_we),
8149 .wd (alert_class_shadowed_32_wd),
8150
8151 // from internal hardware
8152 .de (1'b0),
8153 .d ('0),
8154
8155 // to internal hardware
8156 .qe (),
8157 .q (reg2hw.alert_class_shadowed[32].q),
8158 .ds (),
8159
8160 // to register interface (read)
8161 .qs (alert_class_shadowed_32_qs),
8162
8163 // Shadow register phase. Relevant for hwext only.
8164 .phase (),
8165
8166 // Shadow register error conditions
8167 .err_update (alert_class_shadowed_32_update_err),
8168 .err_storage (alert_class_shadowed_32_storage_err)
8169 );
8170
8171
8172 // Subregister 33 of Multireg alert_class_shadowed
8173 // R[alert_class_shadowed_33]: V(False)
8174 // Create REGWEN-gated WE signal
8175 logic alert_class_shadowed_33_gated_we;
8176 1/1 assign alert_class_shadowed_33_gated_we = alert_class_shadowed_33_we & alert_regwen_33_qs;
Tests: T1 T2 T3
8177 prim_subreg_shadow #(
8178 .DW (2),
8179 .SwAccess(prim_subreg_pkg::SwAccessRW),
8180 .RESVAL (2'h0),
8181 .Mubi (1'b0)
8182 ) u_alert_class_shadowed_33 (
8183 .clk_i (clk_i),
8184 .rst_ni (rst_ni),
8185 .rst_shadowed_ni (rst_shadowed_ni),
8186
8187 // from register interface
8188 .re (alert_class_shadowed_33_re),
8189 .we (alert_class_shadowed_33_gated_we),
8190 .wd (alert_class_shadowed_33_wd),
8191
8192 // from internal hardware
8193 .de (1'b0),
8194 .d ('0),
8195
8196 // to internal hardware
8197 .qe (),
8198 .q (reg2hw.alert_class_shadowed[33].q),
8199 .ds (),
8200
8201 // to register interface (read)
8202 .qs (alert_class_shadowed_33_qs),
8203
8204 // Shadow register phase. Relevant for hwext only.
8205 .phase (),
8206
8207 // Shadow register error conditions
8208 .err_update (alert_class_shadowed_33_update_err),
8209 .err_storage (alert_class_shadowed_33_storage_err)
8210 );
8211
8212
8213 // Subregister 34 of Multireg alert_class_shadowed
8214 // R[alert_class_shadowed_34]: V(False)
8215 // Create REGWEN-gated WE signal
8216 logic alert_class_shadowed_34_gated_we;
8217 1/1 assign alert_class_shadowed_34_gated_we = alert_class_shadowed_34_we & alert_regwen_34_qs;
Tests: T1 T2 T3
8218 prim_subreg_shadow #(
8219 .DW (2),
8220 .SwAccess(prim_subreg_pkg::SwAccessRW),
8221 .RESVAL (2'h0),
8222 .Mubi (1'b0)
8223 ) u_alert_class_shadowed_34 (
8224 .clk_i (clk_i),
8225 .rst_ni (rst_ni),
8226 .rst_shadowed_ni (rst_shadowed_ni),
8227
8228 // from register interface
8229 .re (alert_class_shadowed_34_re),
8230 .we (alert_class_shadowed_34_gated_we),
8231 .wd (alert_class_shadowed_34_wd),
8232
8233 // from internal hardware
8234 .de (1'b0),
8235 .d ('0),
8236
8237 // to internal hardware
8238 .qe (),
8239 .q (reg2hw.alert_class_shadowed[34].q),
8240 .ds (),
8241
8242 // to register interface (read)
8243 .qs (alert_class_shadowed_34_qs),
8244
8245 // Shadow register phase. Relevant for hwext only.
8246 .phase (),
8247
8248 // Shadow register error conditions
8249 .err_update (alert_class_shadowed_34_update_err),
8250 .err_storage (alert_class_shadowed_34_storage_err)
8251 );
8252
8253
8254 // Subregister 35 of Multireg alert_class_shadowed
8255 // R[alert_class_shadowed_35]: V(False)
8256 // Create REGWEN-gated WE signal
8257 logic alert_class_shadowed_35_gated_we;
8258 1/1 assign alert_class_shadowed_35_gated_we = alert_class_shadowed_35_we & alert_regwen_35_qs;
Tests: T1 T2 T3
8259 prim_subreg_shadow #(
8260 .DW (2),
8261 .SwAccess(prim_subreg_pkg::SwAccessRW),
8262 .RESVAL (2'h0),
8263 .Mubi (1'b0)
8264 ) u_alert_class_shadowed_35 (
8265 .clk_i (clk_i),
8266 .rst_ni (rst_ni),
8267 .rst_shadowed_ni (rst_shadowed_ni),
8268
8269 // from register interface
8270 .re (alert_class_shadowed_35_re),
8271 .we (alert_class_shadowed_35_gated_we),
8272 .wd (alert_class_shadowed_35_wd),
8273
8274 // from internal hardware
8275 .de (1'b0),
8276 .d ('0),
8277
8278 // to internal hardware
8279 .qe (),
8280 .q (reg2hw.alert_class_shadowed[35].q),
8281 .ds (),
8282
8283 // to register interface (read)
8284 .qs (alert_class_shadowed_35_qs),
8285
8286 // Shadow register phase. Relevant for hwext only.
8287 .phase (),
8288
8289 // Shadow register error conditions
8290 .err_update (alert_class_shadowed_35_update_err),
8291 .err_storage (alert_class_shadowed_35_storage_err)
8292 );
8293
8294
8295 // Subregister 36 of Multireg alert_class_shadowed
8296 // R[alert_class_shadowed_36]: V(False)
8297 // Create REGWEN-gated WE signal
8298 logic alert_class_shadowed_36_gated_we;
8299 1/1 assign alert_class_shadowed_36_gated_we = alert_class_shadowed_36_we & alert_regwen_36_qs;
Tests: T1 T2 T3
8300 prim_subreg_shadow #(
8301 .DW (2),
8302 .SwAccess(prim_subreg_pkg::SwAccessRW),
8303 .RESVAL (2'h0),
8304 .Mubi (1'b0)
8305 ) u_alert_class_shadowed_36 (
8306 .clk_i (clk_i),
8307 .rst_ni (rst_ni),
8308 .rst_shadowed_ni (rst_shadowed_ni),
8309
8310 // from register interface
8311 .re (alert_class_shadowed_36_re),
8312 .we (alert_class_shadowed_36_gated_we),
8313 .wd (alert_class_shadowed_36_wd),
8314
8315 // from internal hardware
8316 .de (1'b0),
8317 .d ('0),
8318
8319 // to internal hardware
8320 .qe (),
8321 .q (reg2hw.alert_class_shadowed[36].q),
8322 .ds (),
8323
8324 // to register interface (read)
8325 .qs (alert_class_shadowed_36_qs),
8326
8327 // Shadow register phase. Relevant for hwext only.
8328 .phase (),
8329
8330 // Shadow register error conditions
8331 .err_update (alert_class_shadowed_36_update_err),
8332 .err_storage (alert_class_shadowed_36_storage_err)
8333 );
8334
8335
8336 // Subregister 37 of Multireg alert_class_shadowed
8337 // R[alert_class_shadowed_37]: V(False)
8338 // Create REGWEN-gated WE signal
8339 logic alert_class_shadowed_37_gated_we;
8340 1/1 assign alert_class_shadowed_37_gated_we = alert_class_shadowed_37_we & alert_regwen_37_qs;
Tests: T1 T2 T3
8341 prim_subreg_shadow #(
8342 .DW (2),
8343 .SwAccess(prim_subreg_pkg::SwAccessRW),
8344 .RESVAL (2'h0),
8345 .Mubi (1'b0)
8346 ) u_alert_class_shadowed_37 (
8347 .clk_i (clk_i),
8348 .rst_ni (rst_ni),
8349 .rst_shadowed_ni (rst_shadowed_ni),
8350
8351 // from register interface
8352 .re (alert_class_shadowed_37_re),
8353 .we (alert_class_shadowed_37_gated_we),
8354 .wd (alert_class_shadowed_37_wd),
8355
8356 // from internal hardware
8357 .de (1'b0),
8358 .d ('0),
8359
8360 // to internal hardware
8361 .qe (),
8362 .q (reg2hw.alert_class_shadowed[37].q),
8363 .ds (),
8364
8365 // to register interface (read)
8366 .qs (alert_class_shadowed_37_qs),
8367
8368 // Shadow register phase. Relevant for hwext only.
8369 .phase (),
8370
8371 // Shadow register error conditions
8372 .err_update (alert_class_shadowed_37_update_err),
8373 .err_storage (alert_class_shadowed_37_storage_err)
8374 );
8375
8376
8377 // Subregister 38 of Multireg alert_class_shadowed
8378 // R[alert_class_shadowed_38]: V(False)
8379 // Create REGWEN-gated WE signal
8380 logic alert_class_shadowed_38_gated_we;
8381 1/1 assign alert_class_shadowed_38_gated_we = alert_class_shadowed_38_we & alert_regwen_38_qs;
Tests: T1 T2 T3
8382 prim_subreg_shadow #(
8383 .DW (2),
8384 .SwAccess(prim_subreg_pkg::SwAccessRW),
8385 .RESVAL (2'h0),
8386 .Mubi (1'b0)
8387 ) u_alert_class_shadowed_38 (
8388 .clk_i (clk_i),
8389 .rst_ni (rst_ni),
8390 .rst_shadowed_ni (rst_shadowed_ni),
8391
8392 // from register interface
8393 .re (alert_class_shadowed_38_re),
8394 .we (alert_class_shadowed_38_gated_we),
8395 .wd (alert_class_shadowed_38_wd),
8396
8397 // from internal hardware
8398 .de (1'b0),
8399 .d ('0),
8400
8401 // to internal hardware
8402 .qe (),
8403 .q (reg2hw.alert_class_shadowed[38].q),
8404 .ds (),
8405
8406 // to register interface (read)
8407 .qs (alert_class_shadowed_38_qs),
8408
8409 // Shadow register phase. Relevant for hwext only.
8410 .phase (),
8411
8412 // Shadow register error conditions
8413 .err_update (alert_class_shadowed_38_update_err),
8414 .err_storage (alert_class_shadowed_38_storage_err)
8415 );
8416
8417
8418 // Subregister 39 of Multireg alert_class_shadowed
8419 // R[alert_class_shadowed_39]: V(False)
8420 // Create REGWEN-gated WE signal
8421 logic alert_class_shadowed_39_gated_we;
8422 1/1 assign alert_class_shadowed_39_gated_we = alert_class_shadowed_39_we & alert_regwen_39_qs;
Tests: T1 T2 T3
8423 prim_subreg_shadow #(
8424 .DW (2),
8425 .SwAccess(prim_subreg_pkg::SwAccessRW),
8426 .RESVAL (2'h0),
8427 .Mubi (1'b0)
8428 ) u_alert_class_shadowed_39 (
8429 .clk_i (clk_i),
8430 .rst_ni (rst_ni),
8431 .rst_shadowed_ni (rst_shadowed_ni),
8432
8433 // from register interface
8434 .re (alert_class_shadowed_39_re),
8435 .we (alert_class_shadowed_39_gated_we),
8436 .wd (alert_class_shadowed_39_wd),
8437
8438 // from internal hardware
8439 .de (1'b0),
8440 .d ('0),
8441
8442 // to internal hardware
8443 .qe (),
8444 .q (reg2hw.alert_class_shadowed[39].q),
8445 .ds (),
8446
8447 // to register interface (read)
8448 .qs (alert_class_shadowed_39_qs),
8449
8450 // Shadow register phase. Relevant for hwext only.
8451 .phase (),
8452
8453 // Shadow register error conditions
8454 .err_update (alert_class_shadowed_39_update_err),
8455 .err_storage (alert_class_shadowed_39_storage_err)
8456 );
8457
8458
8459 // Subregister 40 of Multireg alert_class_shadowed
8460 // R[alert_class_shadowed_40]: V(False)
8461 // Create REGWEN-gated WE signal
8462 logic alert_class_shadowed_40_gated_we;
8463 1/1 assign alert_class_shadowed_40_gated_we = alert_class_shadowed_40_we & alert_regwen_40_qs;
Tests: T1 T2 T3
8464 prim_subreg_shadow #(
8465 .DW (2),
8466 .SwAccess(prim_subreg_pkg::SwAccessRW),
8467 .RESVAL (2'h0),
8468 .Mubi (1'b0)
8469 ) u_alert_class_shadowed_40 (
8470 .clk_i (clk_i),
8471 .rst_ni (rst_ni),
8472 .rst_shadowed_ni (rst_shadowed_ni),
8473
8474 // from register interface
8475 .re (alert_class_shadowed_40_re),
8476 .we (alert_class_shadowed_40_gated_we),
8477 .wd (alert_class_shadowed_40_wd),
8478
8479 // from internal hardware
8480 .de (1'b0),
8481 .d ('0),
8482
8483 // to internal hardware
8484 .qe (),
8485 .q (reg2hw.alert_class_shadowed[40].q),
8486 .ds (),
8487
8488 // to register interface (read)
8489 .qs (alert_class_shadowed_40_qs),
8490
8491 // Shadow register phase. Relevant for hwext only.
8492 .phase (),
8493
8494 // Shadow register error conditions
8495 .err_update (alert_class_shadowed_40_update_err),
8496 .err_storage (alert_class_shadowed_40_storage_err)
8497 );
8498
8499
8500 // Subregister 41 of Multireg alert_class_shadowed
8501 // R[alert_class_shadowed_41]: V(False)
8502 // Create REGWEN-gated WE signal
8503 logic alert_class_shadowed_41_gated_we;
8504 1/1 assign alert_class_shadowed_41_gated_we = alert_class_shadowed_41_we & alert_regwen_41_qs;
Tests: T1 T2 T3
8505 prim_subreg_shadow #(
8506 .DW (2),
8507 .SwAccess(prim_subreg_pkg::SwAccessRW),
8508 .RESVAL (2'h0),
8509 .Mubi (1'b0)
8510 ) u_alert_class_shadowed_41 (
8511 .clk_i (clk_i),
8512 .rst_ni (rst_ni),
8513 .rst_shadowed_ni (rst_shadowed_ni),
8514
8515 // from register interface
8516 .re (alert_class_shadowed_41_re),
8517 .we (alert_class_shadowed_41_gated_we),
8518 .wd (alert_class_shadowed_41_wd),
8519
8520 // from internal hardware
8521 .de (1'b0),
8522 .d ('0),
8523
8524 // to internal hardware
8525 .qe (),
8526 .q (reg2hw.alert_class_shadowed[41].q),
8527 .ds (),
8528
8529 // to register interface (read)
8530 .qs (alert_class_shadowed_41_qs),
8531
8532 // Shadow register phase. Relevant for hwext only.
8533 .phase (),
8534
8535 // Shadow register error conditions
8536 .err_update (alert_class_shadowed_41_update_err),
8537 .err_storage (alert_class_shadowed_41_storage_err)
8538 );
8539
8540
8541 // Subregister 42 of Multireg alert_class_shadowed
8542 // R[alert_class_shadowed_42]: V(False)
8543 // Create REGWEN-gated WE signal
8544 logic alert_class_shadowed_42_gated_we;
8545 1/1 assign alert_class_shadowed_42_gated_we = alert_class_shadowed_42_we & alert_regwen_42_qs;
Tests: T1 T2 T3
8546 prim_subreg_shadow #(
8547 .DW (2),
8548 .SwAccess(prim_subreg_pkg::SwAccessRW),
8549 .RESVAL (2'h0),
8550 .Mubi (1'b0)
8551 ) u_alert_class_shadowed_42 (
8552 .clk_i (clk_i),
8553 .rst_ni (rst_ni),
8554 .rst_shadowed_ni (rst_shadowed_ni),
8555
8556 // from register interface
8557 .re (alert_class_shadowed_42_re),
8558 .we (alert_class_shadowed_42_gated_we),
8559 .wd (alert_class_shadowed_42_wd),
8560
8561 // from internal hardware
8562 .de (1'b0),
8563 .d ('0),
8564
8565 // to internal hardware
8566 .qe (),
8567 .q (reg2hw.alert_class_shadowed[42].q),
8568 .ds (),
8569
8570 // to register interface (read)
8571 .qs (alert_class_shadowed_42_qs),
8572
8573 // Shadow register phase. Relevant for hwext only.
8574 .phase (),
8575
8576 // Shadow register error conditions
8577 .err_update (alert_class_shadowed_42_update_err),
8578 .err_storage (alert_class_shadowed_42_storage_err)
8579 );
8580
8581
8582 // Subregister 43 of Multireg alert_class_shadowed
8583 // R[alert_class_shadowed_43]: V(False)
8584 // Create REGWEN-gated WE signal
8585 logic alert_class_shadowed_43_gated_we;
8586 1/1 assign alert_class_shadowed_43_gated_we = alert_class_shadowed_43_we & alert_regwen_43_qs;
Tests: T1 T2 T3
8587 prim_subreg_shadow #(
8588 .DW (2),
8589 .SwAccess(prim_subreg_pkg::SwAccessRW),
8590 .RESVAL (2'h0),
8591 .Mubi (1'b0)
8592 ) u_alert_class_shadowed_43 (
8593 .clk_i (clk_i),
8594 .rst_ni (rst_ni),
8595 .rst_shadowed_ni (rst_shadowed_ni),
8596
8597 // from register interface
8598 .re (alert_class_shadowed_43_re),
8599 .we (alert_class_shadowed_43_gated_we),
8600 .wd (alert_class_shadowed_43_wd),
8601
8602 // from internal hardware
8603 .de (1'b0),
8604 .d ('0),
8605
8606 // to internal hardware
8607 .qe (),
8608 .q (reg2hw.alert_class_shadowed[43].q),
8609 .ds (),
8610
8611 // to register interface (read)
8612 .qs (alert_class_shadowed_43_qs),
8613
8614 // Shadow register phase. Relevant for hwext only.
8615 .phase (),
8616
8617 // Shadow register error conditions
8618 .err_update (alert_class_shadowed_43_update_err),
8619 .err_storage (alert_class_shadowed_43_storage_err)
8620 );
8621
8622
8623 // Subregister 44 of Multireg alert_class_shadowed
8624 // R[alert_class_shadowed_44]: V(False)
8625 // Create REGWEN-gated WE signal
8626 logic alert_class_shadowed_44_gated_we;
8627 1/1 assign alert_class_shadowed_44_gated_we = alert_class_shadowed_44_we & alert_regwen_44_qs;
Tests: T1 T2 T3
8628 prim_subreg_shadow #(
8629 .DW (2),
8630 .SwAccess(prim_subreg_pkg::SwAccessRW),
8631 .RESVAL (2'h0),
8632 .Mubi (1'b0)
8633 ) u_alert_class_shadowed_44 (
8634 .clk_i (clk_i),
8635 .rst_ni (rst_ni),
8636 .rst_shadowed_ni (rst_shadowed_ni),
8637
8638 // from register interface
8639 .re (alert_class_shadowed_44_re),
8640 .we (alert_class_shadowed_44_gated_we),
8641 .wd (alert_class_shadowed_44_wd),
8642
8643 // from internal hardware
8644 .de (1'b0),
8645 .d ('0),
8646
8647 // to internal hardware
8648 .qe (),
8649 .q (reg2hw.alert_class_shadowed[44].q),
8650 .ds (),
8651
8652 // to register interface (read)
8653 .qs (alert_class_shadowed_44_qs),
8654
8655 // Shadow register phase. Relevant for hwext only.
8656 .phase (),
8657
8658 // Shadow register error conditions
8659 .err_update (alert_class_shadowed_44_update_err),
8660 .err_storage (alert_class_shadowed_44_storage_err)
8661 );
8662
8663
8664 // Subregister 45 of Multireg alert_class_shadowed
8665 // R[alert_class_shadowed_45]: V(False)
8666 // Create REGWEN-gated WE signal
8667 logic alert_class_shadowed_45_gated_we;
8668 1/1 assign alert_class_shadowed_45_gated_we = alert_class_shadowed_45_we & alert_regwen_45_qs;
Tests: T1 T2 T3
8669 prim_subreg_shadow #(
8670 .DW (2),
8671 .SwAccess(prim_subreg_pkg::SwAccessRW),
8672 .RESVAL (2'h0),
8673 .Mubi (1'b0)
8674 ) u_alert_class_shadowed_45 (
8675 .clk_i (clk_i),
8676 .rst_ni (rst_ni),
8677 .rst_shadowed_ni (rst_shadowed_ni),
8678
8679 // from register interface
8680 .re (alert_class_shadowed_45_re),
8681 .we (alert_class_shadowed_45_gated_we),
8682 .wd (alert_class_shadowed_45_wd),
8683
8684 // from internal hardware
8685 .de (1'b0),
8686 .d ('0),
8687
8688 // to internal hardware
8689 .qe (),
8690 .q (reg2hw.alert_class_shadowed[45].q),
8691 .ds (),
8692
8693 // to register interface (read)
8694 .qs (alert_class_shadowed_45_qs),
8695
8696 // Shadow register phase. Relevant for hwext only.
8697 .phase (),
8698
8699 // Shadow register error conditions
8700 .err_update (alert_class_shadowed_45_update_err),
8701 .err_storage (alert_class_shadowed_45_storage_err)
8702 );
8703
8704
8705 // Subregister 46 of Multireg alert_class_shadowed
8706 // R[alert_class_shadowed_46]: V(False)
8707 // Create REGWEN-gated WE signal
8708 logic alert_class_shadowed_46_gated_we;
8709 1/1 assign alert_class_shadowed_46_gated_we = alert_class_shadowed_46_we & alert_regwen_46_qs;
Tests: T1 T2 T3
8710 prim_subreg_shadow #(
8711 .DW (2),
8712 .SwAccess(prim_subreg_pkg::SwAccessRW),
8713 .RESVAL (2'h0),
8714 .Mubi (1'b0)
8715 ) u_alert_class_shadowed_46 (
8716 .clk_i (clk_i),
8717 .rst_ni (rst_ni),
8718 .rst_shadowed_ni (rst_shadowed_ni),
8719
8720 // from register interface
8721 .re (alert_class_shadowed_46_re),
8722 .we (alert_class_shadowed_46_gated_we),
8723 .wd (alert_class_shadowed_46_wd),
8724
8725 // from internal hardware
8726 .de (1'b0),
8727 .d ('0),
8728
8729 // to internal hardware
8730 .qe (),
8731 .q (reg2hw.alert_class_shadowed[46].q),
8732 .ds (),
8733
8734 // to register interface (read)
8735 .qs (alert_class_shadowed_46_qs),
8736
8737 // Shadow register phase. Relevant for hwext only.
8738 .phase (),
8739
8740 // Shadow register error conditions
8741 .err_update (alert_class_shadowed_46_update_err),
8742 .err_storage (alert_class_shadowed_46_storage_err)
8743 );
8744
8745
8746 // Subregister 47 of Multireg alert_class_shadowed
8747 // R[alert_class_shadowed_47]: V(False)
8748 // Create REGWEN-gated WE signal
8749 logic alert_class_shadowed_47_gated_we;
8750 1/1 assign alert_class_shadowed_47_gated_we = alert_class_shadowed_47_we & alert_regwen_47_qs;
Tests: T1 T2 T3
8751 prim_subreg_shadow #(
8752 .DW (2),
8753 .SwAccess(prim_subreg_pkg::SwAccessRW),
8754 .RESVAL (2'h0),
8755 .Mubi (1'b0)
8756 ) u_alert_class_shadowed_47 (
8757 .clk_i (clk_i),
8758 .rst_ni (rst_ni),
8759 .rst_shadowed_ni (rst_shadowed_ni),
8760
8761 // from register interface
8762 .re (alert_class_shadowed_47_re),
8763 .we (alert_class_shadowed_47_gated_we),
8764 .wd (alert_class_shadowed_47_wd),
8765
8766 // from internal hardware
8767 .de (1'b0),
8768 .d ('0),
8769
8770 // to internal hardware
8771 .qe (),
8772 .q (reg2hw.alert_class_shadowed[47].q),
8773 .ds (),
8774
8775 // to register interface (read)
8776 .qs (alert_class_shadowed_47_qs),
8777
8778 // Shadow register phase. Relevant for hwext only.
8779 .phase (),
8780
8781 // Shadow register error conditions
8782 .err_update (alert_class_shadowed_47_update_err),
8783 .err_storage (alert_class_shadowed_47_storage_err)
8784 );
8785
8786
8787 // Subregister 48 of Multireg alert_class_shadowed
8788 // R[alert_class_shadowed_48]: V(False)
8789 // Create REGWEN-gated WE signal
8790 logic alert_class_shadowed_48_gated_we;
8791 1/1 assign alert_class_shadowed_48_gated_we = alert_class_shadowed_48_we & alert_regwen_48_qs;
Tests: T1 T2 T3
8792 prim_subreg_shadow #(
8793 .DW (2),
8794 .SwAccess(prim_subreg_pkg::SwAccessRW),
8795 .RESVAL (2'h0),
8796 .Mubi (1'b0)
8797 ) u_alert_class_shadowed_48 (
8798 .clk_i (clk_i),
8799 .rst_ni (rst_ni),
8800 .rst_shadowed_ni (rst_shadowed_ni),
8801
8802 // from register interface
8803 .re (alert_class_shadowed_48_re),
8804 .we (alert_class_shadowed_48_gated_we),
8805 .wd (alert_class_shadowed_48_wd),
8806
8807 // from internal hardware
8808 .de (1'b0),
8809 .d ('0),
8810
8811 // to internal hardware
8812 .qe (),
8813 .q (reg2hw.alert_class_shadowed[48].q),
8814 .ds (),
8815
8816 // to register interface (read)
8817 .qs (alert_class_shadowed_48_qs),
8818
8819 // Shadow register phase. Relevant for hwext only.
8820 .phase (),
8821
8822 // Shadow register error conditions
8823 .err_update (alert_class_shadowed_48_update_err),
8824 .err_storage (alert_class_shadowed_48_storage_err)
8825 );
8826
8827
8828 // Subregister 49 of Multireg alert_class_shadowed
8829 // R[alert_class_shadowed_49]: V(False)
8830 // Create REGWEN-gated WE signal
8831 logic alert_class_shadowed_49_gated_we;
8832 1/1 assign alert_class_shadowed_49_gated_we = alert_class_shadowed_49_we & alert_regwen_49_qs;
Tests: T1 T2 T3
8833 prim_subreg_shadow #(
8834 .DW (2),
8835 .SwAccess(prim_subreg_pkg::SwAccessRW),
8836 .RESVAL (2'h0),
8837 .Mubi (1'b0)
8838 ) u_alert_class_shadowed_49 (
8839 .clk_i (clk_i),
8840 .rst_ni (rst_ni),
8841 .rst_shadowed_ni (rst_shadowed_ni),
8842
8843 // from register interface
8844 .re (alert_class_shadowed_49_re),
8845 .we (alert_class_shadowed_49_gated_we),
8846 .wd (alert_class_shadowed_49_wd),
8847
8848 // from internal hardware
8849 .de (1'b0),
8850 .d ('0),
8851
8852 // to internal hardware
8853 .qe (),
8854 .q (reg2hw.alert_class_shadowed[49].q),
8855 .ds (),
8856
8857 // to register interface (read)
8858 .qs (alert_class_shadowed_49_qs),
8859
8860 // Shadow register phase. Relevant for hwext only.
8861 .phase (),
8862
8863 // Shadow register error conditions
8864 .err_update (alert_class_shadowed_49_update_err),
8865 .err_storage (alert_class_shadowed_49_storage_err)
8866 );
8867
8868
8869 // Subregister 50 of Multireg alert_class_shadowed
8870 // R[alert_class_shadowed_50]: V(False)
8871 // Create REGWEN-gated WE signal
8872 logic alert_class_shadowed_50_gated_we;
8873 1/1 assign alert_class_shadowed_50_gated_we = alert_class_shadowed_50_we & alert_regwen_50_qs;
Tests: T1 T2 T3
8874 prim_subreg_shadow #(
8875 .DW (2),
8876 .SwAccess(prim_subreg_pkg::SwAccessRW),
8877 .RESVAL (2'h0),
8878 .Mubi (1'b0)
8879 ) u_alert_class_shadowed_50 (
8880 .clk_i (clk_i),
8881 .rst_ni (rst_ni),
8882 .rst_shadowed_ni (rst_shadowed_ni),
8883
8884 // from register interface
8885 .re (alert_class_shadowed_50_re),
8886 .we (alert_class_shadowed_50_gated_we),
8887 .wd (alert_class_shadowed_50_wd),
8888
8889 // from internal hardware
8890 .de (1'b0),
8891 .d ('0),
8892
8893 // to internal hardware
8894 .qe (),
8895 .q (reg2hw.alert_class_shadowed[50].q),
8896 .ds (),
8897
8898 // to register interface (read)
8899 .qs (alert_class_shadowed_50_qs),
8900
8901 // Shadow register phase. Relevant for hwext only.
8902 .phase (),
8903
8904 // Shadow register error conditions
8905 .err_update (alert_class_shadowed_50_update_err),
8906 .err_storage (alert_class_shadowed_50_storage_err)
8907 );
8908
8909
8910 // Subregister 51 of Multireg alert_class_shadowed
8911 // R[alert_class_shadowed_51]: V(False)
8912 // Create REGWEN-gated WE signal
8913 logic alert_class_shadowed_51_gated_we;
8914 1/1 assign alert_class_shadowed_51_gated_we = alert_class_shadowed_51_we & alert_regwen_51_qs;
Tests: T1 T2 T3
8915 prim_subreg_shadow #(
8916 .DW (2),
8917 .SwAccess(prim_subreg_pkg::SwAccessRW),
8918 .RESVAL (2'h0),
8919 .Mubi (1'b0)
8920 ) u_alert_class_shadowed_51 (
8921 .clk_i (clk_i),
8922 .rst_ni (rst_ni),
8923 .rst_shadowed_ni (rst_shadowed_ni),
8924
8925 // from register interface
8926 .re (alert_class_shadowed_51_re),
8927 .we (alert_class_shadowed_51_gated_we),
8928 .wd (alert_class_shadowed_51_wd),
8929
8930 // from internal hardware
8931 .de (1'b0),
8932 .d ('0),
8933
8934 // to internal hardware
8935 .qe (),
8936 .q (reg2hw.alert_class_shadowed[51].q),
8937 .ds (),
8938
8939 // to register interface (read)
8940 .qs (alert_class_shadowed_51_qs),
8941
8942 // Shadow register phase. Relevant for hwext only.
8943 .phase (),
8944
8945 // Shadow register error conditions
8946 .err_update (alert_class_shadowed_51_update_err),
8947 .err_storage (alert_class_shadowed_51_storage_err)
8948 );
8949
8950
8951 // Subregister 52 of Multireg alert_class_shadowed
8952 // R[alert_class_shadowed_52]: V(False)
8953 // Create REGWEN-gated WE signal
8954 logic alert_class_shadowed_52_gated_we;
8955 1/1 assign alert_class_shadowed_52_gated_we = alert_class_shadowed_52_we & alert_regwen_52_qs;
Tests: T1 T2 T3
8956 prim_subreg_shadow #(
8957 .DW (2),
8958 .SwAccess(prim_subreg_pkg::SwAccessRW),
8959 .RESVAL (2'h0),
8960 .Mubi (1'b0)
8961 ) u_alert_class_shadowed_52 (
8962 .clk_i (clk_i),
8963 .rst_ni (rst_ni),
8964 .rst_shadowed_ni (rst_shadowed_ni),
8965
8966 // from register interface
8967 .re (alert_class_shadowed_52_re),
8968 .we (alert_class_shadowed_52_gated_we),
8969 .wd (alert_class_shadowed_52_wd),
8970
8971 // from internal hardware
8972 .de (1'b0),
8973 .d ('0),
8974
8975 // to internal hardware
8976 .qe (),
8977 .q (reg2hw.alert_class_shadowed[52].q),
8978 .ds (),
8979
8980 // to register interface (read)
8981 .qs (alert_class_shadowed_52_qs),
8982
8983 // Shadow register phase. Relevant for hwext only.
8984 .phase (),
8985
8986 // Shadow register error conditions
8987 .err_update (alert_class_shadowed_52_update_err),
8988 .err_storage (alert_class_shadowed_52_storage_err)
8989 );
8990
8991
8992 // Subregister 53 of Multireg alert_class_shadowed
8993 // R[alert_class_shadowed_53]: V(False)
8994 // Create REGWEN-gated WE signal
8995 logic alert_class_shadowed_53_gated_we;
8996 1/1 assign alert_class_shadowed_53_gated_we = alert_class_shadowed_53_we & alert_regwen_53_qs;
Tests: T1 T2 T3
8997 prim_subreg_shadow #(
8998 .DW (2),
8999 .SwAccess(prim_subreg_pkg::SwAccessRW),
9000 .RESVAL (2'h0),
9001 .Mubi (1'b0)
9002 ) u_alert_class_shadowed_53 (
9003 .clk_i (clk_i),
9004 .rst_ni (rst_ni),
9005 .rst_shadowed_ni (rst_shadowed_ni),
9006
9007 // from register interface
9008 .re (alert_class_shadowed_53_re),
9009 .we (alert_class_shadowed_53_gated_we),
9010 .wd (alert_class_shadowed_53_wd),
9011
9012 // from internal hardware
9013 .de (1'b0),
9014 .d ('0),
9015
9016 // to internal hardware
9017 .qe (),
9018 .q (reg2hw.alert_class_shadowed[53].q),
9019 .ds (),
9020
9021 // to register interface (read)
9022 .qs (alert_class_shadowed_53_qs),
9023
9024 // Shadow register phase. Relevant for hwext only.
9025 .phase (),
9026
9027 // Shadow register error conditions
9028 .err_update (alert_class_shadowed_53_update_err),
9029 .err_storage (alert_class_shadowed_53_storage_err)
9030 );
9031
9032
9033 // Subregister 54 of Multireg alert_class_shadowed
9034 // R[alert_class_shadowed_54]: V(False)
9035 // Create REGWEN-gated WE signal
9036 logic alert_class_shadowed_54_gated_we;
9037 1/1 assign alert_class_shadowed_54_gated_we = alert_class_shadowed_54_we & alert_regwen_54_qs;
Tests: T1 T2 T3
9038 prim_subreg_shadow #(
9039 .DW (2),
9040 .SwAccess(prim_subreg_pkg::SwAccessRW),
9041 .RESVAL (2'h0),
9042 .Mubi (1'b0)
9043 ) u_alert_class_shadowed_54 (
9044 .clk_i (clk_i),
9045 .rst_ni (rst_ni),
9046 .rst_shadowed_ni (rst_shadowed_ni),
9047
9048 // from register interface
9049 .re (alert_class_shadowed_54_re),
9050 .we (alert_class_shadowed_54_gated_we),
9051 .wd (alert_class_shadowed_54_wd),
9052
9053 // from internal hardware
9054 .de (1'b0),
9055 .d ('0),
9056
9057 // to internal hardware
9058 .qe (),
9059 .q (reg2hw.alert_class_shadowed[54].q),
9060 .ds (),
9061
9062 // to register interface (read)
9063 .qs (alert_class_shadowed_54_qs),
9064
9065 // Shadow register phase. Relevant for hwext only.
9066 .phase (),
9067
9068 // Shadow register error conditions
9069 .err_update (alert_class_shadowed_54_update_err),
9070 .err_storage (alert_class_shadowed_54_storage_err)
9071 );
9072
9073
9074 // Subregister 55 of Multireg alert_class_shadowed
9075 // R[alert_class_shadowed_55]: V(False)
9076 // Create REGWEN-gated WE signal
9077 logic alert_class_shadowed_55_gated_we;
9078 1/1 assign alert_class_shadowed_55_gated_we = alert_class_shadowed_55_we & alert_regwen_55_qs;
Tests: T1 T2 T3
9079 prim_subreg_shadow #(
9080 .DW (2),
9081 .SwAccess(prim_subreg_pkg::SwAccessRW),
9082 .RESVAL (2'h0),
9083 .Mubi (1'b0)
9084 ) u_alert_class_shadowed_55 (
9085 .clk_i (clk_i),
9086 .rst_ni (rst_ni),
9087 .rst_shadowed_ni (rst_shadowed_ni),
9088
9089 // from register interface
9090 .re (alert_class_shadowed_55_re),
9091 .we (alert_class_shadowed_55_gated_we),
9092 .wd (alert_class_shadowed_55_wd),
9093
9094 // from internal hardware
9095 .de (1'b0),
9096 .d ('0),
9097
9098 // to internal hardware
9099 .qe (),
9100 .q (reg2hw.alert_class_shadowed[55].q),
9101 .ds (),
9102
9103 // to register interface (read)
9104 .qs (alert_class_shadowed_55_qs),
9105
9106 // Shadow register phase. Relevant for hwext only.
9107 .phase (),
9108
9109 // Shadow register error conditions
9110 .err_update (alert_class_shadowed_55_update_err),
9111 .err_storage (alert_class_shadowed_55_storage_err)
9112 );
9113
9114
9115 // Subregister 56 of Multireg alert_class_shadowed
9116 // R[alert_class_shadowed_56]: V(False)
9117 // Create REGWEN-gated WE signal
9118 logic alert_class_shadowed_56_gated_we;
9119 1/1 assign alert_class_shadowed_56_gated_we = alert_class_shadowed_56_we & alert_regwen_56_qs;
Tests: T1 T2 T3
9120 prim_subreg_shadow #(
9121 .DW (2),
9122 .SwAccess(prim_subreg_pkg::SwAccessRW),
9123 .RESVAL (2'h0),
9124 .Mubi (1'b0)
9125 ) u_alert_class_shadowed_56 (
9126 .clk_i (clk_i),
9127 .rst_ni (rst_ni),
9128 .rst_shadowed_ni (rst_shadowed_ni),
9129
9130 // from register interface
9131 .re (alert_class_shadowed_56_re),
9132 .we (alert_class_shadowed_56_gated_we),
9133 .wd (alert_class_shadowed_56_wd),
9134
9135 // from internal hardware
9136 .de (1'b0),
9137 .d ('0),
9138
9139 // to internal hardware
9140 .qe (),
9141 .q (reg2hw.alert_class_shadowed[56].q),
9142 .ds (),
9143
9144 // to register interface (read)
9145 .qs (alert_class_shadowed_56_qs),
9146
9147 // Shadow register phase. Relevant for hwext only.
9148 .phase (),
9149
9150 // Shadow register error conditions
9151 .err_update (alert_class_shadowed_56_update_err),
9152 .err_storage (alert_class_shadowed_56_storage_err)
9153 );
9154
9155
9156 // Subregister 57 of Multireg alert_class_shadowed
9157 // R[alert_class_shadowed_57]: V(False)
9158 // Create REGWEN-gated WE signal
9159 logic alert_class_shadowed_57_gated_we;
9160 1/1 assign alert_class_shadowed_57_gated_we = alert_class_shadowed_57_we & alert_regwen_57_qs;
Tests: T1 T2 T3
9161 prim_subreg_shadow #(
9162 .DW (2),
9163 .SwAccess(prim_subreg_pkg::SwAccessRW),
9164 .RESVAL (2'h0),
9165 .Mubi (1'b0)
9166 ) u_alert_class_shadowed_57 (
9167 .clk_i (clk_i),
9168 .rst_ni (rst_ni),
9169 .rst_shadowed_ni (rst_shadowed_ni),
9170
9171 // from register interface
9172 .re (alert_class_shadowed_57_re),
9173 .we (alert_class_shadowed_57_gated_we),
9174 .wd (alert_class_shadowed_57_wd),
9175
9176 // from internal hardware
9177 .de (1'b0),
9178 .d ('0),
9179
9180 // to internal hardware
9181 .qe (),
9182 .q (reg2hw.alert_class_shadowed[57].q),
9183 .ds (),
9184
9185 // to register interface (read)
9186 .qs (alert_class_shadowed_57_qs),
9187
9188 // Shadow register phase. Relevant for hwext only.
9189 .phase (),
9190
9191 // Shadow register error conditions
9192 .err_update (alert_class_shadowed_57_update_err),
9193 .err_storage (alert_class_shadowed_57_storage_err)
9194 );
9195
9196
9197 // Subregister 58 of Multireg alert_class_shadowed
9198 // R[alert_class_shadowed_58]: V(False)
9199 // Create REGWEN-gated WE signal
9200 logic alert_class_shadowed_58_gated_we;
9201 1/1 assign alert_class_shadowed_58_gated_we = alert_class_shadowed_58_we & alert_regwen_58_qs;
Tests: T1 T2 T3
9202 prim_subreg_shadow #(
9203 .DW (2),
9204 .SwAccess(prim_subreg_pkg::SwAccessRW),
9205 .RESVAL (2'h0),
9206 .Mubi (1'b0)
9207 ) u_alert_class_shadowed_58 (
9208 .clk_i (clk_i),
9209 .rst_ni (rst_ni),
9210 .rst_shadowed_ni (rst_shadowed_ni),
9211
9212 // from register interface
9213 .re (alert_class_shadowed_58_re),
9214 .we (alert_class_shadowed_58_gated_we),
9215 .wd (alert_class_shadowed_58_wd),
9216
9217 // from internal hardware
9218 .de (1'b0),
9219 .d ('0),
9220
9221 // to internal hardware
9222 .qe (),
9223 .q (reg2hw.alert_class_shadowed[58].q),
9224 .ds (),
9225
9226 // to register interface (read)
9227 .qs (alert_class_shadowed_58_qs),
9228
9229 // Shadow register phase. Relevant for hwext only.
9230 .phase (),
9231
9232 // Shadow register error conditions
9233 .err_update (alert_class_shadowed_58_update_err),
9234 .err_storage (alert_class_shadowed_58_storage_err)
9235 );
9236
9237
9238 // Subregister 59 of Multireg alert_class_shadowed
9239 // R[alert_class_shadowed_59]: V(False)
9240 // Create REGWEN-gated WE signal
9241 logic alert_class_shadowed_59_gated_we;
9242 1/1 assign alert_class_shadowed_59_gated_we = alert_class_shadowed_59_we & alert_regwen_59_qs;
Tests: T1 T2 T3
9243 prim_subreg_shadow #(
9244 .DW (2),
9245 .SwAccess(prim_subreg_pkg::SwAccessRW),
9246 .RESVAL (2'h0),
9247 .Mubi (1'b0)
9248 ) u_alert_class_shadowed_59 (
9249 .clk_i (clk_i),
9250 .rst_ni (rst_ni),
9251 .rst_shadowed_ni (rst_shadowed_ni),
9252
9253 // from register interface
9254 .re (alert_class_shadowed_59_re),
9255 .we (alert_class_shadowed_59_gated_we),
9256 .wd (alert_class_shadowed_59_wd),
9257
9258 // from internal hardware
9259 .de (1'b0),
9260 .d ('0),
9261
9262 // to internal hardware
9263 .qe (),
9264 .q (reg2hw.alert_class_shadowed[59].q),
9265 .ds (),
9266
9267 // to register interface (read)
9268 .qs (alert_class_shadowed_59_qs),
9269
9270 // Shadow register phase. Relevant for hwext only.
9271 .phase (),
9272
9273 // Shadow register error conditions
9274 .err_update (alert_class_shadowed_59_update_err),
9275 .err_storage (alert_class_shadowed_59_storage_err)
9276 );
9277
9278
9279 // Subregister 60 of Multireg alert_class_shadowed
9280 // R[alert_class_shadowed_60]: V(False)
9281 // Create REGWEN-gated WE signal
9282 logic alert_class_shadowed_60_gated_we;
9283 1/1 assign alert_class_shadowed_60_gated_we = alert_class_shadowed_60_we & alert_regwen_60_qs;
Tests: T1 T2 T3
9284 prim_subreg_shadow #(
9285 .DW (2),
9286 .SwAccess(prim_subreg_pkg::SwAccessRW),
9287 .RESVAL (2'h0),
9288 .Mubi (1'b0)
9289 ) u_alert_class_shadowed_60 (
9290 .clk_i (clk_i),
9291 .rst_ni (rst_ni),
9292 .rst_shadowed_ni (rst_shadowed_ni),
9293
9294 // from register interface
9295 .re (alert_class_shadowed_60_re),
9296 .we (alert_class_shadowed_60_gated_we),
9297 .wd (alert_class_shadowed_60_wd),
9298
9299 // from internal hardware
9300 .de (1'b0),
9301 .d ('0),
9302
9303 // to internal hardware
9304 .qe (),
9305 .q (reg2hw.alert_class_shadowed[60].q),
9306 .ds (),
9307
9308 // to register interface (read)
9309 .qs (alert_class_shadowed_60_qs),
9310
9311 // Shadow register phase. Relevant for hwext only.
9312 .phase (),
9313
9314 // Shadow register error conditions
9315 .err_update (alert_class_shadowed_60_update_err),
9316 .err_storage (alert_class_shadowed_60_storage_err)
9317 );
9318
9319
9320 // Subregister 61 of Multireg alert_class_shadowed
9321 // R[alert_class_shadowed_61]: V(False)
9322 // Create REGWEN-gated WE signal
9323 logic alert_class_shadowed_61_gated_we;
9324 1/1 assign alert_class_shadowed_61_gated_we = alert_class_shadowed_61_we & alert_regwen_61_qs;
Tests: T1 T2 T3
9325 prim_subreg_shadow #(
9326 .DW (2),
9327 .SwAccess(prim_subreg_pkg::SwAccessRW),
9328 .RESVAL (2'h0),
9329 .Mubi (1'b0)
9330 ) u_alert_class_shadowed_61 (
9331 .clk_i (clk_i),
9332 .rst_ni (rst_ni),
9333 .rst_shadowed_ni (rst_shadowed_ni),
9334
9335 // from register interface
9336 .re (alert_class_shadowed_61_re),
9337 .we (alert_class_shadowed_61_gated_we),
9338 .wd (alert_class_shadowed_61_wd),
9339
9340 // from internal hardware
9341 .de (1'b0),
9342 .d ('0),
9343
9344 // to internal hardware
9345 .qe (),
9346 .q (reg2hw.alert_class_shadowed[61].q),
9347 .ds (),
9348
9349 // to register interface (read)
9350 .qs (alert_class_shadowed_61_qs),
9351
9352 // Shadow register phase. Relevant for hwext only.
9353 .phase (),
9354
9355 // Shadow register error conditions
9356 .err_update (alert_class_shadowed_61_update_err),
9357 .err_storage (alert_class_shadowed_61_storage_err)
9358 );
9359
9360
9361 // Subregister 62 of Multireg alert_class_shadowed
9362 // R[alert_class_shadowed_62]: V(False)
9363 // Create REGWEN-gated WE signal
9364 logic alert_class_shadowed_62_gated_we;
9365 1/1 assign alert_class_shadowed_62_gated_we = alert_class_shadowed_62_we & alert_regwen_62_qs;
Tests: T1 T2 T3
9366 prim_subreg_shadow #(
9367 .DW (2),
9368 .SwAccess(prim_subreg_pkg::SwAccessRW),
9369 .RESVAL (2'h0),
9370 .Mubi (1'b0)
9371 ) u_alert_class_shadowed_62 (
9372 .clk_i (clk_i),
9373 .rst_ni (rst_ni),
9374 .rst_shadowed_ni (rst_shadowed_ni),
9375
9376 // from register interface
9377 .re (alert_class_shadowed_62_re),
9378 .we (alert_class_shadowed_62_gated_we),
9379 .wd (alert_class_shadowed_62_wd),
9380
9381 // from internal hardware
9382 .de (1'b0),
9383 .d ('0),
9384
9385 // to internal hardware
9386 .qe (),
9387 .q (reg2hw.alert_class_shadowed[62].q),
9388 .ds (),
9389
9390 // to register interface (read)
9391 .qs (alert_class_shadowed_62_qs),
9392
9393 // Shadow register phase. Relevant for hwext only.
9394 .phase (),
9395
9396 // Shadow register error conditions
9397 .err_update (alert_class_shadowed_62_update_err),
9398 .err_storage (alert_class_shadowed_62_storage_err)
9399 );
9400
9401
9402 // Subregister 63 of Multireg alert_class_shadowed
9403 // R[alert_class_shadowed_63]: V(False)
9404 // Create REGWEN-gated WE signal
9405 logic alert_class_shadowed_63_gated_we;
9406 1/1 assign alert_class_shadowed_63_gated_we = alert_class_shadowed_63_we & alert_regwen_63_qs;
Tests: T1 T2 T3
9407 prim_subreg_shadow #(
9408 .DW (2),
9409 .SwAccess(prim_subreg_pkg::SwAccessRW),
9410 .RESVAL (2'h0),
9411 .Mubi (1'b0)
9412 ) u_alert_class_shadowed_63 (
9413 .clk_i (clk_i),
9414 .rst_ni (rst_ni),
9415 .rst_shadowed_ni (rst_shadowed_ni),
9416
9417 // from register interface
9418 .re (alert_class_shadowed_63_re),
9419 .we (alert_class_shadowed_63_gated_we),
9420 .wd (alert_class_shadowed_63_wd),
9421
9422 // from internal hardware
9423 .de (1'b0),
9424 .d ('0),
9425
9426 // to internal hardware
9427 .qe (),
9428 .q (reg2hw.alert_class_shadowed[63].q),
9429 .ds (),
9430
9431 // to register interface (read)
9432 .qs (alert_class_shadowed_63_qs),
9433
9434 // Shadow register phase. Relevant for hwext only.
9435 .phase (),
9436
9437 // Shadow register error conditions
9438 .err_update (alert_class_shadowed_63_update_err),
9439 .err_storage (alert_class_shadowed_63_storage_err)
9440 );
9441
9442
9443 // Subregister 64 of Multireg alert_class_shadowed
9444 // R[alert_class_shadowed_64]: V(False)
9445 // Create REGWEN-gated WE signal
9446 logic alert_class_shadowed_64_gated_we;
9447 1/1 assign alert_class_shadowed_64_gated_we = alert_class_shadowed_64_we & alert_regwen_64_qs;
Tests: T1 T2 T3
9448 prim_subreg_shadow #(
9449 .DW (2),
9450 .SwAccess(prim_subreg_pkg::SwAccessRW),
9451 .RESVAL (2'h0),
9452 .Mubi (1'b0)
9453 ) u_alert_class_shadowed_64 (
9454 .clk_i (clk_i),
9455 .rst_ni (rst_ni),
9456 .rst_shadowed_ni (rst_shadowed_ni),
9457
9458 // from register interface
9459 .re (alert_class_shadowed_64_re),
9460 .we (alert_class_shadowed_64_gated_we),
9461 .wd (alert_class_shadowed_64_wd),
9462
9463 // from internal hardware
9464 .de (1'b0),
9465 .d ('0),
9466
9467 // to internal hardware
9468 .qe (),
9469 .q (reg2hw.alert_class_shadowed[64].q),
9470 .ds (),
9471
9472 // to register interface (read)
9473 .qs (alert_class_shadowed_64_qs),
9474
9475 // Shadow register phase. Relevant for hwext only.
9476 .phase (),
9477
9478 // Shadow register error conditions
9479 .err_update (alert_class_shadowed_64_update_err),
9480 .err_storage (alert_class_shadowed_64_storage_err)
9481 );
9482
9483
9484 // Subregister 0 of Multireg alert_cause
9485 // R[alert_cause_0]: V(False)
9486 prim_subreg #(
9487 .DW (1),
9488 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9489 .RESVAL (1'h0),
9490 .Mubi (1'b0)
9491 ) u_alert_cause_0 (
9492 .clk_i (clk_i),
9493 .rst_ni (rst_ni),
9494
9495 // from register interface
9496 .we (alert_cause_0_we),
9497 .wd (alert_cause_0_wd),
9498
9499 // from internal hardware
9500 .de (hw2reg.alert_cause[0].de),
9501 .d (hw2reg.alert_cause[0].d),
9502
9503 // to internal hardware
9504 .qe (),
9505 .q (reg2hw.alert_cause[0].q),
9506 .ds (),
9507
9508 // to register interface (read)
9509 .qs (alert_cause_0_qs)
9510 );
9511
9512
9513 // Subregister 1 of Multireg alert_cause
9514 // R[alert_cause_1]: V(False)
9515 prim_subreg #(
9516 .DW (1),
9517 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9518 .RESVAL (1'h0),
9519 .Mubi (1'b0)
9520 ) u_alert_cause_1 (
9521 .clk_i (clk_i),
9522 .rst_ni (rst_ni),
9523
9524 // from register interface
9525 .we (alert_cause_1_we),
9526 .wd (alert_cause_1_wd),
9527
9528 // from internal hardware
9529 .de (hw2reg.alert_cause[1].de),
9530 .d (hw2reg.alert_cause[1].d),
9531
9532 // to internal hardware
9533 .qe (),
9534 .q (reg2hw.alert_cause[1].q),
9535 .ds (),
9536
9537 // to register interface (read)
9538 .qs (alert_cause_1_qs)
9539 );
9540
9541
9542 // Subregister 2 of Multireg alert_cause
9543 // R[alert_cause_2]: V(False)
9544 prim_subreg #(
9545 .DW (1),
9546 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9547 .RESVAL (1'h0),
9548 .Mubi (1'b0)
9549 ) u_alert_cause_2 (
9550 .clk_i (clk_i),
9551 .rst_ni (rst_ni),
9552
9553 // from register interface
9554 .we (alert_cause_2_we),
9555 .wd (alert_cause_2_wd),
9556
9557 // from internal hardware
9558 .de (hw2reg.alert_cause[2].de),
9559 .d (hw2reg.alert_cause[2].d),
9560
9561 // to internal hardware
9562 .qe (),
9563 .q (reg2hw.alert_cause[2].q),
9564 .ds (),
9565
9566 // to register interface (read)
9567 .qs (alert_cause_2_qs)
9568 );
9569
9570
9571 // Subregister 3 of Multireg alert_cause
9572 // R[alert_cause_3]: V(False)
9573 prim_subreg #(
9574 .DW (1),
9575 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9576 .RESVAL (1'h0),
9577 .Mubi (1'b0)
9578 ) u_alert_cause_3 (
9579 .clk_i (clk_i),
9580 .rst_ni (rst_ni),
9581
9582 // from register interface
9583 .we (alert_cause_3_we),
9584 .wd (alert_cause_3_wd),
9585
9586 // from internal hardware
9587 .de (hw2reg.alert_cause[3].de),
9588 .d (hw2reg.alert_cause[3].d),
9589
9590 // to internal hardware
9591 .qe (),
9592 .q (reg2hw.alert_cause[3].q),
9593 .ds (),
9594
9595 // to register interface (read)
9596 .qs (alert_cause_3_qs)
9597 );
9598
9599
9600 // Subregister 4 of Multireg alert_cause
9601 // R[alert_cause_4]: V(False)
9602 prim_subreg #(
9603 .DW (1),
9604 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9605 .RESVAL (1'h0),
9606 .Mubi (1'b0)
9607 ) u_alert_cause_4 (
9608 .clk_i (clk_i),
9609 .rst_ni (rst_ni),
9610
9611 // from register interface
9612 .we (alert_cause_4_we),
9613 .wd (alert_cause_4_wd),
9614
9615 // from internal hardware
9616 .de (hw2reg.alert_cause[4].de),
9617 .d (hw2reg.alert_cause[4].d),
9618
9619 // to internal hardware
9620 .qe (),
9621 .q (reg2hw.alert_cause[4].q),
9622 .ds (),
9623
9624 // to register interface (read)
9625 .qs (alert_cause_4_qs)
9626 );
9627
9628
9629 // Subregister 5 of Multireg alert_cause
9630 // R[alert_cause_5]: V(False)
9631 prim_subreg #(
9632 .DW (1),
9633 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9634 .RESVAL (1'h0),
9635 .Mubi (1'b0)
9636 ) u_alert_cause_5 (
9637 .clk_i (clk_i),
9638 .rst_ni (rst_ni),
9639
9640 // from register interface
9641 .we (alert_cause_5_we),
9642 .wd (alert_cause_5_wd),
9643
9644 // from internal hardware
9645 .de (hw2reg.alert_cause[5].de),
9646 .d (hw2reg.alert_cause[5].d),
9647
9648 // to internal hardware
9649 .qe (),
9650 .q (reg2hw.alert_cause[5].q),
9651 .ds (),
9652
9653 // to register interface (read)
9654 .qs (alert_cause_5_qs)
9655 );
9656
9657
9658 // Subregister 6 of Multireg alert_cause
9659 // R[alert_cause_6]: V(False)
9660 prim_subreg #(
9661 .DW (1),
9662 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9663 .RESVAL (1'h0),
9664 .Mubi (1'b0)
9665 ) u_alert_cause_6 (
9666 .clk_i (clk_i),
9667 .rst_ni (rst_ni),
9668
9669 // from register interface
9670 .we (alert_cause_6_we),
9671 .wd (alert_cause_6_wd),
9672
9673 // from internal hardware
9674 .de (hw2reg.alert_cause[6].de),
9675 .d (hw2reg.alert_cause[6].d),
9676
9677 // to internal hardware
9678 .qe (),
9679 .q (reg2hw.alert_cause[6].q),
9680 .ds (),
9681
9682 // to register interface (read)
9683 .qs (alert_cause_6_qs)
9684 );
9685
9686
9687 // Subregister 7 of Multireg alert_cause
9688 // R[alert_cause_7]: V(False)
9689 prim_subreg #(
9690 .DW (1),
9691 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9692 .RESVAL (1'h0),
9693 .Mubi (1'b0)
9694 ) u_alert_cause_7 (
9695 .clk_i (clk_i),
9696 .rst_ni (rst_ni),
9697
9698 // from register interface
9699 .we (alert_cause_7_we),
9700 .wd (alert_cause_7_wd),
9701
9702 // from internal hardware
9703 .de (hw2reg.alert_cause[7].de),
9704 .d (hw2reg.alert_cause[7].d),
9705
9706 // to internal hardware
9707 .qe (),
9708 .q (reg2hw.alert_cause[7].q),
9709 .ds (),
9710
9711 // to register interface (read)
9712 .qs (alert_cause_7_qs)
9713 );
9714
9715
9716 // Subregister 8 of Multireg alert_cause
9717 // R[alert_cause_8]: V(False)
9718 prim_subreg #(
9719 .DW (1),
9720 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9721 .RESVAL (1'h0),
9722 .Mubi (1'b0)
9723 ) u_alert_cause_8 (
9724 .clk_i (clk_i),
9725 .rst_ni (rst_ni),
9726
9727 // from register interface
9728 .we (alert_cause_8_we),
9729 .wd (alert_cause_8_wd),
9730
9731 // from internal hardware
9732 .de (hw2reg.alert_cause[8].de),
9733 .d (hw2reg.alert_cause[8].d),
9734
9735 // to internal hardware
9736 .qe (),
9737 .q (reg2hw.alert_cause[8].q),
9738 .ds (),
9739
9740 // to register interface (read)
9741 .qs (alert_cause_8_qs)
9742 );
9743
9744
9745 // Subregister 9 of Multireg alert_cause
9746 // R[alert_cause_9]: V(False)
9747 prim_subreg #(
9748 .DW (1),
9749 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9750 .RESVAL (1'h0),
9751 .Mubi (1'b0)
9752 ) u_alert_cause_9 (
9753 .clk_i (clk_i),
9754 .rst_ni (rst_ni),
9755
9756 // from register interface
9757 .we (alert_cause_9_we),
9758 .wd (alert_cause_9_wd),
9759
9760 // from internal hardware
9761 .de (hw2reg.alert_cause[9].de),
9762 .d (hw2reg.alert_cause[9].d),
9763
9764 // to internal hardware
9765 .qe (),
9766 .q (reg2hw.alert_cause[9].q),
9767 .ds (),
9768
9769 // to register interface (read)
9770 .qs (alert_cause_9_qs)
9771 );
9772
9773
9774 // Subregister 10 of Multireg alert_cause
9775 // R[alert_cause_10]: V(False)
9776 prim_subreg #(
9777 .DW (1),
9778 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9779 .RESVAL (1'h0),
9780 .Mubi (1'b0)
9781 ) u_alert_cause_10 (
9782 .clk_i (clk_i),
9783 .rst_ni (rst_ni),
9784
9785 // from register interface
9786 .we (alert_cause_10_we),
9787 .wd (alert_cause_10_wd),
9788
9789 // from internal hardware
9790 .de (hw2reg.alert_cause[10].de),
9791 .d (hw2reg.alert_cause[10].d),
9792
9793 // to internal hardware
9794 .qe (),
9795 .q (reg2hw.alert_cause[10].q),
9796 .ds (),
9797
9798 // to register interface (read)
9799 .qs (alert_cause_10_qs)
9800 );
9801
9802
9803 // Subregister 11 of Multireg alert_cause
9804 // R[alert_cause_11]: V(False)
9805 prim_subreg #(
9806 .DW (1),
9807 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9808 .RESVAL (1'h0),
9809 .Mubi (1'b0)
9810 ) u_alert_cause_11 (
9811 .clk_i (clk_i),
9812 .rst_ni (rst_ni),
9813
9814 // from register interface
9815 .we (alert_cause_11_we),
9816 .wd (alert_cause_11_wd),
9817
9818 // from internal hardware
9819 .de (hw2reg.alert_cause[11].de),
9820 .d (hw2reg.alert_cause[11].d),
9821
9822 // to internal hardware
9823 .qe (),
9824 .q (reg2hw.alert_cause[11].q),
9825 .ds (),
9826
9827 // to register interface (read)
9828 .qs (alert_cause_11_qs)
9829 );
9830
9831
9832 // Subregister 12 of Multireg alert_cause
9833 // R[alert_cause_12]: V(False)
9834 prim_subreg #(
9835 .DW (1),
9836 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9837 .RESVAL (1'h0),
9838 .Mubi (1'b0)
9839 ) u_alert_cause_12 (
9840 .clk_i (clk_i),
9841 .rst_ni (rst_ni),
9842
9843 // from register interface
9844 .we (alert_cause_12_we),
9845 .wd (alert_cause_12_wd),
9846
9847 // from internal hardware
9848 .de (hw2reg.alert_cause[12].de),
9849 .d (hw2reg.alert_cause[12].d),
9850
9851 // to internal hardware
9852 .qe (),
9853 .q (reg2hw.alert_cause[12].q),
9854 .ds (),
9855
9856 // to register interface (read)
9857 .qs (alert_cause_12_qs)
9858 );
9859
9860
9861 // Subregister 13 of Multireg alert_cause
9862 // R[alert_cause_13]: V(False)
9863 prim_subreg #(
9864 .DW (1),
9865 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9866 .RESVAL (1'h0),
9867 .Mubi (1'b0)
9868 ) u_alert_cause_13 (
9869 .clk_i (clk_i),
9870 .rst_ni (rst_ni),
9871
9872 // from register interface
9873 .we (alert_cause_13_we),
9874 .wd (alert_cause_13_wd),
9875
9876 // from internal hardware
9877 .de (hw2reg.alert_cause[13].de),
9878 .d (hw2reg.alert_cause[13].d),
9879
9880 // to internal hardware
9881 .qe (),
9882 .q (reg2hw.alert_cause[13].q),
9883 .ds (),
9884
9885 // to register interface (read)
9886 .qs (alert_cause_13_qs)
9887 );
9888
9889
9890 // Subregister 14 of Multireg alert_cause
9891 // R[alert_cause_14]: V(False)
9892 prim_subreg #(
9893 .DW (1),
9894 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9895 .RESVAL (1'h0),
9896 .Mubi (1'b0)
9897 ) u_alert_cause_14 (
9898 .clk_i (clk_i),
9899 .rst_ni (rst_ni),
9900
9901 // from register interface
9902 .we (alert_cause_14_we),
9903 .wd (alert_cause_14_wd),
9904
9905 // from internal hardware
9906 .de (hw2reg.alert_cause[14].de),
9907 .d (hw2reg.alert_cause[14].d),
9908
9909 // to internal hardware
9910 .qe (),
9911 .q (reg2hw.alert_cause[14].q),
9912 .ds (),
9913
9914 // to register interface (read)
9915 .qs (alert_cause_14_qs)
9916 );
9917
9918
9919 // Subregister 15 of Multireg alert_cause
9920 // R[alert_cause_15]: V(False)
9921 prim_subreg #(
9922 .DW (1),
9923 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9924 .RESVAL (1'h0),
9925 .Mubi (1'b0)
9926 ) u_alert_cause_15 (
9927 .clk_i (clk_i),
9928 .rst_ni (rst_ni),
9929
9930 // from register interface
9931 .we (alert_cause_15_we),
9932 .wd (alert_cause_15_wd),
9933
9934 // from internal hardware
9935 .de (hw2reg.alert_cause[15].de),
9936 .d (hw2reg.alert_cause[15].d),
9937
9938 // to internal hardware
9939 .qe (),
9940 .q (reg2hw.alert_cause[15].q),
9941 .ds (),
9942
9943 // to register interface (read)
9944 .qs (alert_cause_15_qs)
9945 );
9946
9947
9948 // Subregister 16 of Multireg alert_cause
9949 // R[alert_cause_16]: V(False)
9950 prim_subreg #(
9951 .DW (1),
9952 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9953 .RESVAL (1'h0),
9954 .Mubi (1'b0)
9955 ) u_alert_cause_16 (
9956 .clk_i (clk_i),
9957 .rst_ni (rst_ni),
9958
9959 // from register interface
9960 .we (alert_cause_16_we),
9961 .wd (alert_cause_16_wd),
9962
9963 // from internal hardware
9964 .de (hw2reg.alert_cause[16].de),
9965 .d (hw2reg.alert_cause[16].d),
9966
9967 // to internal hardware
9968 .qe (),
9969 .q (reg2hw.alert_cause[16].q),
9970 .ds (),
9971
9972 // to register interface (read)
9973 .qs (alert_cause_16_qs)
9974 );
9975
9976
9977 // Subregister 17 of Multireg alert_cause
9978 // R[alert_cause_17]: V(False)
9979 prim_subreg #(
9980 .DW (1),
9981 .SwAccess(prim_subreg_pkg::SwAccessW1C),
9982 .RESVAL (1'h0),
9983 .Mubi (1'b0)
9984 ) u_alert_cause_17 (
9985 .clk_i (clk_i),
9986 .rst_ni (rst_ni),
9987
9988 // from register interface
9989 .we (alert_cause_17_we),
9990 .wd (alert_cause_17_wd),
9991
9992 // from internal hardware
9993 .de (hw2reg.alert_cause[17].de),
9994 .d (hw2reg.alert_cause[17].d),
9995
9996 // to internal hardware
9997 .qe (),
9998 .q (reg2hw.alert_cause[17].q),
9999 .ds (),
10000
10001 // to register interface (read)
10002 .qs (alert_cause_17_qs)
10003 );
10004
10005
10006 // Subregister 18 of Multireg alert_cause
10007 // R[alert_cause_18]: V(False)
10008 prim_subreg #(
10009 .DW (1),
10010 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10011 .RESVAL (1'h0),
10012 .Mubi (1'b0)
10013 ) u_alert_cause_18 (
10014 .clk_i (clk_i),
10015 .rst_ni (rst_ni),
10016
10017 // from register interface
10018 .we (alert_cause_18_we),
10019 .wd (alert_cause_18_wd),
10020
10021 // from internal hardware
10022 .de (hw2reg.alert_cause[18].de),
10023 .d (hw2reg.alert_cause[18].d),
10024
10025 // to internal hardware
10026 .qe (),
10027 .q (reg2hw.alert_cause[18].q),
10028 .ds (),
10029
10030 // to register interface (read)
10031 .qs (alert_cause_18_qs)
10032 );
10033
10034
10035 // Subregister 19 of Multireg alert_cause
10036 // R[alert_cause_19]: V(False)
10037 prim_subreg #(
10038 .DW (1),
10039 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10040 .RESVAL (1'h0),
10041 .Mubi (1'b0)
10042 ) u_alert_cause_19 (
10043 .clk_i (clk_i),
10044 .rst_ni (rst_ni),
10045
10046 // from register interface
10047 .we (alert_cause_19_we),
10048 .wd (alert_cause_19_wd),
10049
10050 // from internal hardware
10051 .de (hw2reg.alert_cause[19].de),
10052 .d (hw2reg.alert_cause[19].d),
10053
10054 // to internal hardware
10055 .qe (),
10056 .q (reg2hw.alert_cause[19].q),
10057 .ds (),
10058
10059 // to register interface (read)
10060 .qs (alert_cause_19_qs)
10061 );
10062
10063
10064 // Subregister 20 of Multireg alert_cause
10065 // R[alert_cause_20]: V(False)
10066 prim_subreg #(
10067 .DW (1),
10068 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10069 .RESVAL (1'h0),
10070 .Mubi (1'b0)
10071 ) u_alert_cause_20 (
10072 .clk_i (clk_i),
10073 .rst_ni (rst_ni),
10074
10075 // from register interface
10076 .we (alert_cause_20_we),
10077 .wd (alert_cause_20_wd),
10078
10079 // from internal hardware
10080 .de (hw2reg.alert_cause[20].de),
10081 .d (hw2reg.alert_cause[20].d),
10082
10083 // to internal hardware
10084 .qe (),
10085 .q (reg2hw.alert_cause[20].q),
10086 .ds (),
10087
10088 // to register interface (read)
10089 .qs (alert_cause_20_qs)
10090 );
10091
10092
10093 // Subregister 21 of Multireg alert_cause
10094 // R[alert_cause_21]: V(False)
10095 prim_subreg #(
10096 .DW (1),
10097 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10098 .RESVAL (1'h0),
10099 .Mubi (1'b0)
10100 ) u_alert_cause_21 (
10101 .clk_i (clk_i),
10102 .rst_ni (rst_ni),
10103
10104 // from register interface
10105 .we (alert_cause_21_we),
10106 .wd (alert_cause_21_wd),
10107
10108 // from internal hardware
10109 .de (hw2reg.alert_cause[21].de),
10110 .d (hw2reg.alert_cause[21].d),
10111
10112 // to internal hardware
10113 .qe (),
10114 .q (reg2hw.alert_cause[21].q),
10115 .ds (),
10116
10117 // to register interface (read)
10118 .qs (alert_cause_21_qs)
10119 );
10120
10121
10122 // Subregister 22 of Multireg alert_cause
10123 // R[alert_cause_22]: V(False)
10124 prim_subreg #(
10125 .DW (1),
10126 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10127 .RESVAL (1'h0),
10128 .Mubi (1'b0)
10129 ) u_alert_cause_22 (
10130 .clk_i (clk_i),
10131 .rst_ni (rst_ni),
10132
10133 // from register interface
10134 .we (alert_cause_22_we),
10135 .wd (alert_cause_22_wd),
10136
10137 // from internal hardware
10138 .de (hw2reg.alert_cause[22].de),
10139 .d (hw2reg.alert_cause[22].d),
10140
10141 // to internal hardware
10142 .qe (),
10143 .q (reg2hw.alert_cause[22].q),
10144 .ds (),
10145
10146 // to register interface (read)
10147 .qs (alert_cause_22_qs)
10148 );
10149
10150
10151 // Subregister 23 of Multireg alert_cause
10152 // R[alert_cause_23]: V(False)
10153 prim_subreg #(
10154 .DW (1),
10155 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10156 .RESVAL (1'h0),
10157 .Mubi (1'b0)
10158 ) u_alert_cause_23 (
10159 .clk_i (clk_i),
10160 .rst_ni (rst_ni),
10161
10162 // from register interface
10163 .we (alert_cause_23_we),
10164 .wd (alert_cause_23_wd),
10165
10166 // from internal hardware
10167 .de (hw2reg.alert_cause[23].de),
10168 .d (hw2reg.alert_cause[23].d),
10169
10170 // to internal hardware
10171 .qe (),
10172 .q (reg2hw.alert_cause[23].q),
10173 .ds (),
10174
10175 // to register interface (read)
10176 .qs (alert_cause_23_qs)
10177 );
10178
10179
10180 // Subregister 24 of Multireg alert_cause
10181 // R[alert_cause_24]: V(False)
10182 prim_subreg #(
10183 .DW (1),
10184 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10185 .RESVAL (1'h0),
10186 .Mubi (1'b0)
10187 ) u_alert_cause_24 (
10188 .clk_i (clk_i),
10189 .rst_ni (rst_ni),
10190
10191 // from register interface
10192 .we (alert_cause_24_we),
10193 .wd (alert_cause_24_wd),
10194
10195 // from internal hardware
10196 .de (hw2reg.alert_cause[24].de),
10197 .d (hw2reg.alert_cause[24].d),
10198
10199 // to internal hardware
10200 .qe (),
10201 .q (reg2hw.alert_cause[24].q),
10202 .ds (),
10203
10204 // to register interface (read)
10205 .qs (alert_cause_24_qs)
10206 );
10207
10208
10209 // Subregister 25 of Multireg alert_cause
10210 // R[alert_cause_25]: V(False)
10211 prim_subreg #(
10212 .DW (1),
10213 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10214 .RESVAL (1'h0),
10215 .Mubi (1'b0)
10216 ) u_alert_cause_25 (
10217 .clk_i (clk_i),
10218 .rst_ni (rst_ni),
10219
10220 // from register interface
10221 .we (alert_cause_25_we),
10222 .wd (alert_cause_25_wd),
10223
10224 // from internal hardware
10225 .de (hw2reg.alert_cause[25].de),
10226 .d (hw2reg.alert_cause[25].d),
10227
10228 // to internal hardware
10229 .qe (),
10230 .q (reg2hw.alert_cause[25].q),
10231 .ds (),
10232
10233 // to register interface (read)
10234 .qs (alert_cause_25_qs)
10235 );
10236
10237
10238 // Subregister 26 of Multireg alert_cause
10239 // R[alert_cause_26]: V(False)
10240 prim_subreg #(
10241 .DW (1),
10242 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10243 .RESVAL (1'h0),
10244 .Mubi (1'b0)
10245 ) u_alert_cause_26 (
10246 .clk_i (clk_i),
10247 .rst_ni (rst_ni),
10248
10249 // from register interface
10250 .we (alert_cause_26_we),
10251 .wd (alert_cause_26_wd),
10252
10253 // from internal hardware
10254 .de (hw2reg.alert_cause[26].de),
10255 .d (hw2reg.alert_cause[26].d),
10256
10257 // to internal hardware
10258 .qe (),
10259 .q (reg2hw.alert_cause[26].q),
10260 .ds (),
10261
10262 // to register interface (read)
10263 .qs (alert_cause_26_qs)
10264 );
10265
10266
10267 // Subregister 27 of Multireg alert_cause
10268 // R[alert_cause_27]: V(False)
10269 prim_subreg #(
10270 .DW (1),
10271 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10272 .RESVAL (1'h0),
10273 .Mubi (1'b0)
10274 ) u_alert_cause_27 (
10275 .clk_i (clk_i),
10276 .rst_ni (rst_ni),
10277
10278 // from register interface
10279 .we (alert_cause_27_we),
10280 .wd (alert_cause_27_wd),
10281
10282 // from internal hardware
10283 .de (hw2reg.alert_cause[27].de),
10284 .d (hw2reg.alert_cause[27].d),
10285
10286 // to internal hardware
10287 .qe (),
10288 .q (reg2hw.alert_cause[27].q),
10289 .ds (),
10290
10291 // to register interface (read)
10292 .qs (alert_cause_27_qs)
10293 );
10294
10295
10296 // Subregister 28 of Multireg alert_cause
10297 // R[alert_cause_28]: V(False)
10298 prim_subreg #(
10299 .DW (1),
10300 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10301 .RESVAL (1'h0),
10302 .Mubi (1'b0)
10303 ) u_alert_cause_28 (
10304 .clk_i (clk_i),
10305 .rst_ni (rst_ni),
10306
10307 // from register interface
10308 .we (alert_cause_28_we),
10309 .wd (alert_cause_28_wd),
10310
10311 // from internal hardware
10312 .de (hw2reg.alert_cause[28].de),
10313 .d (hw2reg.alert_cause[28].d),
10314
10315 // to internal hardware
10316 .qe (),
10317 .q (reg2hw.alert_cause[28].q),
10318 .ds (),
10319
10320 // to register interface (read)
10321 .qs (alert_cause_28_qs)
10322 );
10323
10324
10325 // Subregister 29 of Multireg alert_cause
10326 // R[alert_cause_29]: V(False)
10327 prim_subreg #(
10328 .DW (1),
10329 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10330 .RESVAL (1'h0),
10331 .Mubi (1'b0)
10332 ) u_alert_cause_29 (
10333 .clk_i (clk_i),
10334 .rst_ni (rst_ni),
10335
10336 // from register interface
10337 .we (alert_cause_29_we),
10338 .wd (alert_cause_29_wd),
10339
10340 // from internal hardware
10341 .de (hw2reg.alert_cause[29].de),
10342 .d (hw2reg.alert_cause[29].d),
10343
10344 // to internal hardware
10345 .qe (),
10346 .q (reg2hw.alert_cause[29].q),
10347 .ds (),
10348
10349 // to register interface (read)
10350 .qs (alert_cause_29_qs)
10351 );
10352
10353
10354 // Subregister 30 of Multireg alert_cause
10355 // R[alert_cause_30]: V(False)
10356 prim_subreg #(
10357 .DW (1),
10358 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10359 .RESVAL (1'h0),
10360 .Mubi (1'b0)
10361 ) u_alert_cause_30 (
10362 .clk_i (clk_i),
10363 .rst_ni (rst_ni),
10364
10365 // from register interface
10366 .we (alert_cause_30_we),
10367 .wd (alert_cause_30_wd),
10368
10369 // from internal hardware
10370 .de (hw2reg.alert_cause[30].de),
10371 .d (hw2reg.alert_cause[30].d),
10372
10373 // to internal hardware
10374 .qe (),
10375 .q (reg2hw.alert_cause[30].q),
10376 .ds (),
10377
10378 // to register interface (read)
10379 .qs (alert_cause_30_qs)
10380 );
10381
10382
10383 // Subregister 31 of Multireg alert_cause
10384 // R[alert_cause_31]: V(False)
10385 prim_subreg #(
10386 .DW (1),
10387 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10388 .RESVAL (1'h0),
10389 .Mubi (1'b0)
10390 ) u_alert_cause_31 (
10391 .clk_i (clk_i),
10392 .rst_ni (rst_ni),
10393
10394 // from register interface
10395 .we (alert_cause_31_we),
10396 .wd (alert_cause_31_wd),
10397
10398 // from internal hardware
10399 .de (hw2reg.alert_cause[31].de),
10400 .d (hw2reg.alert_cause[31].d),
10401
10402 // to internal hardware
10403 .qe (),
10404 .q (reg2hw.alert_cause[31].q),
10405 .ds (),
10406
10407 // to register interface (read)
10408 .qs (alert_cause_31_qs)
10409 );
10410
10411
10412 // Subregister 32 of Multireg alert_cause
10413 // R[alert_cause_32]: V(False)
10414 prim_subreg #(
10415 .DW (1),
10416 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10417 .RESVAL (1'h0),
10418 .Mubi (1'b0)
10419 ) u_alert_cause_32 (
10420 .clk_i (clk_i),
10421 .rst_ni (rst_ni),
10422
10423 // from register interface
10424 .we (alert_cause_32_we),
10425 .wd (alert_cause_32_wd),
10426
10427 // from internal hardware
10428 .de (hw2reg.alert_cause[32].de),
10429 .d (hw2reg.alert_cause[32].d),
10430
10431 // to internal hardware
10432 .qe (),
10433 .q (reg2hw.alert_cause[32].q),
10434 .ds (),
10435
10436 // to register interface (read)
10437 .qs (alert_cause_32_qs)
10438 );
10439
10440
10441 // Subregister 33 of Multireg alert_cause
10442 // R[alert_cause_33]: V(False)
10443 prim_subreg #(
10444 .DW (1),
10445 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10446 .RESVAL (1'h0),
10447 .Mubi (1'b0)
10448 ) u_alert_cause_33 (
10449 .clk_i (clk_i),
10450 .rst_ni (rst_ni),
10451
10452 // from register interface
10453 .we (alert_cause_33_we),
10454 .wd (alert_cause_33_wd),
10455
10456 // from internal hardware
10457 .de (hw2reg.alert_cause[33].de),
10458 .d (hw2reg.alert_cause[33].d),
10459
10460 // to internal hardware
10461 .qe (),
10462 .q (reg2hw.alert_cause[33].q),
10463 .ds (),
10464
10465 // to register interface (read)
10466 .qs (alert_cause_33_qs)
10467 );
10468
10469
10470 // Subregister 34 of Multireg alert_cause
10471 // R[alert_cause_34]: V(False)
10472 prim_subreg #(
10473 .DW (1),
10474 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10475 .RESVAL (1'h0),
10476 .Mubi (1'b0)
10477 ) u_alert_cause_34 (
10478 .clk_i (clk_i),
10479 .rst_ni (rst_ni),
10480
10481 // from register interface
10482 .we (alert_cause_34_we),
10483 .wd (alert_cause_34_wd),
10484
10485 // from internal hardware
10486 .de (hw2reg.alert_cause[34].de),
10487 .d (hw2reg.alert_cause[34].d),
10488
10489 // to internal hardware
10490 .qe (),
10491 .q (reg2hw.alert_cause[34].q),
10492 .ds (),
10493
10494 // to register interface (read)
10495 .qs (alert_cause_34_qs)
10496 );
10497
10498
10499 // Subregister 35 of Multireg alert_cause
10500 // R[alert_cause_35]: V(False)
10501 prim_subreg #(
10502 .DW (1),
10503 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10504 .RESVAL (1'h0),
10505 .Mubi (1'b0)
10506 ) u_alert_cause_35 (
10507 .clk_i (clk_i),
10508 .rst_ni (rst_ni),
10509
10510 // from register interface
10511 .we (alert_cause_35_we),
10512 .wd (alert_cause_35_wd),
10513
10514 // from internal hardware
10515 .de (hw2reg.alert_cause[35].de),
10516 .d (hw2reg.alert_cause[35].d),
10517
10518 // to internal hardware
10519 .qe (),
10520 .q (reg2hw.alert_cause[35].q),
10521 .ds (),
10522
10523 // to register interface (read)
10524 .qs (alert_cause_35_qs)
10525 );
10526
10527
10528 // Subregister 36 of Multireg alert_cause
10529 // R[alert_cause_36]: V(False)
10530 prim_subreg #(
10531 .DW (1),
10532 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10533 .RESVAL (1'h0),
10534 .Mubi (1'b0)
10535 ) u_alert_cause_36 (
10536 .clk_i (clk_i),
10537 .rst_ni (rst_ni),
10538
10539 // from register interface
10540 .we (alert_cause_36_we),
10541 .wd (alert_cause_36_wd),
10542
10543 // from internal hardware
10544 .de (hw2reg.alert_cause[36].de),
10545 .d (hw2reg.alert_cause[36].d),
10546
10547 // to internal hardware
10548 .qe (),
10549 .q (reg2hw.alert_cause[36].q),
10550 .ds (),
10551
10552 // to register interface (read)
10553 .qs (alert_cause_36_qs)
10554 );
10555
10556
10557 // Subregister 37 of Multireg alert_cause
10558 // R[alert_cause_37]: V(False)
10559 prim_subreg #(
10560 .DW (1),
10561 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10562 .RESVAL (1'h0),
10563 .Mubi (1'b0)
10564 ) u_alert_cause_37 (
10565 .clk_i (clk_i),
10566 .rst_ni (rst_ni),
10567
10568 // from register interface
10569 .we (alert_cause_37_we),
10570 .wd (alert_cause_37_wd),
10571
10572 // from internal hardware
10573 .de (hw2reg.alert_cause[37].de),
10574 .d (hw2reg.alert_cause[37].d),
10575
10576 // to internal hardware
10577 .qe (),
10578 .q (reg2hw.alert_cause[37].q),
10579 .ds (),
10580
10581 // to register interface (read)
10582 .qs (alert_cause_37_qs)
10583 );
10584
10585
10586 // Subregister 38 of Multireg alert_cause
10587 // R[alert_cause_38]: V(False)
10588 prim_subreg #(
10589 .DW (1),
10590 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10591 .RESVAL (1'h0),
10592 .Mubi (1'b0)
10593 ) u_alert_cause_38 (
10594 .clk_i (clk_i),
10595 .rst_ni (rst_ni),
10596
10597 // from register interface
10598 .we (alert_cause_38_we),
10599 .wd (alert_cause_38_wd),
10600
10601 // from internal hardware
10602 .de (hw2reg.alert_cause[38].de),
10603 .d (hw2reg.alert_cause[38].d),
10604
10605 // to internal hardware
10606 .qe (),
10607 .q (reg2hw.alert_cause[38].q),
10608 .ds (),
10609
10610 // to register interface (read)
10611 .qs (alert_cause_38_qs)
10612 );
10613
10614
10615 // Subregister 39 of Multireg alert_cause
10616 // R[alert_cause_39]: V(False)
10617 prim_subreg #(
10618 .DW (1),
10619 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10620 .RESVAL (1'h0),
10621 .Mubi (1'b0)
10622 ) u_alert_cause_39 (
10623 .clk_i (clk_i),
10624 .rst_ni (rst_ni),
10625
10626 // from register interface
10627 .we (alert_cause_39_we),
10628 .wd (alert_cause_39_wd),
10629
10630 // from internal hardware
10631 .de (hw2reg.alert_cause[39].de),
10632 .d (hw2reg.alert_cause[39].d),
10633
10634 // to internal hardware
10635 .qe (),
10636 .q (reg2hw.alert_cause[39].q),
10637 .ds (),
10638
10639 // to register interface (read)
10640 .qs (alert_cause_39_qs)
10641 );
10642
10643
10644 // Subregister 40 of Multireg alert_cause
10645 // R[alert_cause_40]: V(False)
10646 prim_subreg #(
10647 .DW (1),
10648 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10649 .RESVAL (1'h0),
10650 .Mubi (1'b0)
10651 ) u_alert_cause_40 (
10652 .clk_i (clk_i),
10653 .rst_ni (rst_ni),
10654
10655 // from register interface
10656 .we (alert_cause_40_we),
10657 .wd (alert_cause_40_wd),
10658
10659 // from internal hardware
10660 .de (hw2reg.alert_cause[40].de),
10661 .d (hw2reg.alert_cause[40].d),
10662
10663 // to internal hardware
10664 .qe (),
10665 .q (reg2hw.alert_cause[40].q),
10666 .ds (),
10667
10668 // to register interface (read)
10669 .qs (alert_cause_40_qs)
10670 );
10671
10672
10673 // Subregister 41 of Multireg alert_cause
10674 // R[alert_cause_41]: V(False)
10675 prim_subreg #(
10676 .DW (1),
10677 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10678 .RESVAL (1'h0),
10679 .Mubi (1'b0)
10680 ) u_alert_cause_41 (
10681 .clk_i (clk_i),
10682 .rst_ni (rst_ni),
10683
10684 // from register interface
10685 .we (alert_cause_41_we),
10686 .wd (alert_cause_41_wd),
10687
10688 // from internal hardware
10689 .de (hw2reg.alert_cause[41].de),
10690 .d (hw2reg.alert_cause[41].d),
10691
10692 // to internal hardware
10693 .qe (),
10694 .q (reg2hw.alert_cause[41].q),
10695 .ds (),
10696
10697 // to register interface (read)
10698 .qs (alert_cause_41_qs)
10699 );
10700
10701
10702 // Subregister 42 of Multireg alert_cause
10703 // R[alert_cause_42]: V(False)
10704 prim_subreg #(
10705 .DW (1),
10706 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10707 .RESVAL (1'h0),
10708 .Mubi (1'b0)
10709 ) u_alert_cause_42 (
10710 .clk_i (clk_i),
10711 .rst_ni (rst_ni),
10712
10713 // from register interface
10714 .we (alert_cause_42_we),
10715 .wd (alert_cause_42_wd),
10716
10717 // from internal hardware
10718 .de (hw2reg.alert_cause[42].de),
10719 .d (hw2reg.alert_cause[42].d),
10720
10721 // to internal hardware
10722 .qe (),
10723 .q (reg2hw.alert_cause[42].q),
10724 .ds (),
10725
10726 // to register interface (read)
10727 .qs (alert_cause_42_qs)
10728 );
10729
10730
10731 // Subregister 43 of Multireg alert_cause
10732 // R[alert_cause_43]: V(False)
10733 prim_subreg #(
10734 .DW (1),
10735 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10736 .RESVAL (1'h0),
10737 .Mubi (1'b0)
10738 ) u_alert_cause_43 (
10739 .clk_i (clk_i),
10740 .rst_ni (rst_ni),
10741
10742 // from register interface
10743 .we (alert_cause_43_we),
10744 .wd (alert_cause_43_wd),
10745
10746 // from internal hardware
10747 .de (hw2reg.alert_cause[43].de),
10748 .d (hw2reg.alert_cause[43].d),
10749
10750 // to internal hardware
10751 .qe (),
10752 .q (reg2hw.alert_cause[43].q),
10753 .ds (),
10754
10755 // to register interface (read)
10756 .qs (alert_cause_43_qs)
10757 );
10758
10759
10760 // Subregister 44 of Multireg alert_cause
10761 // R[alert_cause_44]: V(False)
10762 prim_subreg #(
10763 .DW (1),
10764 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10765 .RESVAL (1'h0),
10766 .Mubi (1'b0)
10767 ) u_alert_cause_44 (
10768 .clk_i (clk_i),
10769 .rst_ni (rst_ni),
10770
10771 // from register interface
10772 .we (alert_cause_44_we),
10773 .wd (alert_cause_44_wd),
10774
10775 // from internal hardware
10776 .de (hw2reg.alert_cause[44].de),
10777 .d (hw2reg.alert_cause[44].d),
10778
10779 // to internal hardware
10780 .qe (),
10781 .q (reg2hw.alert_cause[44].q),
10782 .ds (),
10783
10784 // to register interface (read)
10785 .qs (alert_cause_44_qs)
10786 );
10787
10788
10789 // Subregister 45 of Multireg alert_cause
10790 // R[alert_cause_45]: V(False)
10791 prim_subreg #(
10792 .DW (1),
10793 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10794 .RESVAL (1'h0),
10795 .Mubi (1'b0)
10796 ) u_alert_cause_45 (
10797 .clk_i (clk_i),
10798 .rst_ni (rst_ni),
10799
10800 // from register interface
10801 .we (alert_cause_45_we),
10802 .wd (alert_cause_45_wd),
10803
10804 // from internal hardware
10805 .de (hw2reg.alert_cause[45].de),
10806 .d (hw2reg.alert_cause[45].d),
10807
10808 // to internal hardware
10809 .qe (),
10810 .q (reg2hw.alert_cause[45].q),
10811 .ds (),
10812
10813 // to register interface (read)
10814 .qs (alert_cause_45_qs)
10815 );
10816
10817
10818 // Subregister 46 of Multireg alert_cause
10819 // R[alert_cause_46]: V(False)
10820 prim_subreg #(
10821 .DW (1),
10822 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10823 .RESVAL (1'h0),
10824 .Mubi (1'b0)
10825 ) u_alert_cause_46 (
10826 .clk_i (clk_i),
10827 .rst_ni (rst_ni),
10828
10829 // from register interface
10830 .we (alert_cause_46_we),
10831 .wd (alert_cause_46_wd),
10832
10833 // from internal hardware
10834 .de (hw2reg.alert_cause[46].de),
10835 .d (hw2reg.alert_cause[46].d),
10836
10837 // to internal hardware
10838 .qe (),
10839 .q (reg2hw.alert_cause[46].q),
10840 .ds (),
10841
10842 // to register interface (read)
10843 .qs (alert_cause_46_qs)
10844 );
10845
10846
10847 // Subregister 47 of Multireg alert_cause
10848 // R[alert_cause_47]: V(False)
10849 prim_subreg #(
10850 .DW (1),
10851 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10852 .RESVAL (1'h0),
10853 .Mubi (1'b0)
10854 ) u_alert_cause_47 (
10855 .clk_i (clk_i),
10856 .rst_ni (rst_ni),
10857
10858 // from register interface
10859 .we (alert_cause_47_we),
10860 .wd (alert_cause_47_wd),
10861
10862 // from internal hardware
10863 .de (hw2reg.alert_cause[47].de),
10864 .d (hw2reg.alert_cause[47].d),
10865
10866 // to internal hardware
10867 .qe (),
10868 .q (reg2hw.alert_cause[47].q),
10869 .ds (),
10870
10871 // to register interface (read)
10872 .qs (alert_cause_47_qs)
10873 );
10874
10875
10876 // Subregister 48 of Multireg alert_cause
10877 // R[alert_cause_48]: V(False)
10878 prim_subreg #(
10879 .DW (1),
10880 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10881 .RESVAL (1'h0),
10882 .Mubi (1'b0)
10883 ) u_alert_cause_48 (
10884 .clk_i (clk_i),
10885 .rst_ni (rst_ni),
10886
10887 // from register interface
10888 .we (alert_cause_48_we),
10889 .wd (alert_cause_48_wd),
10890
10891 // from internal hardware
10892 .de (hw2reg.alert_cause[48].de),
10893 .d (hw2reg.alert_cause[48].d),
10894
10895 // to internal hardware
10896 .qe (),
10897 .q (reg2hw.alert_cause[48].q),
10898 .ds (),
10899
10900 // to register interface (read)
10901 .qs (alert_cause_48_qs)
10902 );
10903
10904
10905 // Subregister 49 of Multireg alert_cause
10906 // R[alert_cause_49]: V(False)
10907 prim_subreg #(
10908 .DW (1),
10909 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10910 .RESVAL (1'h0),
10911 .Mubi (1'b0)
10912 ) u_alert_cause_49 (
10913 .clk_i (clk_i),
10914 .rst_ni (rst_ni),
10915
10916 // from register interface
10917 .we (alert_cause_49_we),
10918 .wd (alert_cause_49_wd),
10919
10920 // from internal hardware
10921 .de (hw2reg.alert_cause[49].de),
10922 .d (hw2reg.alert_cause[49].d),
10923
10924 // to internal hardware
10925 .qe (),
10926 .q (reg2hw.alert_cause[49].q),
10927 .ds (),
10928
10929 // to register interface (read)
10930 .qs (alert_cause_49_qs)
10931 );
10932
10933
10934 // Subregister 50 of Multireg alert_cause
10935 // R[alert_cause_50]: V(False)
10936 prim_subreg #(
10937 .DW (1),
10938 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10939 .RESVAL (1'h0),
10940 .Mubi (1'b0)
10941 ) u_alert_cause_50 (
10942 .clk_i (clk_i),
10943 .rst_ni (rst_ni),
10944
10945 // from register interface
10946 .we (alert_cause_50_we),
10947 .wd (alert_cause_50_wd),
10948
10949 // from internal hardware
10950 .de (hw2reg.alert_cause[50].de),
10951 .d (hw2reg.alert_cause[50].d),
10952
10953 // to internal hardware
10954 .qe (),
10955 .q (reg2hw.alert_cause[50].q),
10956 .ds (),
10957
10958 // to register interface (read)
10959 .qs (alert_cause_50_qs)
10960 );
10961
10962
10963 // Subregister 51 of Multireg alert_cause
10964 // R[alert_cause_51]: V(False)
10965 prim_subreg #(
10966 .DW (1),
10967 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10968 .RESVAL (1'h0),
10969 .Mubi (1'b0)
10970 ) u_alert_cause_51 (
10971 .clk_i (clk_i),
10972 .rst_ni (rst_ni),
10973
10974 // from register interface
10975 .we (alert_cause_51_we),
10976 .wd (alert_cause_51_wd),
10977
10978 // from internal hardware
10979 .de (hw2reg.alert_cause[51].de),
10980 .d (hw2reg.alert_cause[51].d),
10981
10982 // to internal hardware
10983 .qe (),
10984 .q (reg2hw.alert_cause[51].q),
10985 .ds (),
10986
10987 // to register interface (read)
10988 .qs (alert_cause_51_qs)
10989 );
10990
10991
10992 // Subregister 52 of Multireg alert_cause
10993 // R[alert_cause_52]: V(False)
10994 prim_subreg #(
10995 .DW (1),
10996 .SwAccess(prim_subreg_pkg::SwAccessW1C),
10997 .RESVAL (1'h0),
10998 .Mubi (1'b0)
10999 ) u_alert_cause_52 (
11000 .clk_i (clk_i),
11001 .rst_ni (rst_ni),
11002
11003 // from register interface
11004 .we (alert_cause_52_we),
11005 .wd (alert_cause_52_wd),
11006
11007 // from internal hardware
11008 .de (hw2reg.alert_cause[52].de),
11009 .d (hw2reg.alert_cause[52].d),
11010
11011 // to internal hardware
11012 .qe (),
11013 .q (reg2hw.alert_cause[52].q),
11014 .ds (),
11015
11016 // to register interface (read)
11017 .qs (alert_cause_52_qs)
11018 );
11019
11020
11021 // Subregister 53 of Multireg alert_cause
11022 // R[alert_cause_53]: V(False)
11023 prim_subreg #(
11024 .DW (1),
11025 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11026 .RESVAL (1'h0),
11027 .Mubi (1'b0)
11028 ) u_alert_cause_53 (
11029 .clk_i (clk_i),
11030 .rst_ni (rst_ni),
11031
11032 // from register interface
11033 .we (alert_cause_53_we),
11034 .wd (alert_cause_53_wd),
11035
11036 // from internal hardware
11037 .de (hw2reg.alert_cause[53].de),
11038 .d (hw2reg.alert_cause[53].d),
11039
11040 // to internal hardware
11041 .qe (),
11042 .q (reg2hw.alert_cause[53].q),
11043 .ds (),
11044
11045 // to register interface (read)
11046 .qs (alert_cause_53_qs)
11047 );
11048
11049
11050 // Subregister 54 of Multireg alert_cause
11051 // R[alert_cause_54]: V(False)
11052 prim_subreg #(
11053 .DW (1),
11054 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11055 .RESVAL (1'h0),
11056 .Mubi (1'b0)
11057 ) u_alert_cause_54 (
11058 .clk_i (clk_i),
11059 .rst_ni (rst_ni),
11060
11061 // from register interface
11062 .we (alert_cause_54_we),
11063 .wd (alert_cause_54_wd),
11064
11065 // from internal hardware
11066 .de (hw2reg.alert_cause[54].de),
11067 .d (hw2reg.alert_cause[54].d),
11068
11069 // to internal hardware
11070 .qe (),
11071 .q (reg2hw.alert_cause[54].q),
11072 .ds (),
11073
11074 // to register interface (read)
11075 .qs (alert_cause_54_qs)
11076 );
11077
11078
11079 // Subregister 55 of Multireg alert_cause
11080 // R[alert_cause_55]: V(False)
11081 prim_subreg #(
11082 .DW (1),
11083 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11084 .RESVAL (1'h0),
11085 .Mubi (1'b0)
11086 ) u_alert_cause_55 (
11087 .clk_i (clk_i),
11088 .rst_ni (rst_ni),
11089
11090 // from register interface
11091 .we (alert_cause_55_we),
11092 .wd (alert_cause_55_wd),
11093
11094 // from internal hardware
11095 .de (hw2reg.alert_cause[55].de),
11096 .d (hw2reg.alert_cause[55].d),
11097
11098 // to internal hardware
11099 .qe (),
11100 .q (reg2hw.alert_cause[55].q),
11101 .ds (),
11102
11103 // to register interface (read)
11104 .qs (alert_cause_55_qs)
11105 );
11106
11107
11108 // Subregister 56 of Multireg alert_cause
11109 // R[alert_cause_56]: V(False)
11110 prim_subreg #(
11111 .DW (1),
11112 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11113 .RESVAL (1'h0),
11114 .Mubi (1'b0)
11115 ) u_alert_cause_56 (
11116 .clk_i (clk_i),
11117 .rst_ni (rst_ni),
11118
11119 // from register interface
11120 .we (alert_cause_56_we),
11121 .wd (alert_cause_56_wd),
11122
11123 // from internal hardware
11124 .de (hw2reg.alert_cause[56].de),
11125 .d (hw2reg.alert_cause[56].d),
11126
11127 // to internal hardware
11128 .qe (),
11129 .q (reg2hw.alert_cause[56].q),
11130 .ds (),
11131
11132 // to register interface (read)
11133 .qs (alert_cause_56_qs)
11134 );
11135
11136
11137 // Subregister 57 of Multireg alert_cause
11138 // R[alert_cause_57]: V(False)
11139 prim_subreg #(
11140 .DW (1),
11141 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11142 .RESVAL (1'h0),
11143 .Mubi (1'b0)
11144 ) u_alert_cause_57 (
11145 .clk_i (clk_i),
11146 .rst_ni (rst_ni),
11147
11148 // from register interface
11149 .we (alert_cause_57_we),
11150 .wd (alert_cause_57_wd),
11151
11152 // from internal hardware
11153 .de (hw2reg.alert_cause[57].de),
11154 .d (hw2reg.alert_cause[57].d),
11155
11156 // to internal hardware
11157 .qe (),
11158 .q (reg2hw.alert_cause[57].q),
11159 .ds (),
11160
11161 // to register interface (read)
11162 .qs (alert_cause_57_qs)
11163 );
11164
11165
11166 // Subregister 58 of Multireg alert_cause
11167 // R[alert_cause_58]: V(False)
11168 prim_subreg #(
11169 .DW (1),
11170 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11171 .RESVAL (1'h0),
11172 .Mubi (1'b0)
11173 ) u_alert_cause_58 (
11174 .clk_i (clk_i),
11175 .rst_ni (rst_ni),
11176
11177 // from register interface
11178 .we (alert_cause_58_we),
11179 .wd (alert_cause_58_wd),
11180
11181 // from internal hardware
11182 .de (hw2reg.alert_cause[58].de),
11183 .d (hw2reg.alert_cause[58].d),
11184
11185 // to internal hardware
11186 .qe (),
11187 .q (reg2hw.alert_cause[58].q),
11188 .ds (),
11189
11190 // to register interface (read)
11191 .qs (alert_cause_58_qs)
11192 );
11193
11194
11195 // Subregister 59 of Multireg alert_cause
11196 // R[alert_cause_59]: V(False)
11197 prim_subreg #(
11198 .DW (1),
11199 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11200 .RESVAL (1'h0),
11201 .Mubi (1'b0)
11202 ) u_alert_cause_59 (
11203 .clk_i (clk_i),
11204 .rst_ni (rst_ni),
11205
11206 // from register interface
11207 .we (alert_cause_59_we),
11208 .wd (alert_cause_59_wd),
11209
11210 // from internal hardware
11211 .de (hw2reg.alert_cause[59].de),
11212 .d (hw2reg.alert_cause[59].d),
11213
11214 // to internal hardware
11215 .qe (),
11216 .q (reg2hw.alert_cause[59].q),
11217 .ds (),
11218
11219 // to register interface (read)
11220 .qs (alert_cause_59_qs)
11221 );
11222
11223
11224 // Subregister 60 of Multireg alert_cause
11225 // R[alert_cause_60]: V(False)
11226 prim_subreg #(
11227 .DW (1),
11228 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11229 .RESVAL (1'h0),
11230 .Mubi (1'b0)
11231 ) u_alert_cause_60 (
11232 .clk_i (clk_i),
11233 .rst_ni (rst_ni),
11234
11235 // from register interface
11236 .we (alert_cause_60_we),
11237 .wd (alert_cause_60_wd),
11238
11239 // from internal hardware
11240 .de (hw2reg.alert_cause[60].de),
11241 .d (hw2reg.alert_cause[60].d),
11242
11243 // to internal hardware
11244 .qe (),
11245 .q (reg2hw.alert_cause[60].q),
11246 .ds (),
11247
11248 // to register interface (read)
11249 .qs (alert_cause_60_qs)
11250 );
11251
11252
11253 // Subregister 61 of Multireg alert_cause
11254 // R[alert_cause_61]: V(False)
11255 prim_subreg #(
11256 .DW (1),
11257 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11258 .RESVAL (1'h0),
11259 .Mubi (1'b0)
11260 ) u_alert_cause_61 (
11261 .clk_i (clk_i),
11262 .rst_ni (rst_ni),
11263
11264 // from register interface
11265 .we (alert_cause_61_we),
11266 .wd (alert_cause_61_wd),
11267
11268 // from internal hardware
11269 .de (hw2reg.alert_cause[61].de),
11270 .d (hw2reg.alert_cause[61].d),
11271
11272 // to internal hardware
11273 .qe (),
11274 .q (reg2hw.alert_cause[61].q),
11275 .ds (),
11276
11277 // to register interface (read)
11278 .qs (alert_cause_61_qs)
11279 );
11280
11281
11282 // Subregister 62 of Multireg alert_cause
11283 // R[alert_cause_62]: V(False)
11284 prim_subreg #(
11285 .DW (1),
11286 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11287 .RESVAL (1'h0),
11288 .Mubi (1'b0)
11289 ) u_alert_cause_62 (
11290 .clk_i (clk_i),
11291 .rst_ni (rst_ni),
11292
11293 // from register interface
11294 .we (alert_cause_62_we),
11295 .wd (alert_cause_62_wd),
11296
11297 // from internal hardware
11298 .de (hw2reg.alert_cause[62].de),
11299 .d (hw2reg.alert_cause[62].d),
11300
11301 // to internal hardware
11302 .qe (),
11303 .q (reg2hw.alert_cause[62].q),
11304 .ds (),
11305
11306 // to register interface (read)
11307 .qs (alert_cause_62_qs)
11308 );
11309
11310
11311 // Subregister 63 of Multireg alert_cause
11312 // R[alert_cause_63]: V(False)
11313 prim_subreg #(
11314 .DW (1),
11315 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11316 .RESVAL (1'h0),
11317 .Mubi (1'b0)
11318 ) u_alert_cause_63 (
11319 .clk_i (clk_i),
11320 .rst_ni (rst_ni),
11321
11322 // from register interface
11323 .we (alert_cause_63_we),
11324 .wd (alert_cause_63_wd),
11325
11326 // from internal hardware
11327 .de (hw2reg.alert_cause[63].de),
11328 .d (hw2reg.alert_cause[63].d),
11329
11330 // to internal hardware
11331 .qe (),
11332 .q (reg2hw.alert_cause[63].q),
11333 .ds (),
11334
11335 // to register interface (read)
11336 .qs (alert_cause_63_qs)
11337 );
11338
11339
11340 // Subregister 64 of Multireg alert_cause
11341 // R[alert_cause_64]: V(False)
11342 prim_subreg #(
11343 .DW (1),
11344 .SwAccess(prim_subreg_pkg::SwAccessW1C),
11345 .RESVAL (1'h0),
11346 .Mubi (1'b0)
11347 ) u_alert_cause_64 (
11348 .clk_i (clk_i),
11349 .rst_ni (rst_ni),
11350
11351 // from register interface
11352 .we (alert_cause_64_we),
11353 .wd (alert_cause_64_wd),
11354
11355 // from internal hardware
11356 .de (hw2reg.alert_cause[64].de),
11357 .d (hw2reg.alert_cause[64].d),
11358
11359 // to internal hardware
11360 .qe (),
11361 .q (reg2hw.alert_cause[64].q),
11362 .ds (),
11363
11364 // to register interface (read)
11365 .qs (alert_cause_64_qs)
11366 );
11367
11368
11369 // Subregister 0 of Multireg loc_alert_regwen
11370 // R[loc_alert_regwen_0]: V(False)
11371 prim_subreg #(
11372 .DW (1),
11373 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11374 .RESVAL (1'h1),
11375 .Mubi (1'b0)
11376 ) u_loc_alert_regwen_0 (
11377 .clk_i (clk_i),
11378 .rst_ni (rst_ni),
11379
11380 // from register interface
11381 .we (loc_alert_regwen_0_we),
11382 .wd (loc_alert_regwen_0_wd),
11383
11384 // from internal hardware
11385 .de (1'b0),
11386 .d ('0),
11387
11388 // to internal hardware
11389 .qe (),
11390 .q (),
11391 .ds (),
11392
11393 // to register interface (read)
11394 .qs (loc_alert_regwen_0_qs)
11395 );
11396
11397
11398 // Subregister 1 of Multireg loc_alert_regwen
11399 // R[loc_alert_regwen_1]: V(False)
11400 prim_subreg #(
11401 .DW (1),
11402 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11403 .RESVAL (1'h1),
11404 .Mubi (1'b0)
11405 ) u_loc_alert_regwen_1 (
11406 .clk_i (clk_i),
11407 .rst_ni (rst_ni),
11408
11409 // from register interface
11410 .we (loc_alert_regwen_1_we),
11411 .wd (loc_alert_regwen_1_wd),
11412
11413 // from internal hardware
11414 .de (1'b0),
11415 .d ('0),
11416
11417 // to internal hardware
11418 .qe (),
11419 .q (),
11420 .ds (),
11421
11422 // to register interface (read)
11423 .qs (loc_alert_regwen_1_qs)
11424 );
11425
11426
11427 // Subregister 2 of Multireg loc_alert_regwen
11428 // R[loc_alert_regwen_2]: V(False)
11429 prim_subreg #(
11430 .DW (1),
11431 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11432 .RESVAL (1'h1),
11433 .Mubi (1'b0)
11434 ) u_loc_alert_regwen_2 (
11435 .clk_i (clk_i),
11436 .rst_ni (rst_ni),
11437
11438 // from register interface
11439 .we (loc_alert_regwen_2_we),
11440 .wd (loc_alert_regwen_2_wd),
11441
11442 // from internal hardware
11443 .de (1'b0),
11444 .d ('0),
11445
11446 // to internal hardware
11447 .qe (),
11448 .q (),
11449 .ds (),
11450
11451 // to register interface (read)
11452 .qs (loc_alert_regwen_2_qs)
11453 );
11454
11455
11456 // Subregister 3 of Multireg loc_alert_regwen
11457 // R[loc_alert_regwen_3]: V(False)
11458 prim_subreg #(
11459 .DW (1),
11460 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11461 .RESVAL (1'h1),
11462 .Mubi (1'b0)
11463 ) u_loc_alert_regwen_3 (
11464 .clk_i (clk_i),
11465 .rst_ni (rst_ni),
11466
11467 // from register interface
11468 .we (loc_alert_regwen_3_we),
11469 .wd (loc_alert_regwen_3_wd),
11470
11471 // from internal hardware
11472 .de (1'b0),
11473 .d ('0),
11474
11475 // to internal hardware
11476 .qe (),
11477 .q (),
11478 .ds (),
11479
11480 // to register interface (read)
11481 .qs (loc_alert_regwen_3_qs)
11482 );
11483
11484
11485 // Subregister 4 of Multireg loc_alert_regwen
11486 // R[loc_alert_regwen_4]: V(False)
11487 prim_subreg #(
11488 .DW (1),
11489 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11490 .RESVAL (1'h1),
11491 .Mubi (1'b0)
11492 ) u_loc_alert_regwen_4 (
11493 .clk_i (clk_i),
11494 .rst_ni (rst_ni),
11495
11496 // from register interface
11497 .we (loc_alert_regwen_4_we),
11498 .wd (loc_alert_regwen_4_wd),
11499
11500 // from internal hardware
11501 .de (1'b0),
11502 .d ('0),
11503
11504 // to internal hardware
11505 .qe (),
11506 .q (),
11507 .ds (),
11508
11509 // to register interface (read)
11510 .qs (loc_alert_regwen_4_qs)
11511 );
11512
11513
11514 // Subregister 5 of Multireg loc_alert_regwen
11515 // R[loc_alert_regwen_5]: V(False)
11516 prim_subreg #(
11517 .DW (1),
11518 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11519 .RESVAL (1'h1),
11520 .Mubi (1'b0)
11521 ) u_loc_alert_regwen_5 (
11522 .clk_i (clk_i),
11523 .rst_ni (rst_ni),
11524
11525 // from register interface
11526 .we (loc_alert_regwen_5_we),
11527 .wd (loc_alert_regwen_5_wd),
11528
11529 // from internal hardware
11530 .de (1'b0),
11531 .d ('0),
11532
11533 // to internal hardware
11534 .qe (),
11535 .q (),
11536 .ds (),
11537
11538 // to register interface (read)
11539 .qs (loc_alert_regwen_5_qs)
11540 );
11541
11542
11543 // Subregister 6 of Multireg loc_alert_regwen
11544 // R[loc_alert_regwen_6]: V(False)
11545 prim_subreg #(
11546 .DW (1),
11547 .SwAccess(prim_subreg_pkg::SwAccessW0C),
11548 .RESVAL (1'h1),
11549 .Mubi (1'b0)
11550 ) u_loc_alert_regwen_6 (
11551 .clk_i (clk_i),
11552 .rst_ni (rst_ni),
11553
11554 // from register interface
11555 .we (loc_alert_regwen_6_we),
11556 .wd (loc_alert_regwen_6_wd),
11557
11558 // from internal hardware
11559 .de (1'b0),
11560 .d ('0),
11561
11562 // to internal hardware
11563 .qe (),
11564 .q (),
11565 .ds (),
11566
11567 // to register interface (read)
11568 .qs (loc_alert_regwen_6_qs)
11569 );
11570
11571
11572 // Subregister 0 of Multireg loc_alert_en_shadowed
11573 // R[loc_alert_en_shadowed_0]: V(False)
11574 // Create REGWEN-gated WE signal
11575 logic loc_alert_en_shadowed_0_gated_we;
11576 1/1 assign loc_alert_en_shadowed_0_gated_we = loc_alert_en_shadowed_0_we & loc_alert_regwen_0_qs;
Tests: T1 T2 T3
11577 prim_subreg_shadow #(
11578 .DW (1),
11579 .SwAccess(prim_subreg_pkg::SwAccessRW),
11580 .RESVAL (1'h0),
11581 .Mubi (1'b0)
11582 ) u_loc_alert_en_shadowed_0 (
11583 .clk_i (clk_i),
11584 .rst_ni (rst_ni),
11585 .rst_shadowed_ni (rst_shadowed_ni),
11586
11587 // from register interface
11588 .re (loc_alert_en_shadowed_0_re),
11589 .we (loc_alert_en_shadowed_0_gated_we),
11590 .wd (loc_alert_en_shadowed_0_wd),
11591
11592 // from internal hardware
11593 .de (1'b0),
11594 .d ('0),
11595
11596 // to internal hardware
11597 .qe (),
11598 .q (reg2hw.loc_alert_en_shadowed[0].q),
11599 .ds (),
11600
11601 // to register interface (read)
11602 .qs (loc_alert_en_shadowed_0_qs),
11603
11604 // Shadow register phase. Relevant for hwext only.
11605 .phase (),
11606
11607 // Shadow register error conditions
11608 .err_update (loc_alert_en_shadowed_0_update_err),
11609 .err_storage (loc_alert_en_shadowed_0_storage_err)
11610 );
11611
11612
11613 // Subregister 1 of Multireg loc_alert_en_shadowed
11614 // R[loc_alert_en_shadowed_1]: V(False)
11615 // Create REGWEN-gated WE signal
11616 logic loc_alert_en_shadowed_1_gated_we;
11617 1/1 assign loc_alert_en_shadowed_1_gated_we = loc_alert_en_shadowed_1_we & loc_alert_regwen_1_qs;
Tests: T1 T2 T3
11618 prim_subreg_shadow #(
11619 .DW (1),
11620 .SwAccess(prim_subreg_pkg::SwAccessRW),
11621 .RESVAL (1'h0),
11622 .Mubi (1'b0)
11623 ) u_loc_alert_en_shadowed_1 (
11624 .clk_i (clk_i),
11625 .rst_ni (rst_ni),
11626 .rst_shadowed_ni (rst_shadowed_ni),
11627
11628 // from register interface
11629 .re (loc_alert_en_shadowed_1_re),
11630 .we (loc_alert_en_shadowed_1_gated_we),
11631 .wd (loc_alert_en_shadowed_1_wd),
11632
11633 // from internal hardware
11634 .de (1'b0),
11635 .d ('0),
11636
11637 // to internal hardware
11638 .qe (),
11639 .q (reg2hw.loc_alert_en_shadowed[1].q),
11640 .ds (),
11641
11642 // to register interface (read)
11643 .qs (loc_alert_en_shadowed_1_qs),
11644
11645 // Shadow register phase. Relevant for hwext only.
11646 .phase (),
11647
11648 // Shadow register error conditions
11649 .err_update (loc_alert_en_shadowed_1_update_err),
11650 .err_storage (loc_alert_en_shadowed_1_storage_err)
11651 );
11652
11653
11654 // Subregister 2 of Multireg loc_alert_en_shadowed
11655 // R[loc_alert_en_shadowed_2]: V(False)
11656 // Create REGWEN-gated WE signal
11657 logic loc_alert_en_shadowed_2_gated_we;
11658 1/1 assign loc_alert_en_shadowed_2_gated_we = loc_alert_en_shadowed_2_we & loc_alert_regwen_2_qs;
Tests: T1 T2 T3
11659 prim_subreg_shadow #(
11660 .DW (1),
11661 .SwAccess(prim_subreg_pkg::SwAccessRW),
11662 .RESVAL (1'h0),
11663 .Mubi (1'b0)
11664 ) u_loc_alert_en_shadowed_2 (
11665 .clk_i (clk_i),
11666 .rst_ni (rst_ni),
11667 .rst_shadowed_ni (rst_shadowed_ni),
11668
11669 // from register interface
11670 .re (loc_alert_en_shadowed_2_re),
11671 .we (loc_alert_en_shadowed_2_gated_we),
11672 .wd (loc_alert_en_shadowed_2_wd),
11673
11674 // from internal hardware
11675 .de (1'b0),
11676 .d ('0),
11677
11678 // to internal hardware
11679 .qe (),
11680 .q (reg2hw.loc_alert_en_shadowed[2].q),
11681 .ds (),
11682
11683 // to register interface (read)
11684 .qs (loc_alert_en_shadowed_2_qs),
11685
11686 // Shadow register phase. Relevant for hwext only.
11687 .phase (),
11688
11689 // Shadow register error conditions
11690 .err_update (loc_alert_en_shadowed_2_update_err),
11691 .err_storage (loc_alert_en_shadowed_2_storage_err)
11692 );
11693
11694
11695 // Subregister 3 of Multireg loc_alert_en_shadowed
11696 // R[loc_alert_en_shadowed_3]: V(False)
11697 // Create REGWEN-gated WE signal
11698 logic loc_alert_en_shadowed_3_gated_we;
11699 1/1 assign loc_alert_en_shadowed_3_gated_we = loc_alert_en_shadowed_3_we & loc_alert_regwen_3_qs;
Tests: T1 T2 T3
11700 prim_subreg_shadow #(
11701 .DW (1),
11702 .SwAccess(prim_subreg_pkg::SwAccessRW),
11703 .RESVAL (1'h0),
11704 .Mubi (1'b0)
11705 ) u_loc_alert_en_shadowed_3 (
11706 .clk_i (clk_i),
11707 .rst_ni (rst_ni),
11708 .rst_shadowed_ni (rst_shadowed_ni),
11709
11710 // from register interface
11711 .re (loc_alert_en_shadowed_3_re),
11712 .we (loc_alert_en_shadowed_3_gated_we),
11713 .wd (loc_alert_en_shadowed_3_wd),
11714
11715 // from internal hardware
11716 .de (1'b0),
11717 .d ('0),
11718
11719 // to internal hardware
11720 .qe (),
11721 .q (reg2hw.loc_alert_en_shadowed[3].q),
11722 .ds (),
11723
11724 // to register interface (read)
11725 .qs (loc_alert_en_shadowed_3_qs),
11726
11727 // Shadow register phase. Relevant for hwext only.
11728 .phase (),
11729
11730 // Shadow register error conditions
11731 .err_update (loc_alert_en_shadowed_3_update_err),
11732 .err_storage (loc_alert_en_shadowed_3_storage_err)
11733 );
11734
11735
11736 // Subregister 4 of Multireg loc_alert_en_shadowed
11737 // R[loc_alert_en_shadowed_4]: V(False)
11738 // Create REGWEN-gated WE signal
11739 logic loc_alert_en_shadowed_4_gated_we;
11740 1/1 assign loc_alert_en_shadowed_4_gated_we = loc_alert_en_shadowed_4_we & loc_alert_regwen_4_qs;
Tests: T1 T2 T3
11741 prim_subreg_shadow #(
11742 .DW (1),
11743 .SwAccess(prim_subreg_pkg::SwAccessRW),
11744 .RESVAL (1'h0),
11745 .Mubi (1'b0)
11746 ) u_loc_alert_en_shadowed_4 (
11747 .clk_i (clk_i),
11748 .rst_ni (rst_ni),
11749 .rst_shadowed_ni (rst_shadowed_ni),
11750
11751 // from register interface
11752 .re (loc_alert_en_shadowed_4_re),
11753 .we (loc_alert_en_shadowed_4_gated_we),
11754 .wd (loc_alert_en_shadowed_4_wd),
11755
11756 // from internal hardware
11757 .de (1'b0),
11758 .d ('0),
11759
11760 // to internal hardware
11761 .qe (),
11762 .q (reg2hw.loc_alert_en_shadowed[4].q),
11763 .ds (),
11764
11765 // to register interface (read)
11766 .qs (loc_alert_en_shadowed_4_qs),
11767
11768 // Shadow register phase. Relevant for hwext only.
11769 .phase (),
11770
11771 // Shadow register error conditions
11772 .err_update (loc_alert_en_shadowed_4_update_err),
11773 .err_storage (loc_alert_en_shadowed_4_storage_err)
11774 );
11775
11776
11777 // Subregister 5 of Multireg loc_alert_en_shadowed
11778 // R[loc_alert_en_shadowed_5]: V(False)
11779 // Create REGWEN-gated WE signal
11780 logic loc_alert_en_shadowed_5_gated_we;
11781 1/1 assign loc_alert_en_shadowed_5_gated_we = loc_alert_en_shadowed_5_we & loc_alert_regwen_5_qs;
Tests: T1 T2 T3
11782 prim_subreg_shadow #(
11783 .DW (1),
11784 .SwAccess(prim_subreg_pkg::SwAccessRW),
11785 .RESVAL (1'h0),
11786 .Mubi (1'b0)
11787 ) u_loc_alert_en_shadowed_5 (
11788 .clk_i (clk_i),
11789 .rst_ni (rst_ni),
11790 .rst_shadowed_ni (rst_shadowed_ni),
11791
11792 // from register interface
11793 .re (loc_alert_en_shadowed_5_re),
11794 .we (loc_alert_en_shadowed_5_gated_we),
11795 .wd (loc_alert_en_shadowed_5_wd),
11796
11797 // from internal hardware
11798 .de (1'b0),
11799 .d ('0),
11800
11801 // to internal hardware
11802 .qe (),
11803 .q (reg2hw.loc_alert_en_shadowed[5].q),
11804 .ds (),
11805
11806 // to register interface (read)
11807 .qs (loc_alert_en_shadowed_5_qs),
11808
11809 // Shadow register phase. Relevant for hwext only.
11810 .phase (),
11811
11812 // Shadow register error conditions
11813 .err_update (loc_alert_en_shadowed_5_update_err),
11814 .err_storage (loc_alert_en_shadowed_5_storage_err)
11815 );
11816
11817
11818 // Subregister 6 of Multireg loc_alert_en_shadowed
11819 // R[loc_alert_en_shadowed_6]: V(False)
11820 // Create REGWEN-gated WE signal
11821 logic loc_alert_en_shadowed_6_gated_we;
11822 1/1 assign loc_alert_en_shadowed_6_gated_we = loc_alert_en_shadowed_6_we & loc_alert_regwen_6_qs;
Tests: T1 T2 T3
11823 prim_subreg_shadow #(
11824 .DW (1),
11825 .SwAccess(prim_subreg_pkg::SwAccessRW),
11826 .RESVAL (1'h0),
11827 .Mubi (1'b0)
11828 ) u_loc_alert_en_shadowed_6 (
11829 .clk_i (clk_i),
11830 .rst_ni (rst_ni),
11831 .rst_shadowed_ni (rst_shadowed_ni),
11832
11833 // from register interface
11834 .re (loc_alert_en_shadowed_6_re),
11835 .we (loc_alert_en_shadowed_6_gated_we),
11836 .wd (loc_alert_en_shadowed_6_wd),
11837
11838 // from internal hardware
11839 .de (1'b0),
11840 .d ('0),
11841
11842 // to internal hardware
11843 .qe (),
11844 .q (reg2hw.loc_alert_en_shadowed[6].q),
11845 .ds (),
11846
11847 // to register interface (read)
11848 .qs (loc_alert_en_shadowed_6_qs),
11849
11850 // Shadow register phase. Relevant for hwext only.
11851 .phase (),
11852
11853 // Shadow register error conditions
11854 .err_update (loc_alert_en_shadowed_6_update_err),
11855 .err_storage (loc_alert_en_shadowed_6_storage_err)
11856 );
11857
11858
11859 // Subregister 0 of Multireg loc_alert_class_shadowed
11860 // R[loc_alert_class_shadowed_0]: V(False)
11861 // Create REGWEN-gated WE signal
11862 logic loc_alert_class_shadowed_0_gated_we;
11863 1/1 assign loc_alert_class_shadowed_0_gated_we =
Tests: T1 T2 T3
11864 loc_alert_class_shadowed_0_we & loc_alert_regwen_0_qs;
11865 prim_subreg_shadow #(
11866 .DW (2),
11867 .SwAccess(prim_subreg_pkg::SwAccessRW),
11868 .RESVAL (2'h0),
11869 .Mubi (1'b0)
11870 ) u_loc_alert_class_shadowed_0 (
11871 .clk_i (clk_i),
11872 .rst_ni (rst_ni),
11873 .rst_shadowed_ni (rst_shadowed_ni),
11874
11875 // from register interface
11876 .re (loc_alert_class_shadowed_0_re),
11877 .we (loc_alert_class_shadowed_0_gated_we),
11878 .wd (loc_alert_class_shadowed_0_wd),
11879
11880 // from internal hardware
11881 .de (1'b0),
11882 .d ('0),
11883
11884 // to internal hardware
11885 .qe (),
11886 .q (reg2hw.loc_alert_class_shadowed[0].q),
11887 .ds (),
11888
11889 // to register interface (read)
11890 .qs (loc_alert_class_shadowed_0_qs),
11891
11892 // Shadow register phase. Relevant for hwext only.
11893 .phase (),
11894
11895 // Shadow register error conditions
11896 .err_update (loc_alert_class_shadowed_0_update_err),
11897 .err_storage (loc_alert_class_shadowed_0_storage_err)
11898 );
11899
11900
11901 // Subregister 1 of Multireg loc_alert_class_shadowed
11902 // R[loc_alert_class_shadowed_1]: V(False)
11903 // Create REGWEN-gated WE signal
11904 logic loc_alert_class_shadowed_1_gated_we;
11905 1/1 assign loc_alert_class_shadowed_1_gated_we =
Tests: T1 T2 T3
11906 loc_alert_class_shadowed_1_we & loc_alert_regwen_1_qs;
11907 prim_subreg_shadow #(
11908 .DW (2),
11909 .SwAccess(prim_subreg_pkg::SwAccessRW),
11910 .RESVAL (2'h0),
11911 .Mubi (1'b0)
11912 ) u_loc_alert_class_shadowed_1 (
11913 .clk_i (clk_i),
11914 .rst_ni (rst_ni),
11915 .rst_shadowed_ni (rst_shadowed_ni),
11916
11917 // from register interface
11918 .re (loc_alert_class_shadowed_1_re),
11919 .we (loc_alert_class_shadowed_1_gated_we),
11920 .wd (loc_alert_class_shadowed_1_wd),
11921
11922 // from internal hardware
11923 .de (1'b0),
11924 .d ('0),
11925
11926 // to internal hardware
11927 .qe (),
11928 .q (reg2hw.loc_alert_class_shadowed[1].q),
11929 .ds (),
11930
11931 // to register interface (read)
11932 .qs (loc_alert_class_shadowed_1_qs),
11933
11934 // Shadow register phase. Relevant for hwext only.
11935 .phase (),
11936
11937 // Shadow register error conditions
11938 .err_update (loc_alert_class_shadowed_1_update_err),
11939 .err_storage (loc_alert_class_shadowed_1_storage_err)
11940 );
11941
11942
11943 // Subregister 2 of Multireg loc_alert_class_shadowed
11944 // R[loc_alert_class_shadowed_2]: V(False)
11945 // Create REGWEN-gated WE signal
11946 logic loc_alert_class_shadowed_2_gated_we;
11947 1/1 assign loc_alert_class_shadowed_2_gated_we =
Tests: T1 T2 T3
11948 loc_alert_class_shadowed_2_we & loc_alert_regwen_2_qs;
11949 prim_subreg_shadow #(
11950 .DW (2),
11951 .SwAccess(prim_subreg_pkg::SwAccessRW),
11952 .RESVAL (2'h0),
11953 .Mubi (1'b0)
11954 ) u_loc_alert_class_shadowed_2 (
11955 .clk_i (clk_i),
11956 .rst_ni (rst_ni),
11957 .rst_shadowed_ni (rst_shadowed_ni),
11958
11959 // from register interface
11960 .re (loc_alert_class_shadowed_2_re),
11961 .we (loc_alert_class_shadowed_2_gated_we),
11962 .wd (loc_alert_class_shadowed_2_wd),
11963
11964 // from internal hardware
11965 .de (1'b0),
11966 .d ('0),
11967
11968 // to internal hardware
11969 .qe (),
11970 .q (reg2hw.loc_alert_class_shadowed[2].q),
11971 .ds (),
11972
11973 // to register interface (read)
11974 .qs (loc_alert_class_shadowed_2_qs),
11975
11976 // Shadow register phase. Relevant for hwext only.
11977 .phase (),
11978
11979 // Shadow register error conditions
11980 .err_update (loc_alert_class_shadowed_2_update_err),
11981 .err_storage (loc_alert_class_shadowed_2_storage_err)
11982 );
11983
11984
11985 // Subregister 3 of Multireg loc_alert_class_shadowed
11986 // R[loc_alert_class_shadowed_3]: V(False)
11987 // Create REGWEN-gated WE signal
11988 logic loc_alert_class_shadowed_3_gated_we;
11989 1/1 assign loc_alert_class_shadowed_3_gated_we =
Tests: T1 T2 T3
11990 loc_alert_class_shadowed_3_we & loc_alert_regwen_3_qs;
11991 prim_subreg_shadow #(
11992 .DW (2),
11993 .SwAccess(prim_subreg_pkg::SwAccessRW),
11994 .RESVAL (2'h0),
11995 .Mubi (1'b0)
11996 ) u_loc_alert_class_shadowed_3 (
11997 .clk_i (clk_i),
11998 .rst_ni (rst_ni),
11999 .rst_shadowed_ni (rst_shadowed_ni),
12000
12001 // from register interface
12002 .re (loc_alert_class_shadowed_3_re),
12003 .we (loc_alert_class_shadowed_3_gated_we),
12004 .wd (loc_alert_class_shadowed_3_wd),
12005
12006 // from internal hardware
12007 .de (1'b0),
12008 .d ('0),
12009
12010 // to internal hardware
12011 .qe (),
12012 .q (reg2hw.loc_alert_class_shadowed[3].q),
12013 .ds (),
12014
12015 // to register interface (read)
12016 .qs (loc_alert_class_shadowed_3_qs),
12017
12018 // Shadow register phase. Relevant for hwext only.
12019 .phase (),
12020
12021 // Shadow register error conditions
12022 .err_update (loc_alert_class_shadowed_3_update_err),
12023 .err_storage (loc_alert_class_shadowed_3_storage_err)
12024 );
12025
12026
12027 // Subregister 4 of Multireg loc_alert_class_shadowed
12028 // R[loc_alert_class_shadowed_4]: V(False)
12029 // Create REGWEN-gated WE signal
12030 logic loc_alert_class_shadowed_4_gated_we;
12031 1/1 assign loc_alert_class_shadowed_4_gated_we =
Tests: T1 T2 T3
12032 loc_alert_class_shadowed_4_we & loc_alert_regwen_4_qs;
12033 prim_subreg_shadow #(
12034 .DW (2),
12035 .SwAccess(prim_subreg_pkg::SwAccessRW),
12036 .RESVAL (2'h0),
12037 .Mubi (1'b0)
12038 ) u_loc_alert_class_shadowed_4 (
12039 .clk_i (clk_i),
12040 .rst_ni (rst_ni),
12041 .rst_shadowed_ni (rst_shadowed_ni),
12042
12043 // from register interface
12044 .re (loc_alert_class_shadowed_4_re),
12045 .we (loc_alert_class_shadowed_4_gated_we),
12046 .wd (loc_alert_class_shadowed_4_wd),
12047
12048 // from internal hardware
12049 .de (1'b0),
12050 .d ('0),
12051
12052 // to internal hardware
12053 .qe (),
12054 .q (reg2hw.loc_alert_class_shadowed[4].q),
12055 .ds (),
12056
12057 // to register interface (read)
12058 .qs (loc_alert_class_shadowed_4_qs),
12059
12060 // Shadow register phase. Relevant for hwext only.
12061 .phase (),
12062
12063 // Shadow register error conditions
12064 .err_update (loc_alert_class_shadowed_4_update_err),
12065 .err_storage (loc_alert_class_shadowed_4_storage_err)
12066 );
12067
12068
12069 // Subregister 5 of Multireg loc_alert_class_shadowed
12070 // R[loc_alert_class_shadowed_5]: V(False)
12071 // Create REGWEN-gated WE signal
12072 logic loc_alert_class_shadowed_5_gated_we;
12073 1/1 assign loc_alert_class_shadowed_5_gated_we =
Tests: T1 T2 T3
12074 loc_alert_class_shadowed_5_we & loc_alert_regwen_5_qs;
12075 prim_subreg_shadow #(
12076 .DW (2),
12077 .SwAccess(prim_subreg_pkg::SwAccessRW),
12078 .RESVAL (2'h0),
12079 .Mubi (1'b0)
12080 ) u_loc_alert_class_shadowed_5 (
12081 .clk_i (clk_i),
12082 .rst_ni (rst_ni),
12083 .rst_shadowed_ni (rst_shadowed_ni),
12084
12085 // from register interface
12086 .re (loc_alert_class_shadowed_5_re),
12087 .we (loc_alert_class_shadowed_5_gated_we),
12088 .wd (loc_alert_class_shadowed_5_wd),
12089
12090 // from internal hardware
12091 .de (1'b0),
12092 .d ('0),
12093
12094 // to internal hardware
12095 .qe (),
12096 .q (reg2hw.loc_alert_class_shadowed[5].q),
12097 .ds (),
12098
12099 // to register interface (read)
12100 .qs (loc_alert_class_shadowed_5_qs),
12101
12102 // Shadow register phase. Relevant for hwext only.
12103 .phase (),
12104
12105 // Shadow register error conditions
12106 .err_update (loc_alert_class_shadowed_5_update_err),
12107 .err_storage (loc_alert_class_shadowed_5_storage_err)
12108 );
12109
12110
12111 // Subregister 6 of Multireg loc_alert_class_shadowed
12112 // R[loc_alert_class_shadowed_6]: V(False)
12113 // Create REGWEN-gated WE signal
12114 logic loc_alert_class_shadowed_6_gated_we;
12115 1/1 assign loc_alert_class_shadowed_6_gated_we =
Tests: T1 T2 T3
12116 loc_alert_class_shadowed_6_we & loc_alert_regwen_6_qs;
12117 prim_subreg_shadow #(
12118 .DW (2),
12119 .SwAccess(prim_subreg_pkg::SwAccessRW),
12120 .RESVAL (2'h0),
12121 .Mubi (1'b0)
12122 ) u_loc_alert_class_shadowed_6 (
12123 .clk_i (clk_i),
12124 .rst_ni (rst_ni),
12125 .rst_shadowed_ni (rst_shadowed_ni),
12126
12127 // from register interface
12128 .re (loc_alert_class_shadowed_6_re),
12129 .we (loc_alert_class_shadowed_6_gated_we),
12130 .wd (loc_alert_class_shadowed_6_wd),
12131
12132 // from internal hardware
12133 .de (1'b0),
12134 .d ('0),
12135
12136 // to internal hardware
12137 .qe (),
12138 .q (reg2hw.loc_alert_class_shadowed[6].q),
12139 .ds (),
12140
12141 // to register interface (read)
12142 .qs (loc_alert_class_shadowed_6_qs),
12143
12144 // Shadow register phase. Relevant for hwext only.
12145 .phase (),
12146
12147 // Shadow register error conditions
12148 .err_update (loc_alert_class_shadowed_6_update_err),
12149 .err_storage (loc_alert_class_shadowed_6_storage_err)
12150 );
12151
12152
12153 // Subregister 0 of Multireg loc_alert_cause
12154 // R[loc_alert_cause_0]: V(False)
12155 prim_subreg #(
12156 .DW (1),
12157 .SwAccess(prim_subreg_pkg::SwAccessW1C),
12158 .RESVAL (1'h0),
12159 .Mubi (1'b0)
12160 ) u_loc_alert_cause_0 (
12161 .clk_i (clk_i),
12162 .rst_ni (rst_ni),
12163
12164 // from register interface
12165 .we (loc_alert_cause_0_we),
12166 .wd (loc_alert_cause_0_wd),
12167
12168 // from internal hardware
12169 .de (hw2reg.loc_alert_cause[0].de),
12170 .d (hw2reg.loc_alert_cause[0].d),
12171
12172 // to internal hardware
12173 .qe (),
12174 .q (reg2hw.loc_alert_cause[0].q),
12175 .ds (),
12176
12177 // to register interface (read)
12178 .qs (loc_alert_cause_0_qs)
12179 );
12180
12181
12182 // Subregister 1 of Multireg loc_alert_cause
12183 // R[loc_alert_cause_1]: V(False)
12184 prim_subreg #(
12185 .DW (1),
12186 .SwAccess(prim_subreg_pkg::SwAccessW1C),
12187 .RESVAL (1'h0),
12188 .Mubi (1'b0)
12189 ) u_loc_alert_cause_1 (
12190 .clk_i (clk_i),
12191 .rst_ni (rst_ni),
12192
12193 // from register interface
12194 .we (loc_alert_cause_1_we),
12195 .wd (loc_alert_cause_1_wd),
12196
12197 // from internal hardware
12198 .de (hw2reg.loc_alert_cause[1].de),
12199 .d (hw2reg.loc_alert_cause[1].d),
12200
12201 // to internal hardware
12202 .qe (),
12203 .q (reg2hw.loc_alert_cause[1].q),
12204 .ds (),
12205
12206 // to register interface (read)
12207 .qs (loc_alert_cause_1_qs)
12208 );
12209
12210
12211 // Subregister 2 of Multireg loc_alert_cause
12212 // R[loc_alert_cause_2]: V(False)
12213 prim_subreg #(
12214 .DW (1),
12215 .SwAccess(prim_subreg_pkg::SwAccessW1C),
12216 .RESVAL (1'h0),
12217 .Mubi (1'b0)
12218 ) u_loc_alert_cause_2 (
12219 .clk_i (clk_i),
12220 .rst_ni (rst_ni),
12221
12222 // from register interface
12223 .we (loc_alert_cause_2_we),
12224 .wd (loc_alert_cause_2_wd),
12225
12226 // from internal hardware
12227 .de (hw2reg.loc_alert_cause[2].de),
12228 .d (hw2reg.loc_alert_cause[2].d),
12229
12230 // to internal hardware
12231 .qe (),
12232 .q (reg2hw.loc_alert_cause[2].q),
12233 .ds (),
12234
12235 // to register interface (read)
12236 .qs (loc_alert_cause_2_qs)
12237 );
12238
12239
12240 // Subregister 3 of Multireg loc_alert_cause
12241 // R[loc_alert_cause_3]: V(False)
12242 prim_subreg #(
12243 .DW (1),
12244 .SwAccess(prim_subreg_pkg::SwAccessW1C),
12245 .RESVAL (1'h0),
12246 .Mubi (1'b0)
12247 ) u_loc_alert_cause_3 (
12248 .clk_i (clk_i),
12249 .rst_ni (rst_ni),
12250
12251 // from register interface
12252 .we (loc_alert_cause_3_we),
12253 .wd (loc_alert_cause_3_wd),
12254
12255 // from internal hardware
12256 .de (hw2reg.loc_alert_cause[3].de),
12257 .d (hw2reg.loc_alert_cause[3].d),
12258
12259 // to internal hardware
12260 .qe (),
12261 .q (reg2hw.loc_alert_cause[3].q),
12262 .ds (),
12263
12264 // to register interface (read)
12265 .qs (loc_alert_cause_3_qs)
12266 );
12267
12268
12269 // Subregister 4 of Multireg loc_alert_cause
12270 // R[loc_alert_cause_4]: V(False)
12271 prim_subreg #(
12272 .DW (1),
12273 .SwAccess(prim_subreg_pkg::SwAccessW1C),
12274 .RESVAL (1'h0),
12275 .Mubi (1'b0)
12276 ) u_loc_alert_cause_4 (
12277 .clk_i (clk_i),
12278 .rst_ni (rst_ni),
12279
12280 // from register interface
12281 .we (loc_alert_cause_4_we),
12282 .wd (loc_alert_cause_4_wd),
12283
12284 // from internal hardware
12285 .de (hw2reg.loc_alert_cause[4].de),
12286 .d (hw2reg.loc_alert_cause[4].d),
12287
12288 // to internal hardware
12289 .qe (),
12290 .q (reg2hw.loc_alert_cause[4].q),
12291 .ds (),
12292
12293 // to register interface (read)
12294 .qs (loc_alert_cause_4_qs)
12295 );
12296
12297
12298 // Subregister 5 of Multireg loc_alert_cause
12299 // R[loc_alert_cause_5]: V(False)
12300 prim_subreg #(
12301 .DW (1),
12302 .SwAccess(prim_subreg_pkg::SwAccessW1C),
12303 .RESVAL (1'h0),
12304 .Mubi (1'b0)
12305 ) u_loc_alert_cause_5 (
12306 .clk_i (clk_i),
12307 .rst_ni (rst_ni),
12308
12309 // from register interface
12310 .we (loc_alert_cause_5_we),
12311 .wd (loc_alert_cause_5_wd),
12312
12313 // from internal hardware
12314 .de (hw2reg.loc_alert_cause[5].de),
12315 .d (hw2reg.loc_alert_cause[5].d),
12316
12317 // to internal hardware
12318 .qe (),
12319 .q (reg2hw.loc_alert_cause[5].q),
12320 .ds (),
12321
12322 // to register interface (read)
12323 .qs (loc_alert_cause_5_qs)
12324 );
12325
12326
12327 // Subregister 6 of Multireg loc_alert_cause
12328 // R[loc_alert_cause_6]: V(False)
12329 prim_subreg #(
12330 .DW (1),
12331 .SwAccess(prim_subreg_pkg::SwAccessW1C),
12332 .RESVAL (1'h0),
12333 .Mubi (1'b0)
12334 ) u_loc_alert_cause_6 (
12335 .clk_i (clk_i),
12336 .rst_ni (rst_ni),
12337
12338 // from register interface
12339 .we (loc_alert_cause_6_we),
12340 .wd (loc_alert_cause_6_wd),
12341
12342 // from internal hardware
12343 .de (hw2reg.loc_alert_cause[6].de),
12344 .d (hw2reg.loc_alert_cause[6].d),
12345
12346 // to internal hardware
12347 .qe (),
12348 .q (reg2hw.loc_alert_cause[6].q),
12349 .ds (),
12350
12351 // to register interface (read)
12352 .qs (loc_alert_cause_6_qs)
12353 );
12354
12355
12356 // R[classa_regwen]: V(False)
12357 prim_subreg #(
12358 .DW (1),
12359 .SwAccess(prim_subreg_pkg::SwAccessW0C),
12360 .RESVAL (1'h1),
12361 .Mubi (1'b0)
12362 ) u_classa_regwen (
12363 .clk_i (clk_i),
12364 .rst_ni (rst_ni),
12365
12366 // from register interface
12367 .we (classa_regwen_we),
12368 .wd (classa_regwen_wd),
12369
12370 // from internal hardware
12371 .de (1'b0),
12372 .d ('0),
12373
12374 // to internal hardware
12375 .qe (),
12376 .q (),
12377 .ds (),
12378
12379 // to register interface (read)
12380 .qs (classa_regwen_qs)
12381 );
12382
12383
12384 // R[classa_ctrl_shadowed]: V(False)
12385 // Create REGWEN-gated WE signal
12386 logic classa_ctrl_shadowed_gated_we;
12387 1/1 assign classa_ctrl_shadowed_gated_we = classa_ctrl_shadowed_we & classa_regwen_qs;
Tests: T1 T2 T3
12388 // F[en]: 0:0
12389 prim_subreg_shadow #(
12390 .DW (1),
12391 .SwAccess(prim_subreg_pkg::SwAccessRW),
12392 .RESVAL (1'h0),
12393 .Mubi (1'b0)
12394 ) u_classa_ctrl_shadowed_en (
12395 .clk_i (clk_i),
12396 .rst_ni (rst_ni),
12397 .rst_shadowed_ni (rst_shadowed_ni),
12398
12399 // from register interface
12400 .re (classa_ctrl_shadowed_re),
12401 .we (classa_ctrl_shadowed_gated_we),
12402 .wd (classa_ctrl_shadowed_en_wd),
12403
12404 // from internal hardware
12405 .de (1'b0),
12406 .d ('0),
12407
12408 // to internal hardware
12409 .qe (),
12410 .q (reg2hw.classa_ctrl_shadowed.en.q),
12411 .ds (),
12412
12413 // to register interface (read)
12414 .qs (classa_ctrl_shadowed_en_qs),
12415
12416 // Shadow register phase. Relevant for hwext only.
12417 .phase (),
12418
12419 // Shadow register error conditions
12420 .err_update (classa_ctrl_shadowed_en_update_err),
12421 .err_storage (classa_ctrl_shadowed_en_storage_err)
12422 );
12423
12424 // F[lock]: 1:1
12425 prim_subreg_shadow #(
12426 .DW (1),
12427 .SwAccess(prim_subreg_pkg::SwAccessRW),
12428 .RESVAL (1'h0),
12429 .Mubi (1'b0)
12430 ) u_classa_ctrl_shadowed_lock (
12431 .clk_i (clk_i),
12432 .rst_ni (rst_ni),
12433 .rst_shadowed_ni (rst_shadowed_ni),
12434
12435 // from register interface
12436 .re (classa_ctrl_shadowed_re),
12437 .we (classa_ctrl_shadowed_gated_we),
12438 .wd (classa_ctrl_shadowed_lock_wd),
12439
12440 // from internal hardware
12441 .de (1'b0),
12442 .d ('0),
12443
12444 // to internal hardware
12445 .qe (),
12446 .q (reg2hw.classa_ctrl_shadowed.lock.q),
12447 .ds (),
12448
12449 // to register interface (read)
12450 .qs (classa_ctrl_shadowed_lock_qs),
12451
12452 // Shadow register phase. Relevant for hwext only.
12453 .phase (),
12454
12455 // Shadow register error conditions
12456 .err_update (classa_ctrl_shadowed_lock_update_err),
12457 .err_storage (classa_ctrl_shadowed_lock_storage_err)
12458 );
12459
12460 // F[en_e0]: 2:2
12461 prim_subreg_shadow #(
12462 .DW (1),
12463 .SwAccess(prim_subreg_pkg::SwAccessRW),
12464 .RESVAL (1'h1),
12465 .Mubi (1'b0)
12466 ) u_classa_ctrl_shadowed_en_e0 (
12467 .clk_i (clk_i),
12468 .rst_ni (rst_ni),
12469 .rst_shadowed_ni (rst_shadowed_ni),
12470
12471 // from register interface
12472 .re (classa_ctrl_shadowed_re),
12473 .we (classa_ctrl_shadowed_gated_we),
12474 .wd (classa_ctrl_shadowed_en_e0_wd),
12475
12476 // from internal hardware
12477 .de (1'b0),
12478 .d ('0),
12479
12480 // to internal hardware
12481 .qe (),
12482 .q (reg2hw.classa_ctrl_shadowed.en_e0.q),
12483 .ds (),
12484
12485 // to register interface (read)
12486 .qs (classa_ctrl_shadowed_en_e0_qs),
12487
12488 // Shadow register phase. Relevant for hwext only.
12489 .phase (),
12490
12491 // Shadow register error conditions
12492 .err_update (classa_ctrl_shadowed_en_e0_update_err),
12493 .err_storage (classa_ctrl_shadowed_en_e0_storage_err)
12494 );
12495
12496 // F[en_e1]: 3:3
12497 prim_subreg_shadow #(
12498 .DW (1),
12499 .SwAccess(prim_subreg_pkg::SwAccessRW),
12500 .RESVAL (1'h1),
12501 .Mubi (1'b0)
12502 ) u_classa_ctrl_shadowed_en_e1 (
12503 .clk_i (clk_i),
12504 .rst_ni (rst_ni),
12505 .rst_shadowed_ni (rst_shadowed_ni),
12506
12507 // from register interface
12508 .re (classa_ctrl_shadowed_re),
12509 .we (classa_ctrl_shadowed_gated_we),
12510 .wd (classa_ctrl_shadowed_en_e1_wd),
12511
12512 // from internal hardware
12513 .de (1'b0),
12514 .d ('0),
12515
12516 // to internal hardware
12517 .qe (),
12518 .q (reg2hw.classa_ctrl_shadowed.en_e1.q),
12519 .ds (),
12520
12521 // to register interface (read)
12522 .qs (classa_ctrl_shadowed_en_e1_qs),
12523
12524 // Shadow register phase. Relevant for hwext only.
12525 .phase (),
12526
12527 // Shadow register error conditions
12528 .err_update (classa_ctrl_shadowed_en_e1_update_err),
12529 .err_storage (classa_ctrl_shadowed_en_e1_storage_err)
12530 );
12531
12532 // F[en_e2]: 4:4
12533 prim_subreg_shadow #(
12534 .DW (1),
12535 .SwAccess(prim_subreg_pkg::SwAccessRW),
12536 .RESVAL (1'h1),
12537 .Mubi (1'b0)
12538 ) u_classa_ctrl_shadowed_en_e2 (
12539 .clk_i (clk_i),
12540 .rst_ni (rst_ni),
12541 .rst_shadowed_ni (rst_shadowed_ni),
12542
12543 // from register interface
12544 .re (classa_ctrl_shadowed_re),
12545 .we (classa_ctrl_shadowed_gated_we),
12546 .wd (classa_ctrl_shadowed_en_e2_wd),
12547
12548 // from internal hardware
12549 .de (1'b0),
12550 .d ('0),
12551
12552 // to internal hardware
12553 .qe (),
12554 .q (reg2hw.classa_ctrl_shadowed.en_e2.q),
12555 .ds (),
12556
12557 // to register interface (read)
12558 .qs (classa_ctrl_shadowed_en_e2_qs),
12559
12560 // Shadow register phase. Relevant for hwext only.
12561 .phase (),
12562
12563 // Shadow register error conditions
12564 .err_update (classa_ctrl_shadowed_en_e2_update_err),
12565 .err_storage (classa_ctrl_shadowed_en_e2_storage_err)
12566 );
12567
12568 // F[en_e3]: 5:5
12569 prim_subreg_shadow #(
12570 .DW (1),
12571 .SwAccess(prim_subreg_pkg::SwAccessRW),
12572 .RESVAL (1'h1),
12573 .Mubi (1'b0)
12574 ) u_classa_ctrl_shadowed_en_e3 (
12575 .clk_i (clk_i),
12576 .rst_ni (rst_ni),
12577 .rst_shadowed_ni (rst_shadowed_ni),
12578
12579 // from register interface
12580 .re (classa_ctrl_shadowed_re),
12581 .we (classa_ctrl_shadowed_gated_we),
12582 .wd (classa_ctrl_shadowed_en_e3_wd),
12583
12584 // from internal hardware
12585 .de (1'b0),
12586 .d ('0),
12587
12588 // to internal hardware
12589 .qe (),
12590 .q (reg2hw.classa_ctrl_shadowed.en_e3.q),
12591 .ds (),
12592
12593 // to register interface (read)
12594 .qs (classa_ctrl_shadowed_en_e3_qs),
12595
12596 // Shadow register phase. Relevant for hwext only.
12597 .phase (),
12598
12599 // Shadow register error conditions
12600 .err_update (classa_ctrl_shadowed_en_e3_update_err),
12601 .err_storage (classa_ctrl_shadowed_en_e3_storage_err)
12602 );
12603
12604 // F[map_e0]: 7:6
12605 prim_subreg_shadow #(
12606 .DW (2),
12607 .SwAccess(prim_subreg_pkg::SwAccessRW),
12608 .RESVAL (2'h0),
12609 .Mubi (1'b0)
12610 ) u_classa_ctrl_shadowed_map_e0 (
12611 .clk_i (clk_i),
12612 .rst_ni (rst_ni),
12613 .rst_shadowed_ni (rst_shadowed_ni),
12614
12615 // from register interface
12616 .re (classa_ctrl_shadowed_re),
12617 .we (classa_ctrl_shadowed_gated_we),
12618 .wd (classa_ctrl_shadowed_map_e0_wd),
12619
12620 // from internal hardware
12621 .de (1'b0),
12622 .d ('0),
12623
12624 // to internal hardware
12625 .qe (),
12626 .q (reg2hw.classa_ctrl_shadowed.map_e0.q),
12627 .ds (),
12628
12629 // to register interface (read)
12630 .qs (classa_ctrl_shadowed_map_e0_qs),
12631
12632 // Shadow register phase. Relevant for hwext only.
12633 .phase (),
12634
12635 // Shadow register error conditions
12636 .err_update (classa_ctrl_shadowed_map_e0_update_err),
12637 .err_storage (classa_ctrl_shadowed_map_e0_storage_err)
12638 );
12639
12640 // F[map_e1]: 9:8
12641 prim_subreg_shadow #(
12642 .DW (2),
12643 .SwAccess(prim_subreg_pkg::SwAccessRW),
12644 .RESVAL (2'h1),
12645 .Mubi (1'b0)
12646 ) u_classa_ctrl_shadowed_map_e1 (
12647 .clk_i (clk_i),
12648 .rst_ni (rst_ni),
12649 .rst_shadowed_ni (rst_shadowed_ni),
12650
12651 // from register interface
12652 .re (classa_ctrl_shadowed_re),
12653 .we (classa_ctrl_shadowed_gated_we),
12654 .wd (classa_ctrl_shadowed_map_e1_wd),
12655
12656 // from internal hardware
12657 .de (1'b0),
12658 .d ('0),
12659
12660 // to internal hardware
12661 .qe (),
12662 .q (reg2hw.classa_ctrl_shadowed.map_e1.q),
12663 .ds (),
12664
12665 // to register interface (read)
12666 .qs (classa_ctrl_shadowed_map_e1_qs),
12667
12668 // Shadow register phase. Relevant for hwext only.
12669 .phase (),
12670
12671 // Shadow register error conditions
12672 .err_update (classa_ctrl_shadowed_map_e1_update_err),
12673 .err_storage (classa_ctrl_shadowed_map_e1_storage_err)
12674 );
12675
12676 // F[map_e2]: 11:10
12677 prim_subreg_shadow #(
12678 .DW (2),
12679 .SwAccess(prim_subreg_pkg::SwAccessRW),
12680 .RESVAL (2'h2),
12681 .Mubi (1'b0)
12682 ) u_classa_ctrl_shadowed_map_e2 (
12683 .clk_i (clk_i),
12684 .rst_ni (rst_ni),
12685 .rst_shadowed_ni (rst_shadowed_ni),
12686
12687 // from register interface
12688 .re (classa_ctrl_shadowed_re),
12689 .we (classa_ctrl_shadowed_gated_we),
12690 .wd (classa_ctrl_shadowed_map_e2_wd),
12691
12692 // from internal hardware
12693 .de (1'b0),
12694 .d ('0),
12695
12696 // to internal hardware
12697 .qe (),
12698 .q (reg2hw.classa_ctrl_shadowed.map_e2.q),
12699 .ds (),
12700
12701 // to register interface (read)
12702 .qs (classa_ctrl_shadowed_map_e2_qs),
12703
12704 // Shadow register phase. Relevant for hwext only.
12705 .phase (),
12706
12707 // Shadow register error conditions
12708 .err_update (classa_ctrl_shadowed_map_e2_update_err),
12709 .err_storage (classa_ctrl_shadowed_map_e2_storage_err)
12710 );
12711
12712 // F[map_e3]: 13:12
12713 prim_subreg_shadow #(
12714 .DW (2),
12715 .SwAccess(prim_subreg_pkg::SwAccessRW),
12716 .RESVAL (2'h3),
12717 .Mubi (1'b0)
12718 ) u_classa_ctrl_shadowed_map_e3 (
12719 .clk_i (clk_i),
12720 .rst_ni (rst_ni),
12721 .rst_shadowed_ni (rst_shadowed_ni),
12722
12723 // from register interface
12724 .re (classa_ctrl_shadowed_re),
12725 .we (classa_ctrl_shadowed_gated_we),
12726 .wd (classa_ctrl_shadowed_map_e3_wd),
12727
12728 // from internal hardware
12729 .de (1'b0),
12730 .d ('0),
12731
12732 // to internal hardware
12733 .qe (),
12734 .q (reg2hw.classa_ctrl_shadowed.map_e3.q),
12735 .ds (),
12736
12737 // to register interface (read)
12738 .qs (classa_ctrl_shadowed_map_e3_qs),
12739
12740 // Shadow register phase. Relevant for hwext only.
12741 .phase (),
12742
12743 // Shadow register error conditions
12744 .err_update (classa_ctrl_shadowed_map_e3_update_err),
12745 .err_storage (classa_ctrl_shadowed_map_e3_storage_err)
12746 );
12747
12748
12749 // R[classa_clr_regwen]: V(False)
12750 prim_subreg #(
12751 .DW (1),
12752 .SwAccess(prim_subreg_pkg::SwAccessW0C),
12753 .RESVAL (1'h1),
12754 .Mubi (1'b0)
12755 ) u_classa_clr_regwen (
12756 .clk_i (clk_i),
12757 .rst_ni (rst_ni),
12758
12759 // from register interface
12760 .we (classa_clr_regwen_we),
12761 .wd (classa_clr_regwen_wd),
12762
12763 // from internal hardware
12764 .de (hw2reg.classa_clr_regwen.de),
12765 .d (hw2reg.classa_clr_regwen.d),
12766
12767 // to internal hardware
12768 .qe (),
12769 .q (),
12770 .ds (),
12771
12772 // to register interface (read)
12773 .qs (classa_clr_regwen_qs)
12774 );
12775
12776
12777 // R[classa_clr_shadowed]: V(False)
12778 logic classa_clr_shadowed_qe;
12779 logic [0:0] classa_clr_shadowed_flds_we;
12780 prim_flop #(
12781 .Width(1),
12782 .ResetValue(0)
12783 ) u_classa_clr_shadowed0_qe (
12784 .clk_i(clk_i),
12785 .rst_ni(rst_ni),
12786 .d_i(&classa_clr_shadowed_flds_we),
12787 .q_o(classa_clr_shadowed_qe)
12788 );
12789 // Create REGWEN-gated WE signal
12790 logic classa_clr_shadowed_gated_we;
12791 1/1 assign classa_clr_shadowed_gated_we = classa_clr_shadowed_we & classa_clr_regwen_qs;
Tests: T1 T2 T3
12792 prim_subreg_shadow #(
12793 .DW (1),
12794 .SwAccess(prim_subreg_pkg::SwAccessRW),
12795 .RESVAL (1'h0),
12796 .Mubi (1'b0)
12797 ) u_classa_clr_shadowed (
12798 .clk_i (clk_i),
12799 .rst_ni (rst_ni),
12800 .rst_shadowed_ni (rst_shadowed_ni),
12801
12802 // from register interface
12803 .re (classa_clr_shadowed_re),
12804 .we (classa_clr_shadowed_gated_we),
12805 .wd (classa_clr_shadowed_wd),
12806
12807 // from internal hardware
12808 .de (1'b0),
12809 .d ('0),
12810
12811 // to internal hardware
12812 .qe (classa_clr_shadowed_flds_we[0]),
12813 .q (reg2hw.classa_clr_shadowed.q),
12814 .ds (),
12815
12816 // to register interface (read)
12817 .qs (classa_clr_shadowed_qs),
12818
12819 // Shadow register phase. Relevant for hwext only.
12820 .phase (),
12821
12822 // Shadow register error conditions
12823 .err_update (classa_clr_shadowed_update_err),
12824 .err_storage (classa_clr_shadowed_storage_err)
12825 );
12826 1/1 assign reg2hw.classa_clr_shadowed.qe = classa_clr_shadowed_qe;
Tests: T1 T2 T3
12827
12828
12829 // R[classa_accum_cnt]: V(True)
12830 prim_subreg_ext #(
12831 .DW (16)
12832 ) u_classa_accum_cnt (
12833 .re (classa_accum_cnt_re),
12834 .we (1'b0),
12835 .wd ('0),
12836 .d (hw2reg.classa_accum_cnt.d),
12837 .qre (),
12838 .qe (),
12839 .q (),
12840 .ds (),
12841 .qs (classa_accum_cnt_qs)
12842 );
12843
12844
12845 // R[classa_accum_thresh_shadowed]: V(False)
12846 // Create REGWEN-gated WE signal
12847 logic classa_accum_thresh_shadowed_gated_we;
12848 1/1 assign classa_accum_thresh_shadowed_gated_we = classa_accum_thresh_shadowed_we & classa_regwen_qs;
Tests: T1 T2 T3
12849 prim_subreg_shadow #(
12850 .DW (16),
12851 .SwAccess(prim_subreg_pkg::SwAccessRW),
12852 .RESVAL (16'h0),
12853 .Mubi (1'b0)
12854 ) u_classa_accum_thresh_shadowed (
12855 .clk_i (clk_i),
12856 .rst_ni (rst_ni),
12857 .rst_shadowed_ni (rst_shadowed_ni),
12858
12859 // from register interface
12860 .re (classa_accum_thresh_shadowed_re),
12861 .we (classa_accum_thresh_shadowed_gated_we),
12862 .wd (classa_accum_thresh_shadowed_wd),
12863
12864 // from internal hardware
12865 .de (1'b0),
12866 .d ('0),
12867
12868 // to internal hardware
12869 .qe (),
12870 .q (reg2hw.classa_accum_thresh_shadowed.q),
12871 .ds (),
12872
12873 // to register interface (read)
12874 .qs (classa_accum_thresh_shadowed_qs),
12875
12876 // Shadow register phase. Relevant for hwext only.
12877 .phase (),
12878
12879 // Shadow register error conditions
12880 .err_update (classa_accum_thresh_shadowed_update_err),
12881 .err_storage (classa_accum_thresh_shadowed_storage_err)
12882 );
12883
12884
12885 // R[classa_timeout_cyc_shadowed]: V(False)
12886 // Create REGWEN-gated WE signal
12887 logic classa_timeout_cyc_shadowed_gated_we;
12888 1/1 assign classa_timeout_cyc_shadowed_gated_we = classa_timeout_cyc_shadowed_we & classa_regwen_qs;
Tests: T1 T2 T3
12889 prim_subreg_shadow #(
12890 .DW (32),
12891 .SwAccess(prim_subreg_pkg::SwAccessRW),
12892 .RESVAL (32'h0),
12893 .Mubi (1'b0)
12894 ) u_classa_timeout_cyc_shadowed (
12895 .clk_i (clk_i),
12896 .rst_ni (rst_ni),
12897 .rst_shadowed_ni (rst_shadowed_ni),
12898
12899 // from register interface
12900 .re (classa_timeout_cyc_shadowed_re),
12901 .we (classa_timeout_cyc_shadowed_gated_we),
12902 .wd (classa_timeout_cyc_shadowed_wd),
12903
12904 // from internal hardware
12905 .de (1'b0),
12906 .d ('0),
12907
12908 // to internal hardware
12909 .qe (),
12910 .q (reg2hw.classa_timeout_cyc_shadowed.q),
12911 .ds (),
12912
12913 // to register interface (read)
12914 .qs (classa_timeout_cyc_shadowed_qs),
12915
12916 // Shadow register phase. Relevant for hwext only.
12917 .phase (),
12918
12919 // Shadow register error conditions
12920 .err_update (classa_timeout_cyc_shadowed_update_err),
12921 .err_storage (classa_timeout_cyc_shadowed_storage_err)
12922 );
12923
12924
12925 // R[classa_crashdump_trigger_shadowed]: V(False)
12926 // Create REGWEN-gated WE signal
12927 logic classa_crashdump_trigger_shadowed_gated_we;
12928 1/1 assign classa_crashdump_trigger_shadowed_gated_we =
Tests: T1 T2 T3
12929 classa_crashdump_trigger_shadowed_we & classa_regwen_qs;
12930 prim_subreg_shadow #(
12931 .DW (2),
12932 .SwAccess(prim_subreg_pkg::SwAccessRW),
12933 .RESVAL (2'h0),
12934 .Mubi (1'b0)
12935 ) u_classa_crashdump_trigger_shadowed (
12936 .clk_i (clk_i),
12937 .rst_ni (rst_ni),
12938 .rst_shadowed_ni (rst_shadowed_ni),
12939
12940 // from register interface
12941 .re (classa_crashdump_trigger_shadowed_re),
12942 .we (classa_crashdump_trigger_shadowed_gated_we),
12943 .wd (classa_crashdump_trigger_shadowed_wd),
12944
12945 // from internal hardware
12946 .de (1'b0),
12947 .d ('0),
12948
12949 // to internal hardware
12950 .qe (),
12951 .q (reg2hw.classa_crashdump_trigger_shadowed.q),
12952 .ds (),
12953
12954 // to register interface (read)
12955 .qs (classa_crashdump_trigger_shadowed_qs),
12956
12957 // Shadow register phase. Relevant for hwext only.
12958 .phase (),
12959
12960 // Shadow register error conditions
12961 .err_update (classa_crashdump_trigger_shadowed_update_err),
12962 .err_storage (classa_crashdump_trigger_shadowed_storage_err)
12963 );
12964
12965
12966 // R[classa_phase0_cyc_shadowed]: V(False)
12967 // Create REGWEN-gated WE signal
12968 logic classa_phase0_cyc_shadowed_gated_we;
12969 1/1 assign classa_phase0_cyc_shadowed_gated_we = classa_phase0_cyc_shadowed_we & classa_regwen_qs;
Tests: T1 T2 T3
12970 prim_subreg_shadow #(
12971 .DW (32),
12972 .SwAccess(prim_subreg_pkg::SwAccessRW),
12973 .RESVAL (32'h0),
12974 .Mubi (1'b0)
12975 ) u_classa_phase0_cyc_shadowed (
12976 .clk_i (clk_i),
12977 .rst_ni (rst_ni),
12978 .rst_shadowed_ni (rst_shadowed_ni),
12979
12980 // from register interface
12981 .re (classa_phase0_cyc_shadowed_re),
12982 .we (classa_phase0_cyc_shadowed_gated_we),
12983 .wd (classa_phase0_cyc_shadowed_wd),
12984
12985 // from internal hardware
12986 .de (1'b0),
12987 .d ('0),
12988
12989 // to internal hardware
12990 .qe (),
12991 .q (reg2hw.classa_phase0_cyc_shadowed.q),
12992 .ds (),
12993
12994 // to register interface (read)
12995 .qs (classa_phase0_cyc_shadowed_qs),
12996
12997 // Shadow register phase. Relevant for hwext only.
12998 .phase (),
12999
13000 // Shadow register error conditions
13001 .err_update (classa_phase0_cyc_shadowed_update_err),
13002 .err_storage (classa_phase0_cyc_shadowed_storage_err)
13003 );
13004
13005
13006 // R[classa_phase1_cyc_shadowed]: V(False)
13007 // Create REGWEN-gated WE signal
13008 logic classa_phase1_cyc_shadowed_gated_we;
13009 1/1 assign classa_phase1_cyc_shadowed_gated_we = classa_phase1_cyc_shadowed_we & classa_regwen_qs;
Tests: T1 T2 T3
13010 prim_subreg_shadow #(
13011 .DW (32),
13012 .SwAccess(prim_subreg_pkg::SwAccessRW),
13013 .RESVAL (32'h0),
13014 .Mubi (1'b0)
13015 ) u_classa_phase1_cyc_shadowed (
13016 .clk_i (clk_i),
13017 .rst_ni (rst_ni),
13018 .rst_shadowed_ni (rst_shadowed_ni),
13019
13020 // from register interface
13021 .re (classa_phase1_cyc_shadowed_re),
13022 .we (classa_phase1_cyc_shadowed_gated_we),
13023 .wd (classa_phase1_cyc_shadowed_wd),
13024
13025 // from internal hardware
13026 .de (1'b0),
13027 .d ('0),
13028
13029 // to internal hardware
13030 .qe (),
13031 .q (reg2hw.classa_phase1_cyc_shadowed.q),
13032 .ds (),
13033
13034 // to register interface (read)
13035 .qs (classa_phase1_cyc_shadowed_qs),
13036
13037 // Shadow register phase. Relevant for hwext only.
13038 .phase (),
13039
13040 // Shadow register error conditions
13041 .err_update (classa_phase1_cyc_shadowed_update_err),
13042 .err_storage (classa_phase1_cyc_shadowed_storage_err)
13043 );
13044
13045
13046 // R[classa_phase2_cyc_shadowed]: V(False)
13047 // Create REGWEN-gated WE signal
13048 logic classa_phase2_cyc_shadowed_gated_we;
13049 1/1 assign classa_phase2_cyc_shadowed_gated_we = classa_phase2_cyc_shadowed_we & classa_regwen_qs;
Tests: T1 T2 T3
13050 prim_subreg_shadow #(
13051 .DW (32),
13052 .SwAccess(prim_subreg_pkg::SwAccessRW),
13053 .RESVAL (32'h0),
13054 .Mubi (1'b0)
13055 ) u_classa_phase2_cyc_shadowed (
13056 .clk_i (clk_i),
13057 .rst_ni (rst_ni),
13058 .rst_shadowed_ni (rst_shadowed_ni),
13059
13060 // from register interface
13061 .re (classa_phase2_cyc_shadowed_re),
13062 .we (classa_phase2_cyc_shadowed_gated_we),
13063 .wd (classa_phase2_cyc_shadowed_wd),
13064
13065 // from internal hardware
13066 .de (1'b0),
13067 .d ('0),
13068
13069 // to internal hardware
13070 .qe (),
13071 .q (reg2hw.classa_phase2_cyc_shadowed.q),
13072 .ds (),
13073
13074 // to register interface (read)
13075 .qs (classa_phase2_cyc_shadowed_qs),
13076
13077 // Shadow register phase. Relevant for hwext only.
13078 .phase (),
13079
13080 // Shadow register error conditions
13081 .err_update (classa_phase2_cyc_shadowed_update_err),
13082 .err_storage (classa_phase2_cyc_shadowed_storage_err)
13083 );
13084
13085
13086 // R[classa_phase3_cyc_shadowed]: V(False)
13087 // Create REGWEN-gated WE signal
13088 logic classa_phase3_cyc_shadowed_gated_we;
13089 1/1 assign classa_phase3_cyc_shadowed_gated_we = classa_phase3_cyc_shadowed_we & classa_regwen_qs;
Tests: T1 T2 T3
13090 prim_subreg_shadow #(
13091 .DW (32),
13092 .SwAccess(prim_subreg_pkg::SwAccessRW),
13093 .RESVAL (32'h0),
13094 .Mubi (1'b0)
13095 ) u_classa_phase3_cyc_shadowed (
13096 .clk_i (clk_i),
13097 .rst_ni (rst_ni),
13098 .rst_shadowed_ni (rst_shadowed_ni),
13099
13100 // from register interface
13101 .re (classa_phase3_cyc_shadowed_re),
13102 .we (classa_phase3_cyc_shadowed_gated_we),
13103 .wd (classa_phase3_cyc_shadowed_wd),
13104
13105 // from internal hardware
13106 .de (1'b0),
13107 .d ('0),
13108
13109 // to internal hardware
13110 .qe (),
13111 .q (reg2hw.classa_phase3_cyc_shadowed.q),
13112 .ds (),
13113
13114 // to register interface (read)
13115 .qs (classa_phase3_cyc_shadowed_qs),
13116
13117 // Shadow register phase. Relevant for hwext only.
13118 .phase (),
13119
13120 // Shadow register error conditions
13121 .err_update (classa_phase3_cyc_shadowed_update_err),
13122 .err_storage (classa_phase3_cyc_shadowed_storage_err)
13123 );
13124
13125
13126 // R[classa_esc_cnt]: V(True)
13127 prim_subreg_ext #(
13128 .DW (32)
13129 ) u_classa_esc_cnt (
13130 .re (classa_esc_cnt_re),
13131 .we (1'b0),
13132 .wd ('0),
13133 .d (hw2reg.classa_esc_cnt.d),
13134 .qre (),
13135 .qe (),
13136 .q (),
13137 .ds (),
13138 .qs (classa_esc_cnt_qs)
13139 );
13140
13141
13142 // R[classa_state]: V(True)
13143 prim_subreg_ext #(
13144 .DW (3)
13145 ) u_classa_state (
13146 .re (classa_state_re),
13147 .we (1'b0),
13148 .wd ('0),
13149 .d (hw2reg.classa_state.d),
13150 .qre (),
13151 .qe (),
13152 .q (),
13153 .ds (),
13154 .qs (classa_state_qs)
13155 );
13156
13157
13158 // R[classb_regwen]: V(False)
13159 prim_subreg #(
13160 .DW (1),
13161 .SwAccess(prim_subreg_pkg::SwAccessW0C),
13162 .RESVAL (1'h1),
13163 .Mubi (1'b0)
13164 ) u_classb_regwen (
13165 .clk_i (clk_i),
13166 .rst_ni (rst_ni),
13167
13168 // from register interface
13169 .we (classb_regwen_we),
13170 .wd (classb_regwen_wd),
13171
13172 // from internal hardware
13173 .de (1'b0),
13174 .d ('0),
13175
13176 // to internal hardware
13177 .qe (),
13178 .q (),
13179 .ds (),
13180
13181 // to register interface (read)
13182 .qs (classb_regwen_qs)
13183 );
13184
13185
13186 // R[classb_ctrl_shadowed]: V(False)
13187 // Create REGWEN-gated WE signal
13188 logic classb_ctrl_shadowed_gated_we;
13189 1/1 assign classb_ctrl_shadowed_gated_we = classb_ctrl_shadowed_we & classb_regwen_qs;
Tests: T1 T2 T3
13190 // F[en]: 0:0
13191 prim_subreg_shadow #(
13192 .DW (1),
13193 .SwAccess(prim_subreg_pkg::SwAccessRW),
13194 .RESVAL (1'h0),
13195 .Mubi (1'b0)
13196 ) u_classb_ctrl_shadowed_en (
13197 .clk_i (clk_i),
13198 .rst_ni (rst_ni),
13199 .rst_shadowed_ni (rst_shadowed_ni),
13200
13201 // from register interface
13202 .re (classb_ctrl_shadowed_re),
13203 .we (classb_ctrl_shadowed_gated_we),
13204 .wd (classb_ctrl_shadowed_en_wd),
13205
13206 // from internal hardware
13207 .de (1'b0),
13208 .d ('0),
13209
13210 // to internal hardware
13211 .qe (),
13212 .q (reg2hw.classb_ctrl_shadowed.en.q),
13213 .ds (),
13214
13215 // to register interface (read)
13216 .qs (classb_ctrl_shadowed_en_qs),
13217
13218 // Shadow register phase. Relevant for hwext only.
13219 .phase (),
13220
13221 // Shadow register error conditions
13222 .err_update (classb_ctrl_shadowed_en_update_err),
13223 .err_storage (classb_ctrl_shadowed_en_storage_err)
13224 );
13225
13226 // F[lock]: 1:1
13227 prim_subreg_shadow #(
13228 .DW (1),
13229 .SwAccess(prim_subreg_pkg::SwAccessRW),
13230 .RESVAL (1'h0),
13231 .Mubi (1'b0)
13232 ) u_classb_ctrl_shadowed_lock (
13233 .clk_i (clk_i),
13234 .rst_ni (rst_ni),
13235 .rst_shadowed_ni (rst_shadowed_ni),
13236
13237 // from register interface
13238 .re (classb_ctrl_shadowed_re),
13239 .we (classb_ctrl_shadowed_gated_we),
13240 .wd (classb_ctrl_shadowed_lock_wd),
13241
13242 // from internal hardware
13243 .de (1'b0),
13244 .d ('0),
13245
13246 // to internal hardware
13247 .qe (),
13248 .q (reg2hw.classb_ctrl_shadowed.lock.q),
13249 .ds (),
13250
13251 // to register interface (read)
13252 .qs (classb_ctrl_shadowed_lock_qs),
13253
13254 // Shadow register phase. Relevant for hwext only.
13255 .phase (),
13256
13257 // Shadow register error conditions
13258 .err_update (classb_ctrl_shadowed_lock_update_err),
13259 .err_storage (classb_ctrl_shadowed_lock_storage_err)
13260 );
13261
13262 // F[en_e0]: 2:2
13263 prim_subreg_shadow #(
13264 .DW (1),
13265 .SwAccess(prim_subreg_pkg::SwAccessRW),
13266 .RESVAL (1'h1),
13267 .Mubi (1'b0)
13268 ) u_classb_ctrl_shadowed_en_e0 (
13269 .clk_i (clk_i),
13270 .rst_ni (rst_ni),
13271 .rst_shadowed_ni (rst_shadowed_ni),
13272
13273 // from register interface
13274 .re (classb_ctrl_shadowed_re),
13275 .we (classb_ctrl_shadowed_gated_we),
13276 .wd (classb_ctrl_shadowed_en_e0_wd),
13277
13278 // from internal hardware
13279 .de (1'b0),
13280 .d ('0),
13281
13282 // to internal hardware
13283 .qe (),
13284 .q (reg2hw.classb_ctrl_shadowed.en_e0.q),
13285 .ds (),
13286
13287 // to register interface (read)
13288 .qs (classb_ctrl_shadowed_en_e0_qs),
13289
13290 // Shadow register phase. Relevant for hwext only.
13291 .phase (),
13292
13293 // Shadow register error conditions
13294 .err_update (classb_ctrl_shadowed_en_e0_update_err),
13295 .err_storage (classb_ctrl_shadowed_en_e0_storage_err)
13296 );
13297
13298 // F[en_e1]: 3:3
13299 prim_subreg_shadow #(
13300 .DW (1),
13301 .SwAccess(prim_subreg_pkg::SwAccessRW),
13302 .RESVAL (1'h1),
13303 .Mubi (1'b0)
13304 ) u_classb_ctrl_shadowed_en_e1 (
13305 .clk_i (clk_i),
13306 .rst_ni (rst_ni),
13307 .rst_shadowed_ni (rst_shadowed_ni),
13308
13309 // from register interface
13310 .re (classb_ctrl_shadowed_re),
13311 .we (classb_ctrl_shadowed_gated_we),
13312 .wd (classb_ctrl_shadowed_en_e1_wd),
13313
13314 // from internal hardware
13315 .de (1'b0),
13316 .d ('0),
13317
13318 // to internal hardware
13319 .qe (),
13320 .q (reg2hw.classb_ctrl_shadowed.en_e1.q),
13321 .ds (),
13322
13323 // to register interface (read)
13324 .qs (classb_ctrl_shadowed_en_e1_qs),
13325
13326 // Shadow register phase. Relevant for hwext only.
13327 .phase (),
13328
13329 // Shadow register error conditions
13330 .err_update (classb_ctrl_shadowed_en_e1_update_err),
13331 .err_storage (classb_ctrl_shadowed_en_e1_storage_err)
13332 );
13333
13334 // F[en_e2]: 4:4
13335 prim_subreg_shadow #(
13336 .DW (1),
13337 .SwAccess(prim_subreg_pkg::SwAccessRW),
13338 .RESVAL (1'h1),
13339 .Mubi (1'b0)
13340 ) u_classb_ctrl_shadowed_en_e2 (
13341 .clk_i (clk_i),
13342 .rst_ni (rst_ni),
13343 .rst_shadowed_ni (rst_shadowed_ni),
13344
13345 // from register interface
13346 .re (classb_ctrl_shadowed_re),
13347 .we (classb_ctrl_shadowed_gated_we),
13348 .wd (classb_ctrl_shadowed_en_e2_wd),
13349
13350 // from internal hardware
13351 .de (1'b0),
13352 .d ('0),
13353
13354 // to internal hardware
13355 .qe (),
13356 .q (reg2hw.classb_ctrl_shadowed.en_e2.q),
13357 .ds (),
13358
13359 // to register interface (read)
13360 .qs (classb_ctrl_shadowed_en_e2_qs),
13361
13362 // Shadow register phase. Relevant for hwext only.
13363 .phase (),
13364
13365 // Shadow register error conditions
13366 .err_update (classb_ctrl_shadowed_en_e2_update_err),
13367 .err_storage (classb_ctrl_shadowed_en_e2_storage_err)
13368 );
13369
13370 // F[en_e3]: 5:5
13371 prim_subreg_shadow #(
13372 .DW (1),
13373 .SwAccess(prim_subreg_pkg::SwAccessRW),
13374 .RESVAL (1'h1),
13375 .Mubi (1'b0)
13376 ) u_classb_ctrl_shadowed_en_e3 (
13377 .clk_i (clk_i),
13378 .rst_ni (rst_ni),
13379 .rst_shadowed_ni (rst_shadowed_ni),
13380
13381 // from register interface
13382 .re (classb_ctrl_shadowed_re),
13383 .we (classb_ctrl_shadowed_gated_we),
13384 .wd (classb_ctrl_shadowed_en_e3_wd),
13385
13386 // from internal hardware
13387 .de (1'b0),
13388 .d ('0),
13389
13390 // to internal hardware
13391 .qe (),
13392 .q (reg2hw.classb_ctrl_shadowed.en_e3.q),
13393 .ds (),
13394
13395 // to register interface (read)
13396 .qs (classb_ctrl_shadowed_en_e3_qs),
13397
13398 // Shadow register phase. Relevant for hwext only.
13399 .phase (),
13400
13401 // Shadow register error conditions
13402 .err_update (classb_ctrl_shadowed_en_e3_update_err),
13403 .err_storage (classb_ctrl_shadowed_en_e3_storage_err)
13404 );
13405
13406 // F[map_e0]: 7:6
13407 prim_subreg_shadow #(
13408 .DW (2),
13409 .SwAccess(prim_subreg_pkg::SwAccessRW),
13410 .RESVAL (2'h0),
13411 .Mubi (1'b0)
13412 ) u_classb_ctrl_shadowed_map_e0 (
13413 .clk_i (clk_i),
13414 .rst_ni (rst_ni),
13415 .rst_shadowed_ni (rst_shadowed_ni),
13416
13417 // from register interface
13418 .re (classb_ctrl_shadowed_re),
13419 .we (classb_ctrl_shadowed_gated_we),
13420 .wd (classb_ctrl_shadowed_map_e0_wd),
13421
13422 // from internal hardware
13423 .de (1'b0),
13424 .d ('0),
13425
13426 // to internal hardware
13427 .qe (),
13428 .q (reg2hw.classb_ctrl_shadowed.map_e0.q),
13429 .ds (),
13430
13431 // to register interface (read)
13432 .qs (classb_ctrl_shadowed_map_e0_qs),
13433
13434 // Shadow register phase. Relevant for hwext only.
13435 .phase (),
13436
13437 // Shadow register error conditions
13438 .err_update (classb_ctrl_shadowed_map_e0_update_err),
13439 .err_storage (classb_ctrl_shadowed_map_e0_storage_err)
13440 );
13441
13442 // F[map_e1]: 9:8
13443 prim_subreg_shadow #(
13444 .DW (2),
13445 .SwAccess(prim_subreg_pkg::SwAccessRW),
13446 .RESVAL (2'h1),
13447 .Mubi (1'b0)
13448 ) u_classb_ctrl_shadowed_map_e1 (
13449 .clk_i (clk_i),
13450 .rst_ni (rst_ni),
13451 .rst_shadowed_ni (rst_shadowed_ni),
13452
13453 // from register interface
13454 .re (classb_ctrl_shadowed_re),
13455 .we (classb_ctrl_shadowed_gated_we),
13456 .wd (classb_ctrl_shadowed_map_e1_wd),
13457
13458 // from internal hardware
13459 .de (1'b0),
13460 .d ('0),
13461
13462 // to internal hardware
13463 .qe (),
13464 .q (reg2hw.classb_ctrl_shadowed.map_e1.q),
13465 .ds (),
13466
13467 // to register interface (read)
13468 .qs (classb_ctrl_shadowed_map_e1_qs),
13469
13470 // Shadow register phase. Relevant for hwext only.
13471 .phase (),
13472
13473 // Shadow register error conditions
13474 .err_update (classb_ctrl_shadowed_map_e1_update_err),
13475 .err_storage (classb_ctrl_shadowed_map_e1_storage_err)
13476 );
13477
13478 // F[map_e2]: 11:10
13479 prim_subreg_shadow #(
13480 .DW (2),
13481 .SwAccess(prim_subreg_pkg::SwAccessRW),
13482 .RESVAL (2'h2),
13483 .Mubi (1'b0)
13484 ) u_classb_ctrl_shadowed_map_e2 (
13485 .clk_i (clk_i),
13486 .rst_ni (rst_ni),
13487 .rst_shadowed_ni (rst_shadowed_ni),
13488
13489 // from register interface
13490 .re (classb_ctrl_shadowed_re),
13491 .we (classb_ctrl_shadowed_gated_we),
13492 .wd (classb_ctrl_shadowed_map_e2_wd),
13493
13494 // from internal hardware
13495 .de (1'b0),
13496 .d ('0),
13497
13498 // to internal hardware
13499 .qe (),
13500 .q (reg2hw.classb_ctrl_shadowed.map_e2.q),
13501 .ds (),
13502
13503 // to register interface (read)
13504 .qs (classb_ctrl_shadowed_map_e2_qs),
13505
13506 // Shadow register phase. Relevant for hwext only.
13507 .phase (),
13508
13509 // Shadow register error conditions
13510 .err_update (classb_ctrl_shadowed_map_e2_update_err),
13511 .err_storage (classb_ctrl_shadowed_map_e2_storage_err)
13512 );
13513
13514 // F[map_e3]: 13:12
13515 prim_subreg_shadow #(
13516 .DW (2),
13517 .SwAccess(prim_subreg_pkg::SwAccessRW),
13518 .RESVAL (2'h3),
13519 .Mubi (1'b0)
13520 ) u_classb_ctrl_shadowed_map_e3 (
13521 .clk_i (clk_i),
13522 .rst_ni (rst_ni),
13523 .rst_shadowed_ni (rst_shadowed_ni),
13524
13525 // from register interface
13526 .re (classb_ctrl_shadowed_re),
13527 .we (classb_ctrl_shadowed_gated_we),
13528 .wd (classb_ctrl_shadowed_map_e3_wd),
13529
13530 // from internal hardware
13531 .de (1'b0),
13532 .d ('0),
13533
13534 // to internal hardware
13535 .qe (),
13536 .q (reg2hw.classb_ctrl_shadowed.map_e3.q),
13537 .ds (),
13538
13539 // to register interface (read)
13540 .qs (classb_ctrl_shadowed_map_e3_qs),
13541
13542 // Shadow register phase. Relevant for hwext only.
13543 .phase (),
13544
13545 // Shadow register error conditions
13546 .err_update (classb_ctrl_shadowed_map_e3_update_err),
13547 .err_storage (classb_ctrl_shadowed_map_e3_storage_err)
13548 );
13549
13550
13551 // R[classb_clr_regwen]: V(False)
13552 prim_subreg #(
13553 .DW (1),
13554 .SwAccess(prim_subreg_pkg::SwAccessW0C),
13555 .RESVAL (1'h1),
13556 .Mubi (1'b0)
13557 ) u_classb_clr_regwen (
13558 .clk_i (clk_i),
13559 .rst_ni (rst_ni),
13560
13561 // from register interface
13562 .we (classb_clr_regwen_we),
13563 .wd (classb_clr_regwen_wd),
13564
13565 // from internal hardware
13566 .de (hw2reg.classb_clr_regwen.de),
13567 .d (hw2reg.classb_clr_regwen.d),
13568
13569 // to internal hardware
13570 .qe (),
13571 .q (),
13572 .ds (),
13573
13574 // to register interface (read)
13575 .qs (classb_clr_regwen_qs)
13576 );
13577
13578
13579 // R[classb_clr_shadowed]: V(False)
13580 logic classb_clr_shadowed_qe;
13581 logic [0:0] classb_clr_shadowed_flds_we;
13582 prim_flop #(
13583 .Width(1),
13584 .ResetValue(0)
13585 ) u_classb_clr_shadowed0_qe (
13586 .clk_i(clk_i),
13587 .rst_ni(rst_ni),
13588 .d_i(&classb_clr_shadowed_flds_we),
13589 .q_o(classb_clr_shadowed_qe)
13590 );
13591 // Create REGWEN-gated WE signal
13592 logic classb_clr_shadowed_gated_we;
13593 1/1 assign classb_clr_shadowed_gated_we = classb_clr_shadowed_we & classb_clr_regwen_qs;
Tests: T1 T2 T3
13594 prim_subreg_shadow #(
13595 .DW (1),
13596 .SwAccess(prim_subreg_pkg::SwAccessRW),
13597 .RESVAL (1'h0),
13598 .Mubi (1'b0)
13599 ) u_classb_clr_shadowed (
13600 .clk_i (clk_i),
13601 .rst_ni (rst_ni),
13602 .rst_shadowed_ni (rst_shadowed_ni),
13603
13604 // from register interface
13605 .re (classb_clr_shadowed_re),
13606 .we (classb_clr_shadowed_gated_we),
13607 .wd (classb_clr_shadowed_wd),
13608
13609 // from internal hardware
13610 .de (1'b0),
13611 .d ('0),
13612
13613 // to internal hardware
13614 .qe (classb_clr_shadowed_flds_we[0]),
13615 .q (reg2hw.classb_clr_shadowed.q),
13616 .ds (),
13617
13618 // to register interface (read)
13619 .qs (classb_clr_shadowed_qs),
13620
13621 // Shadow register phase. Relevant for hwext only.
13622 .phase (),
13623
13624 // Shadow register error conditions
13625 .err_update (classb_clr_shadowed_update_err),
13626 .err_storage (classb_clr_shadowed_storage_err)
13627 );
13628 1/1 assign reg2hw.classb_clr_shadowed.qe = classb_clr_shadowed_qe;
Tests: T1 T2 T3
13629
13630
13631 // R[classb_accum_cnt]: V(True)
13632 prim_subreg_ext #(
13633 .DW (16)
13634 ) u_classb_accum_cnt (
13635 .re (classb_accum_cnt_re),
13636 .we (1'b0),
13637 .wd ('0),
13638 .d (hw2reg.classb_accum_cnt.d),
13639 .qre (),
13640 .qe (),
13641 .q (),
13642 .ds (),
13643 .qs (classb_accum_cnt_qs)
13644 );
13645
13646
13647 // R[classb_accum_thresh_shadowed]: V(False)
13648 // Create REGWEN-gated WE signal
13649 logic classb_accum_thresh_shadowed_gated_we;
13650 1/1 assign classb_accum_thresh_shadowed_gated_we = classb_accum_thresh_shadowed_we & classb_regwen_qs;
Tests: T1 T2 T3
13651 prim_subreg_shadow #(
13652 .DW (16),
13653 .SwAccess(prim_subreg_pkg::SwAccessRW),
13654 .RESVAL (16'h0),
13655 .Mubi (1'b0)
13656 ) u_classb_accum_thresh_shadowed (
13657 .clk_i (clk_i),
13658 .rst_ni (rst_ni),
13659 .rst_shadowed_ni (rst_shadowed_ni),
13660
13661 // from register interface
13662 .re (classb_accum_thresh_shadowed_re),
13663 .we (classb_accum_thresh_shadowed_gated_we),
13664 .wd (classb_accum_thresh_shadowed_wd),
13665
13666 // from internal hardware
13667 .de (1'b0),
13668 .d ('0),
13669
13670 // to internal hardware
13671 .qe (),
13672 .q (reg2hw.classb_accum_thresh_shadowed.q),
13673 .ds (),
13674
13675 // to register interface (read)
13676 .qs (classb_accum_thresh_shadowed_qs),
13677
13678 // Shadow register phase. Relevant for hwext only.
13679 .phase (),
13680
13681 // Shadow register error conditions
13682 .err_update (classb_accum_thresh_shadowed_update_err),
13683 .err_storage (classb_accum_thresh_shadowed_storage_err)
13684 );
13685
13686
13687 // R[classb_timeout_cyc_shadowed]: V(False)
13688 // Create REGWEN-gated WE signal
13689 logic classb_timeout_cyc_shadowed_gated_we;
13690 1/1 assign classb_timeout_cyc_shadowed_gated_we = classb_timeout_cyc_shadowed_we & classb_regwen_qs;
Tests: T1 T2 T3
13691 prim_subreg_shadow #(
13692 .DW (32),
13693 .SwAccess(prim_subreg_pkg::SwAccessRW),
13694 .RESVAL (32'h0),
13695 .Mubi (1'b0)
13696 ) u_classb_timeout_cyc_shadowed (
13697 .clk_i (clk_i),
13698 .rst_ni (rst_ni),
13699 .rst_shadowed_ni (rst_shadowed_ni),
13700
13701 // from register interface
13702 .re (classb_timeout_cyc_shadowed_re),
13703 .we (classb_timeout_cyc_shadowed_gated_we),
13704 .wd (classb_timeout_cyc_shadowed_wd),
13705
13706 // from internal hardware
13707 .de (1'b0),
13708 .d ('0),
13709
13710 // to internal hardware
13711 .qe (),
13712 .q (reg2hw.classb_timeout_cyc_shadowed.q),
13713 .ds (),
13714
13715 // to register interface (read)
13716 .qs (classb_timeout_cyc_shadowed_qs),
13717
13718 // Shadow register phase. Relevant for hwext only.
13719 .phase (),
13720
13721 // Shadow register error conditions
13722 .err_update (classb_timeout_cyc_shadowed_update_err),
13723 .err_storage (classb_timeout_cyc_shadowed_storage_err)
13724 );
13725
13726
13727 // R[classb_crashdump_trigger_shadowed]: V(False)
13728 // Create REGWEN-gated WE signal
13729 logic classb_crashdump_trigger_shadowed_gated_we;
13730 1/1 assign classb_crashdump_trigger_shadowed_gated_we =
Tests: T1 T2 T3
13731 classb_crashdump_trigger_shadowed_we & classb_regwen_qs;
13732 prim_subreg_shadow #(
13733 .DW (2),
13734 .SwAccess(prim_subreg_pkg::SwAccessRW),
13735 .RESVAL (2'h0),
13736 .Mubi (1'b0)
13737 ) u_classb_crashdump_trigger_shadowed (
13738 .clk_i (clk_i),
13739 .rst_ni (rst_ni),
13740 .rst_shadowed_ni (rst_shadowed_ni),
13741
13742 // from register interface
13743 .re (classb_crashdump_trigger_shadowed_re),
13744 .we (classb_crashdump_trigger_shadowed_gated_we),
13745 .wd (classb_crashdump_trigger_shadowed_wd),
13746
13747 // from internal hardware
13748 .de (1'b0),
13749 .d ('0),
13750
13751 // to internal hardware
13752 .qe (),
13753 .q (reg2hw.classb_crashdump_trigger_shadowed.q),
13754 .ds (),
13755
13756 // to register interface (read)
13757 .qs (classb_crashdump_trigger_shadowed_qs),
13758
13759 // Shadow register phase. Relevant for hwext only.
13760 .phase (),
13761
13762 // Shadow register error conditions
13763 .err_update (classb_crashdump_trigger_shadowed_update_err),
13764 .err_storage (classb_crashdump_trigger_shadowed_storage_err)
13765 );
13766
13767
13768 // R[classb_phase0_cyc_shadowed]: V(False)
13769 // Create REGWEN-gated WE signal
13770 logic classb_phase0_cyc_shadowed_gated_we;
13771 1/1 assign classb_phase0_cyc_shadowed_gated_we = classb_phase0_cyc_shadowed_we & classb_regwen_qs;
Tests: T1 T2 T3
13772 prim_subreg_shadow #(
13773 .DW (32),
13774 .SwAccess(prim_subreg_pkg::SwAccessRW),
13775 .RESVAL (32'h0),
13776 .Mubi (1'b0)
13777 ) u_classb_phase0_cyc_shadowed (
13778 .clk_i (clk_i),
13779 .rst_ni (rst_ni),
13780 .rst_shadowed_ni (rst_shadowed_ni),
13781
13782 // from register interface
13783 .re (classb_phase0_cyc_shadowed_re),
13784 .we (classb_phase0_cyc_shadowed_gated_we),
13785 .wd (classb_phase0_cyc_shadowed_wd),
13786
13787 // from internal hardware
13788 .de (1'b0),
13789 .d ('0),
13790
13791 // to internal hardware
13792 .qe (),
13793 .q (reg2hw.classb_phase0_cyc_shadowed.q),
13794 .ds (),
13795
13796 // to register interface (read)
13797 .qs (classb_phase0_cyc_shadowed_qs),
13798
13799 // Shadow register phase. Relevant for hwext only.
13800 .phase (),
13801
13802 // Shadow register error conditions
13803 .err_update (classb_phase0_cyc_shadowed_update_err),
13804 .err_storage (classb_phase0_cyc_shadowed_storage_err)
13805 );
13806
13807
13808 // R[classb_phase1_cyc_shadowed]: V(False)
13809 // Create REGWEN-gated WE signal
13810 logic classb_phase1_cyc_shadowed_gated_we;
13811 1/1 assign classb_phase1_cyc_shadowed_gated_we = classb_phase1_cyc_shadowed_we & classb_regwen_qs;
Tests: T1 T2 T3
13812 prim_subreg_shadow #(
13813 .DW (32),
13814 .SwAccess(prim_subreg_pkg::SwAccessRW),
13815 .RESVAL (32'h0),
13816 .Mubi (1'b0)
13817 ) u_classb_phase1_cyc_shadowed (
13818 .clk_i (clk_i),
13819 .rst_ni (rst_ni),
13820 .rst_shadowed_ni (rst_shadowed_ni),
13821
13822 // from register interface
13823 .re (classb_phase1_cyc_shadowed_re),
13824 .we (classb_phase1_cyc_shadowed_gated_we),
13825 .wd (classb_phase1_cyc_shadowed_wd),
13826
13827 // from internal hardware
13828 .de (1'b0),
13829 .d ('0),
13830
13831 // to internal hardware
13832 .qe (),
13833 .q (reg2hw.classb_phase1_cyc_shadowed.q),
13834 .ds (),
13835
13836 // to register interface (read)
13837 .qs (classb_phase1_cyc_shadowed_qs),
13838
13839 // Shadow register phase. Relevant for hwext only.
13840 .phase (),
13841
13842 // Shadow register error conditions
13843 .err_update (classb_phase1_cyc_shadowed_update_err),
13844 .err_storage (classb_phase1_cyc_shadowed_storage_err)
13845 );
13846
13847
13848 // R[classb_phase2_cyc_shadowed]: V(False)
13849 // Create REGWEN-gated WE signal
13850 logic classb_phase2_cyc_shadowed_gated_we;
13851 1/1 assign classb_phase2_cyc_shadowed_gated_we = classb_phase2_cyc_shadowed_we & classb_regwen_qs;
Tests: T1 T2 T3
13852 prim_subreg_shadow #(
13853 .DW (32),
13854 .SwAccess(prim_subreg_pkg::SwAccessRW),
13855 .RESVAL (32'h0),
13856 .Mubi (1'b0)
13857 ) u_classb_phase2_cyc_shadowed (
13858 .clk_i (clk_i),
13859 .rst_ni (rst_ni),
13860 .rst_shadowed_ni (rst_shadowed_ni),
13861
13862 // from register interface
13863 .re (classb_phase2_cyc_shadowed_re),
13864 .we (classb_phase2_cyc_shadowed_gated_we),
13865 .wd (classb_phase2_cyc_shadowed_wd),
13866
13867 // from internal hardware
13868 .de (1'b0),
13869 .d ('0),
13870
13871 // to internal hardware
13872 .qe (),
13873 .q (reg2hw.classb_phase2_cyc_shadowed.q),
13874 .ds (),
13875
13876 // to register interface (read)
13877 .qs (classb_phase2_cyc_shadowed_qs),
13878
13879 // Shadow register phase. Relevant for hwext only.
13880 .phase (),
13881
13882 // Shadow register error conditions
13883 .err_update (classb_phase2_cyc_shadowed_update_err),
13884 .err_storage (classb_phase2_cyc_shadowed_storage_err)
13885 );
13886
13887
13888 // R[classb_phase3_cyc_shadowed]: V(False)
13889 // Create REGWEN-gated WE signal
13890 logic classb_phase3_cyc_shadowed_gated_we;
13891 1/1 assign classb_phase3_cyc_shadowed_gated_we = classb_phase3_cyc_shadowed_we & classb_regwen_qs;
Tests: T1 T2 T3
13892 prim_subreg_shadow #(
13893 .DW (32),
13894 .SwAccess(prim_subreg_pkg::SwAccessRW),
13895 .RESVAL (32'h0),
13896 .Mubi (1'b0)
13897 ) u_classb_phase3_cyc_shadowed (
13898 .clk_i (clk_i),
13899 .rst_ni (rst_ni),
13900 .rst_shadowed_ni (rst_shadowed_ni),
13901
13902 // from register interface
13903 .re (classb_phase3_cyc_shadowed_re),
13904 .we (classb_phase3_cyc_shadowed_gated_we),
13905 .wd (classb_phase3_cyc_shadowed_wd),
13906
13907 // from internal hardware
13908 .de (1'b0),
13909 .d ('0),
13910
13911 // to internal hardware
13912 .qe (),
13913 .q (reg2hw.classb_phase3_cyc_shadowed.q),
13914 .ds (),
13915
13916 // to register interface (read)
13917 .qs (classb_phase3_cyc_shadowed_qs),
13918
13919 // Shadow register phase. Relevant for hwext only.
13920 .phase (),
13921
13922 // Shadow register error conditions
13923 .err_update (classb_phase3_cyc_shadowed_update_err),
13924 .err_storage (classb_phase3_cyc_shadowed_storage_err)
13925 );
13926
13927
13928 // R[classb_esc_cnt]: V(True)
13929 prim_subreg_ext #(
13930 .DW (32)
13931 ) u_classb_esc_cnt (
13932 .re (classb_esc_cnt_re),
13933 .we (1'b0),
13934 .wd ('0),
13935 .d (hw2reg.classb_esc_cnt.d),
13936 .qre (),
13937 .qe (),
13938 .q (),
13939 .ds (),
13940 .qs (classb_esc_cnt_qs)
13941 );
13942
13943
13944 // R[classb_state]: V(True)
13945 prim_subreg_ext #(
13946 .DW (3)
13947 ) u_classb_state (
13948 .re (classb_state_re),
13949 .we (1'b0),
13950 .wd ('0),
13951 .d (hw2reg.classb_state.d),
13952 .qre (),
13953 .qe (),
13954 .q (),
13955 .ds (),
13956 .qs (classb_state_qs)
13957 );
13958
13959
13960 // R[classc_regwen]: V(False)
13961 prim_subreg #(
13962 .DW (1),
13963 .SwAccess(prim_subreg_pkg::SwAccessW0C),
13964 .RESVAL (1'h1),
13965 .Mubi (1'b0)
13966 ) u_classc_regwen (
13967 .clk_i (clk_i),
13968 .rst_ni (rst_ni),
13969
13970 // from register interface
13971 .we (classc_regwen_we),
13972 .wd (classc_regwen_wd),
13973
13974 // from internal hardware
13975 .de (1'b0),
13976 .d ('0),
13977
13978 // to internal hardware
13979 .qe (),
13980 .q (),
13981 .ds (),
13982
13983 // to register interface (read)
13984 .qs (classc_regwen_qs)
13985 );
13986
13987
13988 // R[classc_ctrl_shadowed]: V(False)
13989 // Create REGWEN-gated WE signal
13990 logic classc_ctrl_shadowed_gated_we;
13991 1/1 assign classc_ctrl_shadowed_gated_we = classc_ctrl_shadowed_we & classc_regwen_qs;
Tests: T1 T2 T3
13992 // F[en]: 0:0
13993 prim_subreg_shadow #(
13994 .DW (1),
13995 .SwAccess(prim_subreg_pkg::SwAccessRW),
13996 .RESVAL (1'h0),
13997 .Mubi (1'b0)
13998 ) u_classc_ctrl_shadowed_en (
13999 .clk_i (clk_i),
14000 .rst_ni (rst_ni),
14001 .rst_shadowed_ni (rst_shadowed_ni),
14002
14003 // from register interface
14004 .re (classc_ctrl_shadowed_re),
14005 .we (classc_ctrl_shadowed_gated_we),
14006 .wd (classc_ctrl_shadowed_en_wd),
14007
14008 // from internal hardware
14009 .de (1'b0),
14010 .d ('0),
14011
14012 // to internal hardware
14013 .qe (),
14014 .q (reg2hw.classc_ctrl_shadowed.en.q),
14015 .ds (),
14016
14017 // to register interface (read)
14018 .qs (classc_ctrl_shadowed_en_qs),
14019
14020 // Shadow register phase. Relevant for hwext only.
14021 .phase (),
14022
14023 // Shadow register error conditions
14024 .err_update (classc_ctrl_shadowed_en_update_err),
14025 .err_storage (classc_ctrl_shadowed_en_storage_err)
14026 );
14027
14028 // F[lock]: 1:1
14029 prim_subreg_shadow #(
14030 .DW (1),
14031 .SwAccess(prim_subreg_pkg::SwAccessRW),
14032 .RESVAL (1'h0),
14033 .Mubi (1'b0)
14034 ) u_classc_ctrl_shadowed_lock (
14035 .clk_i (clk_i),
14036 .rst_ni (rst_ni),
14037 .rst_shadowed_ni (rst_shadowed_ni),
14038
14039 // from register interface
14040 .re (classc_ctrl_shadowed_re),
14041 .we (classc_ctrl_shadowed_gated_we),
14042 .wd (classc_ctrl_shadowed_lock_wd),
14043
14044 // from internal hardware
14045 .de (1'b0),
14046 .d ('0),
14047
14048 // to internal hardware
14049 .qe (),
14050 .q (reg2hw.classc_ctrl_shadowed.lock.q),
14051 .ds (),
14052
14053 // to register interface (read)
14054 .qs (classc_ctrl_shadowed_lock_qs),
14055
14056 // Shadow register phase. Relevant for hwext only.
14057 .phase (),
14058
14059 // Shadow register error conditions
14060 .err_update (classc_ctrl_shadowed_lock_update_err),
14061 .err_storage (classc_ctrl_shadowed_lock_storage_err)
14062 );
14063
14064 // F[en_e0]: 2:2
14065 prim_subreg_shadow #(
14066 .DW (1),
14067 .SwAccess(prim_subreg_pkg::SwAccessRW),
14068 .RESVAL (1'h1),
14069 .Mubi (1'b0)
14070 ) u_classc_ctrl_shadowed_en_e0 (
14071 .clk_i (clk_i),
14072 .rst_ni (rst_ni),
14073 .rst_shadowed_ni (rst_shadowed_ni),
14074
14075 // from register interface
14076 .re (classc_ctrl_shadowed_re),
14077 .we (classc_ctrl_shadowed_gated_we),
14078 .wd (classc_ctrl_shadowed_en_e0_wd),
14079
14080 // from internal hardware
14081 .de (1'b0),
14082 .d ('0),
14083
14084 // to internal hardware
14085 .qe (),
14086 .q (reg2hw.classc_ctrl_shadowed.en_e0.q),
14087 .ds (),
14088
14089 // to register interface (read)
14090 .qs (classc_ctrl_shadowed_en_e0_qs),
14091
14092 // Shadow register phase. Relevant for hwext only.
14093 .phase (),
14094
14095 // Shadow register error conditions
14096 .err_update (classc_ctrl_shadowed_en_e0_update_err),
14097 .err_storage (classc_ctrl_shadowed_en_e0_storage_err)
14098 );
14099
14100 // F[en_e1]: 3:3
14101 prim_subreg_shadow #(
14102 .DW (1),
14103 .SwAccess(prim_subreg_pkg::SwAccessRW),
14104 .RESVAL (1'h1),
14105 .Mubi (1'b0)
14106 ) u_classc_ctrl_shadowed_en_e1 (
14107 .clk_i (clk_i),
14108 .rst_ni (rst_ni),
14109 .rst_shadowed_ni (rst_shadowed_ni),
14110
14111 // from register interface
14112 .re (classc_ctrl_shadowed_re),
14113 .we (classc_ctrl_shadowed_gated_we),
14114 .wd (classc_ctrl_shadowed_en_e1_wd),
14115
14116 // from internal hardware
14117 .de (1'b0),
14118 .d ('0),
14119
14120 // to internal hardware
14121 .qe (),
14122 .q (reg2hw.classc_ctrl_shadowed.en_e1.q),
14123 .ds (),
14124
14125 // to register interface (read)
14126 .qs (classc_ctrl_shadowed_en_e1_qs),
14127
14128 // Shadow register phase. Relevant for hwext only.
14129 .phase (),
14130
14131 // Shadow register error conditions
14132 .err_update (classc_ctrl_shadowed_en_e1_update_err),
14133 .err_storage (classc_ctrl_shadowed_en_e1_storage_err)
14134 );
14135
14136 // F[en_e2]: 4:4
14137 prim_subreg_shadow #(
14138 .DW (1),
14139 .SwAccess(prim_subreg_pkg::SwAccessRW),
14140 .RESVAL (1'h1),
14141 .Mubi (1'b0)
14142 ) u_classc_ctrl_shadowed_en_e2 (
14143 .clk_i (clk_i),
14144 .rst_ni (rst_ni),
14145 .rst_shadowed_ni (rst_shadowed_ni),
14146
14147 // from register interface
14148 .re (classc_ctrl_shadowed_re),
14149 .we (classc_ctrl_shadowed_gated_we),
14150 .wd (classc_ctrl_shadowed_en_e2_wd),
14151
14152 // from internal hardware
14153 .de (1'b0),
14154 .d ('0),
14155
14156 // to internal hardware
14157 .qe (),
14158 .q (reg2hw.classc_ctrl_shadowed.en_e2.q),
14159 .ds (),
14160
14161 // to register interface (read)
14162 .qs (classc_ctrl_shadowed_en_e2_qs),
14163
14164 // Shadow register phase. Relevant for hwext only.
14165 .phase (),
14166
14167 // Shadow register error conditions
14168 .err_update (classc_ctrl_shadowed_en_e2_update_err),
14169 .err_storage (classc_ctrl_shadowed_en_e2_storage_err)
14170 );
14171
14172 // F[en_e3]: 5:5
14173 prim_subreg_shadow #(
14174 .DW (1),
14175 .SwAccess(prim_subreg_pkg::SwAccessRW),
14176 .RESVAL (1'h1),
14177 .Mubi (1'b0)
14178 ) u_classc_ctrl_shadowed_en_e3 (
14179 .clk_i (clk_i),
14180 .rst_ni (rst_ni),
14181 .rst_shadowed_ni (rst_shadowed_ni),
14182
14183 // from register interface
14184 .re (classc_ctrl_shadowed_re),
14185 .we (classc_ctrl_shadowed_gated_we),
14186 .wd (classc_ctrl_shadowed_en_e3_wd),
14187
14188 // from internal hardware
14189 .de (1'b0),
14190 .d ('0),
14191
14192 // to internal hardware
14193 .qe (),
14194 .q (reg2hw.classc_ctrl_shadowed.en_e3.q),
14195 .ds (),
14196
14197 // to register interface (read)
14198 .qs (classc_ctrl_shadowed_en_e3_qs),
14199
14200 // Shadow register phase. Relevant for hwext only.
14201 .phase (),
14202
14203 // Shadow register error conditions
14204 .err_update (classc_ctrl_shadowed_en_e3_update_err),
14205 .err_storage (classc_ctrl_shadowed_en_e3_storage_err)
14206 );
14207
14208 // F[map_e0]: 7:6
14209 prim_subreg_shadow #(
14210 .DW (2),
14211 .SwAccess(prim_subreg_pkg::SwAccessRW),
14212 .RESVAL (2'h0),
14213 .Mubi (1'b0)
14214 ) u_classc_ctrl_shadowed_map_e0 (
14215 .clk_i (clk_i),
14216 .rst_ni (rst_ni),
14217 .rst_shadowed_ni (rst_shadowed_ni),
14218
14219 // from register interface
14220 .re (classc_ctrl_shadowed_re),
14221 .we (classc_ctrl_shadowed_gated_we),
14222 .wd (classc_ctrl_shadowed_map_e0_wd),
14223
14224 // from internal hardware
14225 .de (1'b0),
14226 .d ('0),
14227
14228 // to internal hardware
14229 .qe (),
14230 .q (reg2hw.classc_ctrl_shadowed.map_e0.q),
14231 .ds (),
14232
14233 // to register interface (read)
14234 .qs (classc_ctrl_shadowed_map_e0_qs),
14235
14236 // Shadow register phase. Relevant for hwext only.
14237 .phase (),
14238
14239 // Shadow register error conditions
14240 .err_update (classc_ctrl_shadowed_map_e0_update_err),
14241 .err_storage (classc_ctrl_shadowed_map_e0_storage_err)
14242 );
14243
14244 // F[map_e1]: 9:8
14245 prim_subreg_shadow #(
14246 .DW (2),
14247 .SwAccess(prim_subreg_pkg::SwAccessRW),
14248 .RESVAL (2'h1),
14249 .Mubi (1'b0)
14250 ) u_classc_ctrl_shadowed_map_e1 (
14251 .clk_i (clk_i),
14252 .rst_ni (rst_ni),
14253 .rst_shadowed_ni (rst_shadowed_ni),
14254
14255 // from register interface
14256 .re (classc_ctrl_shadowed_re),
14257 .we (classc_ctrl_shadowed_gated_we),
14258 .wd (classc_ctrl_shadowed_map_e1_wd),
14259
14260 // from internal hardware
14261 .de (1'b0),
14262 .d ('0),
14263
14264 // to internal hardware
14265 .qe (),
14266 .q (reg2hw.classc_ctrl_shadowed.map_e1.q),
14267 .ds (),
14268
14269 // to register interface (read)
14270 .qs (classc_ctrl_shadowed_map_e1_qs),
14271
14272 // Shadow register phase. Relevant for hwext only.
14273 .phase (),
14274
14275 // Shadow register error conditions
14276 .err_update (classc_ctrl_shadowed_map_e1_update_err),
14277 .err_storage (classc_ctrl_shadowed_map_e1_storage_err)
14278 );
14279
14280 // F[map_e2]: 11:10
14281 prim_subreg_shadow #(
14282 .DW (2),
14283 .SwAccess(prim_subreg_pkg::SwAccessRW),
14284 .RESVAL (2'h2),
14285 .Mubi (1'b0)
14286 ) u_classc_ctrl_shadowed_map_e2 (
14287 .clk_i (clk_i),
14288 .rst_ni (rst_ni),
14289 .rst_shadowed_ni (rst_shadowed_ni),
14290
14291 // from register interface
14292 .re (classc_ctrl_shadowed_re),
14293 .we (classc_ctrl_shadowed_gated_we),
14294 .wd (classc_ctrl_shadowed_map_e2_wd),
14295
14296 // from internal hardware
14297 .de (1'b0),
14298 .d ('0),
14299
14300 // to internal hardware
14301 .qe (),
14302 .q (reg2hw.classc_ctrl_shadowed.map_e2.q),
14303 .ds (),
14304
14305 // to register interface (read)
14306 .qs (classc_ctrl_shadowed_map_e2_qs),
14307
14308 // Shadow register phase. Relevant for hwext only.
14309 .phase (),
14310
14311 // Shadow register error conditions
14312 .err_update (classc_ctrl_shadowed_map_e2_update_err),
14313 .err_storage (classc_ctrl_shadowed_map_e2_storage_err)
14314 );
14315
14316 // F[map_e3]: 13:12
14317 prim_subreg_shadow #(
14318 .DW (2),
14319 .SwAccess(prim_subreg_pkg::SwAccessRW),
14320 .RESVAL (2'h3),
14321 .Mubi (1'b0)
14322 ) u_classc_ctrl_shadowed_map_e3 (
14323 .clk_i (clk_i),
14324 .rst_ni (rst_ni),
14325 .rst_shadowed_ni (rst_shadowed_ni),
14326
14327 // from register interface
14328 .re (classc_ctrl_shadowed_re),
14329 .we (classc_ctrl_shadowed_gated_we),
14330 .wd (classc_ctrl_shadowed_map_e3_wd),
14331
14332 // from internal hardware
14333 .de (1'b0),
14334 .d ('0),
14335
14336 // to internal hardware
14337 .qe (),
14338 .q (reg2hw.classc_ctrl_shadowed.map_e3.q),
14339 .ds (),
14340
14341 // to register interface (read)
14342 .qs (classc_ctrl_shadowed_map_e3_qs),
14343
14344 // Shadow register phase. Relevant for hwext only.
14345 .phase (),
14346
14347 // Shadow register error conditions
14348 .err_update (classc_ctrl_shadowed_map_e3_update_err),
14349 .err_storage (classc_ctrl_shadowed_map_e3_storage_err)
14350 );
14351
14352
14353 // R[classc_clr_regwen]: V(False)
14354 prim_subreg #(
14355 .DW (1),
14356 .SwAccess(prim_subreg_pkg::SwAccessW0C),
14357 .RESVAL (1'h1),
14358 .Mubi (1'b0)
14359 ) u_classc_clr_regwen (
14360 .clk_i (clk_i),
14361 .rst_ni (rst_ni),
14362
14363 // from register interface
14364 .we (classc_clr_regwen_we),
14365 .wd (classc_clr_regwen_wd),
14366
14367 // from internal hardware
14368 .de (hw2reg.classc_clr_regwen.de),
14369 .d (hw2reg.classc_clr_regwen.d),
14370
14371 // to internal hardware
14372 .qe (),
14373 .q (),
14374 .ds (),
14375
14376 // to register interface (read)
14377 .qs (classc_clr_regwen_qs)
14378 );
14379
14380
14381 // R[classc_clr_shadowed]: V(False)
14382 logic classc_clr_shadowed_qe;
14383 logic [0:0] classc_clr_shadowed_flds_we;
14384 prim_flop #(
14385 .Width(1),
14386 .ResetValue(0)
14387 ) u_classc_clr_shadowed0_qe (
14388 .clk_i(clk_i),
14389 .rst_ni(rst_ni),
14390 .d_i(&classc_clr_shadowed_flds_we),
14391 .q_o(classc_clr_shadowed_qe)
14392 );
14393 // Create REGWEN-gated WE signal
14394 logic classc_clr_shadowed_gated_we;
14395 1/1 assign classc_clr_shadowed_gated_we = classc_clr_shadowed_we & classc_clr_regwen_qs;
Tests: T1 T2 T3
14396 prim_subreg_shadow #(
14397 .DW (1),
14398 .SwAccess(prim_subreg_pkg::SwAccessRW),
14399 .RESVAL (1'h0),
14400 .Mubi (1'b0)
14401 ) u_classc_clr_shadowed (
14402 .clk_i (clk_i),
14403 .rst_ni (rst_ni),
14404 .rst_shadowed_ni (rst_shadowed_ni),
14405
14406 // from register interface
14407 .re (classc_clr_shadowed_re),
14408 .we (classc_clr_shadowed_gated_we),
14409 .wd (classc_clr_shadowed_wd),
14410
14411 // from internal hardware
14412 .de (1'b0),
14413 .d ('0),
14414
14415 // to internal hardware
14416 .qe (classc_clr_shadowed_flds_we[0]),
14417 .q (reg2hw.classc_clr_shadowed.q),
14418 .ds (),
14419
14420 // to register interface (read)
14421 .qs (classc_clr_shadowed_qs),
14422
14423 // Shadow register phase. Relevant for hwext only.
14424 .phase (),
14425
14426 // Shadow register error conditions
14427 .err_update (classc_clr_shadowed_update_err),
14428 .err_storage (classc_clr_shadowed_storage_err)
14429 );
14430 1/1 assign reg2hw.classc_clr_shadowed.qe = classc_clr_shadowed_qe;
Tests: T1 T2 T3
14431
14432
14433 // R[classc_accum_cnt]: V(True)
14434 prim_subreg_ext #(
14435 .DW (16)
14436 ) u_classc_accum_cnt (
14437 .re (classc_accum_cnt_re),
14438 .we (1'b0),
14439 .wd ('0),
14440 .d (hw2reg.classc_accum_cnt.d),
14441 .qre (),
14442 .qe (),
14443 .q (),
14444 .ds (),
14445 .qs (classc_accum_cnt_qs)
14446 );
14447
14448
14449 // R[classc_accum_thresh_shadowed]: V(False)
14450 // Create REGWEN-gated WE signal
14451 logic classc_accum_thresh_shadowed_gated_we;
14452 1/1 assign classc_accum_thresh_shadowed_gated_we = classc_accum_thresh_shadowed_we & classc_regwen_qs;
Tests: T1 T2 T3
14453 prim_subreg_shadow #(
14454 .DW (16),
14455 .SwAccess(prim_subreg_pkg::SwAccessRW),
14456 .RESVAL (16'h0),
14457 .Mubi (1'b0)
14458 ) u_classc_accum_thresh_shadowed (
14459 .clk_i (clk_i),
14460 .rst_ni (rst_ni),
14461 .rst_shadowed_ni (rst_shadowed_ni),
14462
14463 // from register interface
14464 .re (classc_accum_thresh_shadowed_re),
14465 .we (classc_accum_thresh_shadowed_gated_we),
14466 .wd (classc_accum_thresh_shadowed_wd),
14467
14468 // from internal hardware
14469 .de (1'b0),
14470 .d ('0),
14471
14472 // to internal hardware
14473 .qe (),
14474 .q (reg2hw.classc_accum_thresh_shadowed.q),
14475 .ds (),
14476
14477 // to register interface (read)
14478 .qs (classc_accum_thresh_shadowed_qs),
14479
14480 // Shadow register phase. Relevant for hwext only.
14481 .phase (),
14482
14483 // Shadow register error conditions
14484 .err_update (classc_accum_thresh_shadowed_update_err),
14485 .err_storage (classc_accum_thresh_shadowed_storage_err)
14486 );
14487
14488
14489 // R[classc_timeout_cyc_shadowed]: V(False)
14490 // Create REGWEN-gated WE signal
14491 logic classc_timeout_cyc_shadowed_gated_we;
14492 1/1 assign classc_timeout_cyc_shadowed_gated_we = classc_timeout_cyc_shadowed_we & classc_regwen_qs;
Tests: T1 T2 T3
14493 prim_subreg_shadow #(
14494 .DW (32),
14495 .SwAccess(prim_subreg_pkg::SwAccessRW),
14496 .RESVAL (32'h0),
14497 .Mubi (1'b0)
14498 ) u_classc_timeout_cyc_shadowed (
14499 .clk_i (clk_i),
14500 .rst_ni (rst_ni),
14501 .rst_shadowed_ni (rst_shadowed_ni),
14502
14503 // from register interface
14504 .re (classc_timeout_cyc_shadowed_re),
14505 .we (classc_timeout_cyc_shadowed_gated_we),
14506 .wd (classc_timeout_cyc_shadowed_wd),
14507
14508 // from internal hardware
14509 .de (1'b0),
14510 .d ('0),
14511
14512 // to internal hardware
14513 .qe (),
14514 .q (reg2hw.classc_timeout_cyc_shadowed.q),
14515 .ds (),
14516
14517 // to register interface (read)
14518 .qs (classc_timeout_cyc_shadowed_qs),
14519
14520 // Shadow register phase. Relevant for hwext only.
14521 .phase (),
14522
14523 // Shadow register error conditions
14524 .err_update (classc_timeout_cyc_shadowed_update_err),
14525 .err_storage (classc_timeout_cyc_shadowed_storage_err)
14526 );
14527
14528
14529 // R[classc_crashdump_trigger_shadowed]: V(False)
14530 // Create REGWEN-gated WE signal
14531 logic classc_crashdump_trigger_shadowed_gated_we;
14532 1/1 assign classc_crashdump_trigger_shadowed_gated_we =
Tests: T1 T2 T3
14533 classc_crashdump_trigger_shadowed_we & classc_regwen_qs;
14534 prim_subreg_shadow #(
14535 .DW (2),
14536 .SwAccess(prim_subreg_pkg::SwAccessRW),
14537 .RESVAL (2'h0),
14538 .Mubi (1'b0)
14539 ) u_classc_crashdump_trigger_shadowed (
14540 .clk_i (clk_i),
14541 .rst_ni (rst_ni),
14542 .rst_shadowed_ni (rst_shadowed_ni),
14543
14544 // from register interface
14545 .re (classc_crashdump_trigger_shadowed_re),
14546 .we (classc_crashdump_trigger_shadowed_gated_we),
14547 .wd (classc_crashdump_trigger_shadowed_wd),
14548
14549 // from internal hardware
14550 .de (1'b0),
14551 .d ('0),
14552
14553 // to internal hardware
14554 .qe (),
14555 .q (reg2hw.classc_crashdump_trigger_shadowed.q),
14556 .ds (),
14557
14558 // to register interface (read)
14559 .qs (classc_crashdump_trigger_shadowed_qs),
14560
14561 // Shadow register phase. Relevant for hwext only.
14562 .phase (),
14563
14564 // Shadow register error conditions
14565 .err_update (classc_crashdump_trigger_shadowed_update_err),
14566 .err_storage (classc_crashdump_trigger_shadowed_storage_err)
14567 );
14568
14569
14570 // R[classc_phase0_cyc_shadowed]: V(False)
14571 // Create REGWEN-gated WE signal
14572 logic classc_phase0_cyc_shadowed_gated_we;
14573 1/1 assign classc_phase0_cyc_shadowed_gated_we = classc_phase0_cyc_shadowed_we & classc_regwen_qs;
Tests: T1 T2 T3
14574 prim_subreg_shadow #(
14575 .DW (32),
14576 .SwAccess(prim_subreg_pkg::SwAccessRW),
14577 .RESVAL (32'h0),
14578 .Mubi (1'b0)
14579 ) u_classc_phase0_cyc_shadowed (
14580 .clk_i (clk_i),
14581 .rst_ni (rst_ni),
14582 .rst_shadowed_ni (rst_shadowed_ni),
14583
14584 // from register interface
14585 .re (classc_phase0_cyc_shadowed_re),
14586 .we (classc_phase0_cyc_shadowed_gated_we),
14587 .wd (classc_phase0_cyc_shadowed_wd),
14588
14589 // from internal hardware
14590 .de (1'b0),
14591 .d ('0),
14592
14593 // to internal hardware
14594 .qe (),
14595 .q (reg2hw.classc_phase0_cyc_shadowed.q),
14596 .ds (),
14597
14598 // to register interface (read)
14599 .qs (classc_phase0_cyc_shadowed_qs),
14600
14601 // Shadow register phase. Relevant for hwext only.
14602 .phase (),
14603
14604 // Shadow register error conditions
14605 .err_update (classc_phase0_cyc_shadowed_update_err),
14606 .err_storage (classc_phase0_cyc_shadowed_storage_err)
14607 );
14608
14609
14610 // R[classc_phase1_cyc_shadowed]: V(False)
14611 // Create REGWEN-gated WE signal
14612 logic classc_phase1_cyc_shadowed_gated_we;
14613 1/1 assign classc_phase1_cyc_shadowed_gated_we = classc_phase1_cyc_shadowed_we & classc_regwen_qs;
Tests: T1 T2 T3
14614 prim_subreg_shadow #(
14615 .DW (32),
14616 .SwAccess(prim_subreg_pkg::SwAccessRW),
14617 .RESVAL (32'h0),
14618 .Mubi (1'b0)
14619 ) u_classc_phase1_cyc_shadowed (
14620 .clk_i (clk_i),
14621 .rst_ni (rst_ni),
14622 .rst_shadowed_ni (rst_shadowed_ni),
14623
14624 // from register interface
14625 .re (classc_phase1_cyc_shadowed_re),
14626 .we (classc_phase1_cyc_shadowed_gated_we),
14627 .wd (classc_phase1_cyc_shadowed_wd),
14628
14629 // from internal hardware
14630 .de (1'b0),
14631 .d ('0),
14632
14633 // to internal hardware
14634 .qe (),
14635 .q (reg2hw.classc_phase1_cyc_shadowed.q),
14636 .ds (),
14637
14638 // to register interface (read)
14639 .qs (classc_phase1_cyc_shadowed_qs),
14640
14641 // Shadow register phase. Relevant for hwext only.
14642 .phase (),
14643
14644 // Shadow register error conditions
14645 .err_update (classc_phase1_cyc_shadowed_update_err),
14646 .err_storage (classc_phase1_cyc_shadowed_storage_err)
14647 );
14648
14649
14650 // R[classc_phase2_cyc_shadowed]: V(False)
14651 // Create REGWEN-gated WE signal
14652 logic classc_phase2_cyc_shadowed_gated_we;
14653 1/1 assign classc_phase2_cyc_shadowed_gated_we = classc_phase2_cyc_shadowed_we & classc_regwen_qs;
Tests: T1 T2 T3
14654 prim_subreg_shadow #(
14655 .DW (32),
14656 .SwAccess(prim_subreg_pkg::SwAccessRW),
14657 .RESVAL (32'h0),
14658 .Mubi (1'b0)
14659 ) u_classc_phase2_cyc_shadowed (
14660 .clk_i (clk_i),
14661 .rst_ni (rst_ni),
14662 .rst_shadowed_ni (rst_shadowed_ni),
14663
14664 // from register interface
14665 .re (classc_phase2_cyc_shadowed_re),
14666 .we (classc_phase2_cyc_shadowed_gated_we),
14667 .wd (classc_phase2_cyc_shadowed_wd),
14668
14669 // from internal hardware
14670 .de (1'b0),
14671 .d ('0),
14672
14673 // to internal hardware
14674 .qe (),
14675 .q (reg2hw.classc_phase2_cyc_shadowed.q),
14676 .ds (),
14677
14678 // to register interface (read)
14679 .qs (classc_phase2_cyc_shadowed_qs),
14680
14681 // Shadow register phase. Relevant for hwext only.
14682 .phase (),
14683
14684 // Shadow register error conditions
14685 .err_update (classc_phase2_cyc_shadowed_update_err),
14686 .err_storage (classc_phase2_cyc_shadowed_storage_err)
14687 );
14688
14689
14690 // R[classc_phase3_cyc_shadowed]: V(False)
14691 // Create REGWEN-gated WE signal
14692 logic classc_phase3_cyc_shadowed_gated_we;
14693 1/1 assign classc_phase3_cyc_shadowed_gated_we = classc_phase3_cyc_shadowed_we & classc_regwen_qs;
Tests: T1 T2 T3
14694 prim_subreg_shadow #(
14695 .DW (32),
14696 .SwAccess(prim_subreg_pkg::SwAccessRW),
14697 .RESVAL (32'h0),
14698 .Mubi (1'b0)
14699 ) u_classc_phase3_cyc_shadowed (
14700 .clk_i (clk_i),
14701 .rst_ni (rst_ni),
14702 .rst_shadowed_ni (rst_shadowed_ni),
14703
14704 // from register interface
14705 .re (classc_phase3_cyc_shadowed_re),
14706 .we (classc_phase3_cyc_shadowed_gated_we),
14707 .wd (classc_phase3_cyc_shadowed_wd),
14708
14709 // from internal hardware
14710 .de (1'b0),
14711 .d ('0),
14712
14713 // to internal hardware
14714 .qe (),
14715 .q (reg2hw.classc_phase3_cyc_shadowed.q),
14716 .ds (),
14717
14718 // to register interface (read)
14719 .qs (classc_phase3_cyc_shadowed_qs),
14720
14721 // Shadow register phase. Relevant for hwext only.
14722 .phase (),
14723
14724 // Shadow register error conditions
14725 .err_update (classc_phase3_cyc_shadowed_update_err),
14726 .err_storage (classc_phase3_cyc_shadowed_storage_err)
14727 );
14728
14729
14730 // R[classc_esc_cnt]: V(True)
14731 prim_subreg_ext #(
14732 .DW (32)
14733 ) u_classc_esc_cnt (
14734 .re (classc_esc_cnt_re),
14735 .we (1'b0),
14736 .wd ('0),
14737 .d (hw2reg.classc_esc_cnt.d),
14738 .qre (),
14739 .qe (),
14740 .q (),
14741 .ds (),
14742 .qs (classc_esc_cnt_qs)
14743 );
14744
14745
14746 // R[classc_state]: V(True)
14747 prim_subreg_ext #(
14748 .DW (3)
14749 ) u_classc_state (
14750 .re (classc_state_re),
14751 .we (1'b0),
14752 .wd ('0),
14753 .d (hw2reg.classc_state.d),
14754 .qre (),
14755 .qe (),
14756 .q (),
14757 .ds (),
14758 .qs (classc_state_qs)
14759 );
14760
14761
14762 // R[classd_regwen]: V(False)
14763 prim_subreg #(
14764 .DW (1),
14765 .SwAccess(prim_subreg_pkg::SwAccessW0C),
14766 .RESVAL (1'h1),
14767 .Mubi (1'b0)
14768 ) u_classd_regwen (
14769 .clk_i (clk_i),
14770 .rst_ni (rst_ni),
14771
14772 // from register interface
14773 .we (classd_regwen_we),
14774 .wd (classd_regwen_wd),
14775
14776 // from internal hardware
14777 .de (1'b0),
14778 .d ('0),
14779
14780 // to internal hardware
14781 .qe (),
14782 .q (),
14783 .ds (),
14784
14785 // to register interface (read)
14786 .qs (classd_regwen_qs)
14787 );
14788
14789
14790 // R[classd_ctrl_shadowed]: V(False)
14791 // Create REGWEN-gated WE signal
14792 logic classd_ctrl_shadowed_gated_we;
14793 1/1 assign classd_ctrl_shadowed_gated_we = classd_ctrl_shadowed_we & classd_regwen_qs;
Tests: T1 T2 T3
14794 // F[en]: 0:0
14795 prim_subreg_shadow #(
14796 .DW (1),
14797 .SwAccess(prim_subreg_pkg::SwAccessRW),
14798 .RESVAL (1'h0),
14799 .Mubi (1'b0)
14800 ) u_classd_ctrl_shadowed_en (
14801 .clk_i (clk_i),
14802 .rst_ni (rst_ni),
14803 .rst_shadowed_ni (rst_shadowed_ni),
14804
14805 // from register interface
14806 .re (classd_ctrl_shadowed_re),
14807 .we (classd_ctrl_shadowed_gated_we),
14808 .wd (classd_ctrl_shadowed_en_wd),
14809
14810 // from internal hardware
14811 .de (1'b0),
14812 .d ('0),
14813
14814 // to internal hardware
14815 .qe (),
14816 .q (reg2hw.classd_ctrl_shadowed.en.q),
14817 .ds (),
14818
14819 // to register interface (read)
14820 .qs (classd_ctrl_shadowed_en_qs),
14821
14822 // Shadow register phase. Relevant for hwext only.
14823 .phase (),
14824
14825 // Shadow register error conditions
14826 .err_update (classd_ctrl_shadowed_en_update_err),
14827 .err_storage (classd_ctrl_shadowed_en_storage_err)
14828 );
14829
14830 // F[lock]: 1:1
14831 prim_subreg_shadow #(
14832 .DW (1),
14833 .SwAccess(prim_subreg_pkg::SwAccessRW),
14834 .RESVAL (1'h0),
14835 .Mubi (1'b0)
14836 ) u_classd_ctrl_shadowed_lock (
14837 .clk_i (clk_i),
14838 .rst_ni (rst_ni),
14839 .rst_shadowed_ni (rst_shadowed_ni),
14840
14841 // from register interface
14842 .re (classd_ctrl_shadowed_re),
14843 .we (classd_ctrl_shadowed_gated_we),
14844 .wd (classd_ctrl_shadowed_lock_wd),
14845
14846 // from internal hardware
14847 .de (1'b0),
14848 .d ('0),
14849
14850 // to internal hardware
14851 .qe (),
14852 .q (reg2hw.classd_ctrl_shadowed.lock.q),
14853 .ds (),
14854
14855 // to register interface (read)
14856 .qs (classd_ctrl_shadowed_lock_qs),
14857
14858 // Shadow register phase. Relevant for hwext only.
14859 .phase (),
14860
14861 // Shadow register error conditions
14862 .err_update (classd_ctrl_shadowed_lock_update_err),
14863 .err_storage (classd_ctrl_shadowed_lock_storage_err)
14864 );
14865
14866 // F[en_e0]: 2:2
14867 prim_subreg_shadow #(
14868 .DW (1),
14869 .SwAccess(prim_subreg_pkg::SwAccessRW),
14870 .RESVAL (1'h1),
14871 .Mubi (1'b0)
14872 ) u_classd_ctrl_shadowed_en_e0 (
14873 .clk_i (clk_i),
14874 .rst_ni (rst_ni),
14875 .rst_shadowed_ni (rst_shadowed_ni),
14876
14877 // from register interface
14878 .re (classd_ctrl_shadowed_re),
14879 .we (classd_ctrl_shadowed_gated_we),
14880 .wd (classd_ctrl_shadowed_en_e0_wd),
14881
14882 // from internal hardware
14883 .de (1'b0),
14884 .d ('0),
14885
14886 // to internal hardware
14887 .qe (),
14888 .q (reg2hw.classd_ctrl_shadowed.en_e0.q),
14889 .ds (),
14890
14891 // to register interface (read)
14892 .qs (classd_ctrl_shadowed_en_e0_qs),
14893
14894 // Shadow register phase. Relevant for hwext only.
14895 .phase (),
14896
14897 // Shadow register error conditions
14898 .err_update (classd_ctrl_shadowed_en_e0_update_err),
14899 .err_storage (classd_ctrl_shadowed_en_e0_storage_err)
14900 );
14901
14902 // F[en_e1]: 3:3
14903 prim_subreg_shadow #(
14904 .DW (1),
14905 .SwAccess(prim_subreg_pkg::SwAccessRW),
14906 .RESVAL (1'h1),
14907 .Mubi (1'b0)
14908 ) u_classd_ctrl_shadowed_en_e1 (
14909 .clk_i (clk_i),
14910 .rst_ni (rst_ni),
14911 .rst_shadowed_ni (rst_shadowed_ni),
14912
14913 // from register interface
14914 .re (classd_ctrl_shadowed_re),
14915 .we (classd_ctrl_shadowed_gated_we),
14916 .wd (classd_ctrl_shadowed_en_e1_wd),
14917
14918 // from internal hardware
14919 .de (1'b0),
14920 .d ('0),
14921
14922 // to internal hardware
14923 .qe (),
14924 .q (reg2hw.classd_ctrl_shadowed.en_e1.q),
14925 .ds (),
14926
14927 // to register interface (read)
14928 .qs (classd_ctrl_shadowed_en_e1_qs),
14929
14930 // Shadow register phase. Relevant for hwext only.
14931 .phase (),
14932
14933 // Shadow register error conditions
14934 .err_update (classd_ctrl_shadowed_en_e1_update_err),
14935 .err_storage (classd_ctrl_shadowed_en_e1_storage_err)
14936 );
14937
14938 // F[en_e2]: 4:4
14939 prim_subreg_shadow #(
14940 .DW (1),
14941 .SwAccess(prim_subreg_pkg::SwAccessRW),
14942 .RESVAL (1'h1),
14943 .Mubi (1'b0)
14944 ) u_classd_ctrl_shadowed_en_e2 (
14945 .clk_i (clk_i),
14946 .rst_ni (rst_ni),
14947 .rst_shadowed_ni (rst_shadowed_ni),
14948
14949 // from register interface
14950 .re (classd_ctrl_shadowed_re),
14951 .we (classd_ctrl_shadowed_gated_we),
14952 .wd (classd_ctrl_shadowed_en_e2_wd),
14953
14954 // from internal hardware
14955 .de (1'b0),
14956 .d ('0),
14957
14958 // to internal hardware
14959 .qe (),
14960 .q (reg2hw.classd_ctrl_shadowed.en_e2.q),
14961 .ds (),
14962
14963 // to register interface (read)
14964 .qs (classd_ctrl_shadowed_en_e2_qs),
14965
14966 // Shadow register phase. Relevant for hwext only.
14967 .phase (),
14968
14969 // Shadow register error conditions
14970 .err_update (classd_ctrl_shadowed_en_e2_update_err),
14971 .err_storage (classd_ctrl_shadowed_en_e2_storage_err)
14972 );
14973
14974 // F[en_e3]: 5:5
14975 prim_subreg_shadow #(
14976 .DW (1),
14977 .SwAccess(prim_subreg_pkg::SwAccessRW),
14978 .RESVAL (1'h1),
14979 .Mubi (1'b0)
14980 ) u_classd_ctrl_shadowed_en_e3 (
14981 .clk_i (clk_i),
14982 .rst_ni (rst_ni),
14983 .rst_shadowed_ni (rst_shadowed_ni),
14984
14985 // from register interface
14986 .re (classd_ctrl_shadowed_re),
14987 .we (classd_ctrl_shadowed_gated_we),
14988 .wd (classd_ctrl_shadowed_en_e3_wd),
14989
14990 // from internal hardware
14991 .de (1'b0),
14992 .d ('0),
14993
14994 // to internal hardware
14995 .qe (),
14996 .q (reg2hw.classd_ctrl_shadowed.en_e3.q),
14997 .ds (),
14998
14999 // to register interface (read)
15000 .qs (classd_ctrl_shadowed_en_e3_qs),
15001
15002 // Shadow register phase. Relevant for hwext only.
15003 .phase (),
15004
15005 // Shadow register error conditions
15006 .err_update (classd_ctrl_shadowed_en_e3_update_err),
15007 .err_storage (classd_ctrl_shadowed_en_e3_storage_err)
15008 );
15009
15010 // F[map_e0]: 7:6
15011 prim_subreg_shadow #(
15012 .DW (2),
15013 .SwAccess(prim_subreg_pkg::SwAccessRW),
15014 .RESVAL (2'h0),
15015 .Mubi (1'b0)
15016 ) u_classd_ctrl_shadowed_map_e0 (
15017 .clk_i (clk_i),
15018 .rst_ni (rst_ni),
15019 .rst_shadowed_ni (rst_shadowed_ni),
15020
15021 // from register interface
15022 .re (classd_ctrl_shadowed_re),
15023 .we (classd_ctrl_shadowed_gated_we),
15024 .wd (classd_ctrl_shadowed_map_e0_wd),
15025
15026 // from internal hardware
15027 .de (1'b0),
15028 .d ('0),
15029
15030 // to internal hardware
15031 .qe (),
15032 .q (reg2hw.classd_ctrl_shadowed.map_e0.q),
15033 .ds (),
15034
15035 // to register interface (read)
15036 .qs (classd_ctrl_shadowed_map_e0_qs),
15037
15038 // Shadow register phase. Relevant for hwext only.
15039 .phase (),
15040
15041 // Shadow register error conditions
15042 .err_update (classd_ctrl_shadowed_map_e0_update_err),
15043 .err_storage (classd_ctrl_shadowed_map_e0_storage_err)
15044 );
15045
15046 // F[map_e1]: 9:8
15047 prim_subreg_shadow #(
15048 .DW (2),
15049 .SwAccess(prim_subreg_pkg::SwAccessRW),
15050 .RESVAL (2'h1),
15051 .Mubi (1'b0)
15052 ) u_classd_ctrl_shadowed_map_e1 (
15053 .clk_i (clk_i),
15054 .rst_ni (rst_ni),
15055 .rst_shadowed_ni (rst_shadowed_ni),
15056
15057 // from register interface
15058 .re (classd_ctrl_shadowed_re),
15059 .we (classd_ctrl_shadowed_gated_we),
15060 .wd (classd_ctrl_shadowed_map_e1_wd),
15061
15062 // from internal hardware
15063 .de (1'b0),
15064 .d ('0),
15065
15066 // to internal hardware
15067 .qe (),
15068 .q (reg2hw.classd_ctrl_shadowed.map_e1.q),
15069 .ds (),
15070
15071 // to register interface (read)
15072 .qs (classd_ctrl_shadowed_map_e1_qs),
15073
15074 // Shadow register phase. Relevant for hwext only.
15075 .phase (),
15076
15077 // Shadow register error conditions
15078 .err_update (classd_ctrl_shadowed_map_e1_update_err),
15079 .err_storage (classd_ctrl_shadowed_map_e1_storage_err)
15080 );
15081
15082 // F[map_e2]: 11:10
15083 prim_subreg_shadow #(
15084 .DW (2),
15085 .SwAccess(prim_subreg_pkg::SwAccessRW),
15086 .RESVAL (2'h2),
15087 .Mubi (1'b0)
15088 ) u_classd_ctrl_shadowed_map_e2 (
15089 .clk_i (clk_i),
15090 .rst_ni (rst_ni),
15091 .rst_shadowed_ni (rst_shadowed_ni),
15092
15093 // from register interface
15094 .re (classd_ctrl_shadowed_re),
15095 .we (classd_ctrl_shadowed_gated_we),
15096 .wd (classd_ctrl_shadowed_map_e2_wd),
15097
15098 // from internal hardware
15099 .de (1'b0),
15100 .d ('0),
15101
15102 // to internal hardware
15103 .qe (),
15104 .q (reg2hw.classd_ctrl_shadowed.map_e2.q),
15105 .ds (),
15106
15107 // to register interface (read)
15108 .qs (classd_ctrl_shadowed_map_e2_qs),
15109
15110 // Shadow register phase. Relevant for hwext only.
15111 .phase (),
15112
15113 // Shadow register error conditions
15114 .err_update (classd_ctrl_shadowed_map_e2_update_err),
15115 .err_storage (classd_ctrl_shadowed_map_e2_storage_err)
15116 );
15117
15118 // F[map_e3]: 13:12
15119 prim_subreg_shadow #(
15120 .DW (2),
15121 .SwAccess(prim_subreg_pkg::SwAccessRW),
15122 .RESVAL (2'h3),
15123 .Mubi (1'b0)
15124 ) u_classd_ctrl_shadowed_map_e3 (
15125 .clk_i (clk_i),
15126 .rst_ni (rst_ni),
15127 .rst_shadowed_ni (rst_shadowed_ni),
15128
15129 // from register interface
15130 .re (classd_ctrl_shadowed_re),
15131 .we (classd_ctrl_shadowed_gated_we),
15132 .wd (classd_ctrl_shadowed_map_e3_wd),
15133
15134 // from internal hardware
15135 .de (1'b0),
15136 .d ('0),
15137
15138 // to internal hardware
15139 .qe (),
15140 .q (reg2hw.classd_ctrl_shadowed.map_e3.q),
15141 .ds (),
15142
15143 // to register interface (read)
15144 .qs (classd_ctrl_shadowed_map_e3_qs),
15145
15146 // Shadow register phase. Relevant for hwext only.
15147 .phase (),
15148
15149 // Shadow register error conditions
15150 .err_update (classd_ctrl_shadowed_map_e3_update_err),
15151 .err_storage (classd_ctrl_shadowed_map_e3_storage_err)
15152 );
15153
15154
15155 // R[classd_clr_regwen]: V(False)
15156 prim_subreg #(
15157 .DW (1),
15158 .SwAccess(prim_subreg_pkg::SwAccessW0C),
15159 .RESVAL (1'h1),
15160 .Mubi (1'b0)
15161 ) u_classd_clr_regwen (
15162 .clk_i (clk_i),
15163 .rst_ni (rst_ni),
15164
15165 // from register interface
15166 .we (classd_clr_regwen_we),
15167 .wd (classd_clr_regwen_wd),
15168
15169 // from internal hardware
15170 .de (hw2reg.classd_clr_regwen.de),
15171 .d (hw2reg.classd_clr_regwen.d),
15172
15173 // to internal hardware
15174 .qe (),
15175 .q (),
15176 .ds (),
15177
15178 // to register interface (read)
15179 .qs (classd_clr_regwen_qs)
15180 );
15181
15182
15183 // R[classd_clr_shadowed]: V(False)
15184 logic classd_clr_shadowed_qe;
15185 logic [0:0] classd_clr_shadowed_flds_we;
15186 prim_flop #(
15187 .Width(1),
15188 .ResetValue(0)
15189 ) u_classd_clr_shadowed0_qe (
15190 .clk_i(clk_i),
15191 .rst_ni(rst_ni),
15192 .d_i(&classd_clr_shadowed_flds_we),
15193 .q_o(classd_clr_shadowed_qe)
15194 );
15195 // Create REGWEN-gated WE signal
15196 logic classd_clr_shadowed_gated_we;
15197 1/1 assign classd_clr_shadowed_gated_we = classd_clr_shadowed_we & classd_clr_regwen_qs;
Tests: T1 T2 T3
15198 prim_subreg_shadow #(
15199 .DW (1),
15200 .SwAccess(prim_subreg_pkg::SwAccessRW),
15201 .RESVAL (1'h0),
15202 .Mubi (1'b0)
15203 ) u_classd_clr_shadowed (
15204 .clk_i (clk_i),
15205 .rst_ni (rst_ni),
15206 .rst_shadowed_ni (rst_shadowed_ni),
15207
15208 // from register interface
15209 .re (classd_clr_shadowed_re),
15210 .we (classd_clr_shadowed_gated_we),
15211 .wd (classd_clr_shadowed_wd),
15212
15213 // from internal hardware
15214 .de (1'b0),
15215 .d ('0),
15216
15217 // to internal hardware
15218 .qe (classd_clr_shadowed_flds_we[0]),
15219 .q (reg2hw.classd_clr_shadowed.q),
15220 .ds (),
15221
15222 // to register interface (read)
15223 .qs (classd_clr_shadowed_qs),
15224
15225 // Shadow register phase. Relevant for hwext only.
15226 .phase (),
15227
15228 // Shadow register error conditions
15229 .err_update (classd_clr_shadowed_update_err),
15230 .err_storage (classd_clr_shadowed_storage_err)
15231 );
15232 1/1 assign reg2hw.classd_clr_shadowed.qe = classd_clr_shadowed_qe;
Tests: T1 T2 T3
15233
15234
15235 // R[classd_accum_cnt]: V(True)
15236 prim_subreg_ext #(
15237 .DW (16)
15238 ) u_classd_accum_cnt (
15239 .re (classd_accum_cnt_re),
15240 .we (1'b0),
15241 .wd ('0),
15242 .d (hw2reg.classd_accum_cnt.d),
15243 .qre (),
15244 .qe (),
15245 .q (),
15246 .ds (),
15247 .qs (classd_accum_cnt_qs)
15248 );
15249
15250
15251 // R[classd_accum_thresh_shadowed]: V(False)
15252 // Create REGWEN-gated WE signal
15253 logic classd_accum_thresh_shadowed_gated_we;
15254 1/1 assign classd_accum_thresh_shadowed_gated_we = classd_accum_thresh_shadowed_we & classd_regwen_qs;
Tests: T1 T2 T3
15255 prim_subreg_shadow #(
15256 .DW (16),
15257 .SwAccess(prim_subreg_pkg::SwAccessRW),
15258 .RESVAL (16'h0),
15259 .Mubi (1'b0)
15260 ) u_classd_accum_thresh_shadowed (
15261 .clk_i (clk_i),
15262 .rst_ni (rst_ni),
15263 .rst_shadowed_ni (rst_shadowed_ni),
15264
15265 // from register interface
15266 .re (classd_accum_thresh_shadowed_re),
15267 .we (classd_accum_thresh_shadowed_gated_we),
15268 .wd (classd_accum_thresh_shadowed_wd),
15269
15270 // from internal hardware
15271 .de (1'b0),
15272 .d ('0),
15273
15274 // to internal hardware
15275 .qe (),
15276 .q (reg2hw.classd_accum_thresh_shadowed.q),
15277 .ds (),
15278
15279 // to register interface (read)
15280 .qs (classd_accum_thresh_shadowed_qs),
15281
15282 // Shadow register phase. Relevant for hwext only.
15283 .phase (),
15284
15285 // Shadow register error conditions
15286 .err_update (classd_accum_thresh_shadowed_update_err),
15287 .err_storage (classd_accum_thresh_shadowed_storage_err)
15288 );
15289
15290
15291 // R[classd_timeout_cyc_shadowed]: V(False)
15292 // Create REGWEN-gated WE signal
15293 logic classd_timeout_cyc_shadowed_gated_we;
15294 1/1 assign classd_timeout_cyc_shadowed_gated_we = classd_timeout_cyc_shadowed_we & classd_regwen_qs;
Tests: T1 T2 T3
15295 prim_subreg_shadow #(
15296 .DW (32),
15297 .SwAccess(prim_subreg_pkg::SwAccessRW),
15298 .RESVAL (32'h0),
15299 .Mubi (1'b0)
15300 ) u_classd_timeout_cyc_shadowed (
15301 .clk_i (clk_i),
15302 .rst_ni (rst_ni),
15303 .rst_shadowed_ni (rst_shadowed_ni),
15304
15305 // from register interface
15306 .re (classd_timeout_cyc_shadowed_re),
15307 .we (classd_timeout_cyc_shadowed_gated_we),
15308 .wd (classd_timeout_cyc_shadowed_wd),
15309
15310 // from internal hardware
15311 .de (1'b0),
15312 .d ('0),
15313
15314 // to internal hardware
15315 .qe (),
15316 .q (reg2hw.classd_timeout_cyc_shadowed.q),
15317 .ds (),
15318
15319 // to register interface (read)
15320 .qs (classd_timeout_cyc_shadowed_qs),
15321
15322 // Shadow register phase. Relevant for hwext only.
15323 .phase (),
15324
15325 // Shadow register error conditions
15326 .err_update (classd_timeout_cyc_shadowed_update_err),
15327 .err_storage (classd_timeout_cyc_shadowed_storage_err)
15328 );
15329
15330
15331 // R[classd_crashdump_trigger_shadowed]: V(False)
15332 // Create REGWEN-gated WE signal
15333 logic classd_crashdump_trigger_shadowed_gated_we;
15334 1/1 assign classd_crashdump_trigger_shadowed_gated_we =
Tests: T1 T2 T3
15335 classd_crashdump_trigger_shadowed_we & classd_regwen_qs;
15336 prim_subreg_shadow #(
15337 .DW (2),
15338 .SwAccess(prim_subreg_pkg::SwAccessRW),
15339 .RESVAL (2'h0),
15340 .Mubi (1'b0)
15341 ) u_classd_crashdump_trigger_shadowed (
15342 .clk_i (clk_i),
15343 .rst_ni (rst_ni),
15344 .rst_shadowed_ni (rst_shadowed_ni),
15345
15346 // from register interface
15347 .re (classd_crashdump_trigger_shadowed_re),
15348 .we (classd_crashdump_trigger_shadowed_gated_we),
15349 .wd (classd_crashdump_trigger_shadowed_wd),
15350
15351 // from internal hardware
15352 .de (1'b0),
15353 .d ('0),
15354
15355 // to internal hardware
15356 .qe (),
15357 .q (reg2hw.classd_crashdump_trigger_shadowed.q),
15358 .ds (),
15359
15360 // to register interface (read)
15361 .qs (classd_crashdump_trigger_shadowed_qs),
15362
15363 // Shadow register phase. Relevant for hwext only.
15364 .phase (),
15365
15366 // Shadow register error conditions
15367 .err_update (classd_crashdump_trigger_shadowed_update_err),
15368 .err_storage (classd_crashdump_trigger_shadowed_storage_err)
15369 );
15370
15371
15372 // R[classd_phase0_cyc_shadowed]: V(False)
15373 // Create REGWEN-gated WE signal
15374 logic classd_phase0_cyc_shadowed_gated_we;
15375 1/1 assign classd_phase0_cyc_shadowed_gated_we = classd_phase0_cyc_shadowed_we & classd_regwen_qs;
Tests: T1 T2 T3
15376 prim_subreg_shadow #(
15377 .DW (32),
15378 .SwAccess(prim_subreg_pkg::SwAccessRW),
15379 .RESVAL (32'h0),
15380 .Mubi (1'b0)
15381 ) u_classd_phase0_cyc_shadowed (
15382 .clk_i (clk_i),
15383 .rst_ni (rst_ni),
15384 .rst_shadowed_ni (rst_shadowed_ni),
15385
15386 // from register interface
15387 .re (classd_phase0_cyc_shadowed_re),
15388 .we (classd_phase0_cyc_shadowed_gated_we),
15389 .wd (classd_phase0_cyc_shadowed_wd),
15390
15391 // from internal hardware
15392 .de (1'b0),
15393 .d ('0),
15394
15395 // to internal hardware
15396 .qe (),
15397 .q (reg2hw.classd_phase0_cyc_shadowed.q),
15398 .ds (),
15399
15400 // to register interface (read)
15401 .qs (classd_phase0_cyc_shadowed_qs),
15402
15403 // Shadow register phase. Relevant for hwext only.
15404 .phase (),
15405
15406 // Shadow register error conditions
15407 .err_update (classd_phase0_cyc_shadowed_update_err),
15408 .err_storage (classd_phase0_cyc_shadowed_storage_err)
15409 );
15410
15411
15412 // R[classd_phase1_cyc_shadowed]: V(False)
15413 // Create REGWEN-gated WE signal
15414 logic classd_phase1_cyc_shadowed_gated_we;
15415 1/1 assign classd_phase1_cyc_shadowed_gated_we = classd_phase1_cyc_shadowed_we & classd_regwen_qs;
Tests: T1 T2 T3
15416 prim_subreg_shadow #(
15417 .DW (32),
15418 .SwAccess(prim_subreg_pkg::SwAccessRW),
15419 .RESVAL (32'h0),
15420 .Mubi (1'b0)
15421 ) u_classd_phase1_cyc_shadowed (
15422 .clk_i (clk_i),
15423 .rst_ni (rst_ni),
15424 .rst_shadowed_ni (rst_shadowed_ni),
15425
15426 // from register interface
15427 .re (classd_phase1_cyc_shadowed_re),
15428 .we (classd_phase1_cyc_shadowed_gated_we),
15429 .wd (classd_phase1_cyc_shadowed_wd),
15430
15431 // from internal hardware
15432 .de (1'b0),
15433 .d ('0),
15434
15435 // to internal hardware
15436 .qe (),
15437 .q (reg2hw.classd_phase1_cyc_shadowed.q),
15438 .ds (),
15439
15440 // to register interface (read)
15441 .qs (classd_phase1_cyc_shadowed_qs),
15442
15443 // Shadow register phase. Relevant for hwext only.
15444 .phase (),
15445
15446 // Shadow register error conditions
15447 .err_update (classd_phase1_cyc_shadowed_update_err),
15448 .err_storage (classd_phase1_cyc_shadowed_storage_err)
15449 );
15450
15451
15452 // R[classd_phase2_cyc_shadowed]: V(False)
15453 // Create REGWEN-gated WE signal
15454 logic classd_phase2_cyc_shadowed_gated_we;
15455 1/1 assign classd_phase2_cyc_shadowed_gated_we = classd_phase2_cyc_shadowed_we & classd_regwen_qs;
Tests: T1 T2 T3
15456 prim_subreg_shadow #(
15457 .DW (32),
15458 .SwAccess(prim_subreg_pkg::SwAccessRW),
15459 .RESVAL (32'h0),
15460 .Mubi (1'b0)
15461 ) u_classd_phase2_cyc_shadowed (
15462 .clk_i (clk_i),
15463 .rst_ni (rst_ni),
15464 .rst_shadowed_ni (rst_shadowed_ni),
15465
15466 // from register interface
15467 .re (classd_phase2_cyc_shadowed_re),
15468 .we (classd_phase2_cyc_shadowed_gated_we),
15469 .wd (classd_phase2_cyc_shadowed_wd),
15470
15471 // from internal hardware
15472 .de (1'b0),
15473 .d ('0),
15474
15475 // to internal hardware
15476 .qe (),
15477 .q (reg2hw.classd_phase2_cyc_shadowed.q),
15478 .ds (),
15479
15480 // to register interface (read)
15481 .qs (classd_phase2_cyc_shadowed_qs),
15482
15483 // Shadow register phase. Relevant for hwext only.
15484 .phase (),
15485
15486 // Shadow register error conditions
15487 .err_update (classd_phase2_cyc_shadowed_update_err),
15488 .err_storage (classd_phase2_cyc_shadowed_storage_err)
15489 );
15490
15491
15492 // R[classd_phase3_cyc_shadowed]: V(False)
15493 // Create REGWEN-gated WE signal
15494 logic classd_phase3_cyc_shadowed_gated_we;
15495 1/1 assign classd_phase3_cyc_shadowed_gated_we = classd_phase3_cyc_shadowed_we & classd_regwen_qs;
Tests: T1 T2 T3
15496 prim_subreg_shadow #(
15497 .DW (32),
15498 .SwAccess(prim_subreg_pkg::SwAccessRW),
15499 .RESVAL (32'h0),
15500 .Mubi (1'b0)
15501 ) u_classd_phase3_cyc_shadowed (
15502 .clk_i (clk_i),
15503 .rst_ni (rst_ni),
15504 .rst_shadowed_ni (rst_shadowed_ni),
15505
15506 // from register interface
15507 .re (classd_phase3_cyc_shadowed_re),
15508 .we (classd_phase3_cyc_shadowed_gated_we),
15509 .wd (classd_phase3_cyc_shadowed_wd),
15510
15511 // from internal hardware
15512 .de (1'b0),
15513 .d ('0),
15514
15515 // to internal hardware
15516 .qe (),
15517 .q (reg2hw.classd_phase3_cyc_shadowed.q),
15518 .ds (),
15519
15520 // to register interface (read)
15521 .qs (classd_phase3_cyc_shadowed_qs),
15522
15523 // Shadow register phase. Relevant for hwext only.
15524 .phase (),
15525
15526 // Shadow register error conditions
15527 .err_update (classd_phase3_cyc_shadowed_update_err),
15528 .err_storage (classd_phase3_cyc_shadowed_storage_err)
15529 );
15530
15531
15532 // R[classd_esc_cnt]: V(True)
15533 prim_subreg_ext #(
15534 .DW (32)
15535 ) u_classd_esc_cnt (
15536 .re (classd_esc_cnt_re),
15537 .we (1'b0),
15538 .wd ('0),
15539 .d (hw2reg.classd_esc_cnt.d),
15540 .qre (),
15541 .qe (),
15542 .q (),
15543 .ds (),
15544 .qs (classd_esc_cnt_qs)
15545 );
15546
15547
15548 // R[classd_state]: V(True)
15549 prim_subreg_ext #(
15550 .DW (3)
15551 ) u_classd_state (
15552 .re (classd_state_re),
15553 .we (1'b0),
15554 .wd ('0),
15555 .d (hw2reg.classd_state.d),
15556 .qre (),
15557 .qe (),
15558 .q (),
15559 .ds (),
15560 .qs (classd_state_qs)
15561 );
15562
15563
15564
15565 logic [349:0] addr_hit;
15566 always_comb begin
15567 1/1 addr_hit = '0;
Tests: T1 T2 T3
15568 1/1 addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
Tests: T1 T2 T3
15569 1/1 addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
15570 1/1 addr_hit[ 2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET);
Tests: T1 T2 T3
15571 1/1 addr_hit[ 3] = (reg_addr == ALERT_HANDLER_PING_TIMER_REGWEN_OFFSET);
Tests: T1 T2 T3
15572 1/1 addr_hit[ 4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15573 1/1 addr_hit[ 5] = (reg_addr == ALERT_HANDLER_PING_TIMER_EN_SHADOWED_OFFSET);
Tests: T1 T2 T3
15574 1/1 addr_hit[ 6] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_0_OFFSET);
Tests: T1 T2 T3
15575 1/1 addr_hit[ 7] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_1_OFFSET);
Tests: T1 T2 T3
15576 1/1 addr_hit[ 8] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_2_OFFSET);
Tests: T1 T2 T3
15577 1/1 addr_hit[ 9] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_3_OFFSET);
Tests: T1 T2 T3
15578 1/1 addr_hit[ 10] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_4_OFFSET);
Tests: T1 T2 T3
15579 1/1 addr_hit[ 11] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_5_OFFSET);
Tests: T1 T2 T3
15580 1/1 addr_hit[ 12] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_6_OFFSET);
Tests: T1 T2 T3
15581 1/1 addr_hit[ 13] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_7_OFFSET);
Tests: T1 T2 T3
15582 1/1 addr_hit[ 14] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_8_OFFSET);
Tests: T1 T2 T3
15583 1/1 addr_hit[ 15] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_9_OFFSET);
Tests: T1 T2 T3
15584 1/1 addr_hit[ 16] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_10_OFFSET);
Tests: T1 T2 T3
15585 1/1 addr_hit[ 17] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_11_OFFSET);
Tests: T1 T2 T3
15586 1/1 addr_hit[ 18] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_12_OFFSET);
Tests: T1 T2 T3
15587 1/1 addr_hit[ 19] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_13_OFFSET);
Tests: T1 T2 T3
15588 1/1 addr_hit[ 20] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_14_OFFSET);
Tests: T1 T2 T3
15589 1/1 addr_hit[ 21] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_15_OFFSET);
Tests: T1 T2 T3
15590 1/1 addr_hit[ 22] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_16_OFFSET);
Tests: T1 T2 T3
15591 1/1 addr_hit[ 23] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_17_OFFSET);
Tests: T1 T2 T3
15592 1/1 addr_hit[ 24] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_18_OFFSET);
Tests: T1 T2 T3
15593 1/1 addr_hit[ 25] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_19_OFFSET);
Tests: T1 T2 T3
15594 1/1 addr_hit[ 26] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_20_OFFSET);
Tests: T1 T2 T3
15595 1/1 addr_hit[ 27] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_21_OFFSET);
Tests: T1 T2 T3
15596 1/1 addr_hit[ 28] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_22_OFFSET);
Tests: T1 T2 T3
15597 1/1 addr_hit[ 29] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_23_OFFSET);
Tests: T1 T2 T3
15598 1/1 addr_hit[ 30] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_24_OFFSET);
Tests: T1 T2 T3
15599 1/1 addr_hit[ 31] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_25_OFFSET);
Tests: T1 T2 T3
15600 1/1 addr_hit[ 32] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_26_OFFSET);
Tests: T1 T2 T3
15601 1/1 addr_hit[ 33] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_27_OFFSET);
Tests: T1 T2 T3
15602 1/1 addr_hit[ 34] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_28_OFFSET);
Tests: T1 T2 T3
15603 1/1 addr_hit[ 35] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_29_OFFSET);
Tests: T1 T2 T3
15604 1/1 addr_hit[ 36] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_30_OFFSET);
Tests: T1 T2 T3
15605 1/1 addr_hit[ 37] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_31_OFFSET);
Tests: T1 T2 T3
15606 1/1 addr_hit[ 38] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_32_OFFSET);
Tests: T1 T2 T3
15607 1/1 addr_hit[ 39] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_33_OFFSET);
Tests: T1 T2 T3
15608 1/1 addr_hit[ 40] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_34_OFFSET);
Tests: T1 T2 T3
15609 1/1 addr_hit[ 41] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_35_OFFSET);
Tests: T1 T2 T3
15610 1/1 addr_hit[ 42] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_36_OFFSET);
Tests: T1 T2 T3
15611 1/1 addr_hit[ 43] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_37_OFFSET);
Tests: T1 T2 T3
15612 1/1 addr_hit[ 44] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_38_OFFSET);
Tests: T1 T2 T3
15613 1/1 addr_hit[ 45] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_39_OFFSET);
Tests: T1 T2 T3
15614 1/1 addr_hit[ 46] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_40_OFFSET);
Tests: T1 T2 T3
15615 1/1 addr_hit[ 47] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_41_OFFSET);
Tests: T1 T2 T3
15616 1/1 addr_hit[ 48] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_42_OFFSET);
Tests: T1 T2 T3
15617 1/1 addr_hit[ 49] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_43_OFFSET);
Tests: T1 T2 T3
15618 1/1 addr_hit[ 50] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_44_OFFSET);
Tests: T1 T2 T3
15619 1/1 addr_hit[ 51] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_45_OFFSET);
Tests: T1 T2 T3
15620 1/1 addr_hit[ 52] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_46_OFFSET);
Tests: T1 T2 T3
15621 1/1 addr_hit[ 53] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_47_OFFSET);
Tests: T1 T2 T3
15622 1/1 addr_hit[ 54] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_48_OFFSET);
Tests: T1 T2 T3
15623 1/1 addr_hit[ 55] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_49_OFFSET);
Tests: T1 T2 T3
15624 1/1 addr_hit[ 56] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_50_OFFSET);
Tests: T1 T2 T3
15625 1/1 addr_hit[ 57] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_51_OFFSET);
Tests: T1 T2 T3
15626 1/1 addr_hit[ 58] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_52_OFFSET);
Tests: T1 T2 T3
15627 1/1 addr_hit[ 59] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_53_OFFSET);
Tests: T1 T2 T3
15628 1/1 addr_hit[ 60] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_54_OFFSET);
Tests: T1 T2 T3
15629 1/1 addr_hit[ 61] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_55_OFFSET);
Tests: T1 T2 T3
15630 1/1 addr_hit[ 62] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_56_OFFSET);
Tests: T1 T2 T3
15631 1/1 addr_hit[ 63] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_57_OFFSET);
Tests: T1 T2 T3
15632 1/1 addr_hit[ 64] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_58_OFFSET);
Tests: T1 T2 T3
15633 1/1 addr_hit[ 65] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_59_OFFSET);
Tests: T1 T2 T3
15634 1/1 addr_hit[ 66] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_60_OFFSET);
Tests: T1 T2 T3
15635 1/1 addr_hit[ 67] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_61_OFFSET);
Tests: T1 T2 T3
15636 1/1 addr_hit[ 68] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_62_OFFSET);
Tests: T1 T2 T3
15637 1/1 addr_hit[ 69] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_63_OFFSET);
Tests: T1 T2 T3
15638 1/1 addr_hit[ 70] = (reg_addr == ALERT_HANDLER_ALERT_REGWEN_64_OFFSET);
Tests: T1 T2 T3
15639 1/1 addr_hit[ 71] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_0_OFFSET);
Tests: T1 T2 T3
15640 1/1 addr_hit[ 72] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_1_OFFSET);
Tests: T1 T2 T3
15641 1/1 addr_hit[ 73] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_2_OFFSET);
Tests: T1 T2 T3
15642 1/1 addr_hit[ 74] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_3_OFFSET);
Tests: T1 T2 T3
15643 1/1 addr_hit[ 75] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_4_OFFSET);
Tests: T1 T2 T3
15644 1/1 addr_hit[ 76] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_5_OFFSET);
Tests: T1 T2 T3
15645 1/1 addr_hit[ 77] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_6_OFFSET);
Tests: T1 T2 T3
15646 1/1 addr_hit[ 78] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_7_OFFSET);
Tests: T1 T2 T3
15647 1/1 addr_hit[ 79] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_8_OFFSET);
Tests: T1 T2 T3
15648 1/1 addr_hit[ 80] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_9_OFFSET);
Tests: T1 T2 T3
15649 1/1 addr_hit[ 81] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_10_OFFSET);
Tests: T1 T2 T3
15650 1/1 addr_hit[ 82] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_11_OFFSET);
Tests: T1 T2 T3
15651 1/1 addr_hit[ 83] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_12_OFFSET);
Tests: T1 T2 T3
15652 1/1 addr_hit[ 84] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_13_OFFSET);
Tests: T1 T2 T3
15653 1/1 addr_hit[ 85] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_14_OFFSET);
Tests: T1 T2 T3
15654 1/1 addr_hit[ 86] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_15_OFFSET);
Tests: T1 T2 T3
15655 1/1 addr_hit[ 87] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_16_OFFSET);
Tests: T1 T2 T3
15656 1/1 addr_hit[ 88] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_17_OFFSET);
Tests: T1 T2 T3
15657 1/1 addr_hit[ 89] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_18_OFFSET);
Tests: T1 T2 T3
15658 1/1 addr_hit[ 90] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_19_OFFSET);
Tests: T1 T2 T3
15659 1/1 addr_hit[ 91] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_20_OFFSET);
Tests: T1 T2 T3
15660 1/1 addr_hit[ 92] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_21_OFFSET);
Tests: T1 T2 T3
15661 1/1 addr_hit[ 93] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_22_OFFSET);
Tests: T1 T2 T3
15662 1/1 addr_hit[ 94] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_23_OFFSET);
Tests: T1 T2 T3
15663 1/1 addr_hit[ 95] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_24_OFFSET);
Tests: T1 T2 T3
15664 1/1 addr_hit[ 96] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_25_OFFSET);
Tests: T1 T2 T3
15665 1/1 addr_hit[ 97] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_26_OFFSET);
Tests: T1 T2 T3
15666 1/1 addr_hit[ 98] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_27_OFFSET);
Tests: T1 T2 T3
15667 1/1 addr_hit[ 99] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_28_OFFSET);
Tests: T1 T2 T3
15668 1/1 addr_hit[100] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_29_OFFSET);
Tests: T1 T2 T3
15669 1/1 addr_hit[101] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_30_OFFSET);
Tests: T1 T2 T3
15670 1/1 addr_hit[102] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_31_OFFSET);
Tests: T1 T2 T3
15671 1/1 addr_hit[103] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_32_OFFSET);
Tests: T1 T2 T3
15672 1/1 addr_hit[104] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_33_OFFSET);
Tests: T1 T2 T3
15673 1/1 addr_hit[105] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_34_OFFSET);
Tests: T1 T2 T3
15674 1/1 addr_hit[106] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_35_OFFSET);
Tests: T1 T2 T3
15675 1/1 addr_hit[107] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_36_OFFSET);
Tests: T1 T2 T3
15676 1/1 addr_hit[108] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_37_OFFSET);
Tests: T1 T2 T3
15677 1/1 addr_hit[109] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_38_OFFSET);
Tests: T1 T2 T3
15678 1/1 addr_hit[110] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_39_OFFSET);
Tests: T1 T2 T3
15679 1/1 addr_hit[111] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_40_OFFSET);
Tests: T1 T2 T3
15680 1/1 addr_hit[112] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_41_OFFSET);
Tests: T1 T2 T3
15681 1/1 addr_hit[113] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_42_OFFSET);
Tests: T1 T2 T3
15682 1/1 addr_hit[114] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_43_OFFSET);
Tests: T1 T2 T3
15683 1/1 addr_hit[115] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_44_OFFSET);
Tests: T1 T2 T3
15684 1/1 addr_hit[116] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_45_OFFSET);
Tests: T1 T2 T3
15685 1/1 addr_hit[117] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_46_OFFSET);
Tests: T1 T2 T3
15686 1/1 addr_hit[118] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_47_OFFSET);
Tests: T1 T2 T3
15687 1/1 addr_hit[119] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_48_OFFSET);
Tests: T1 T2 T3
15688 1/1 addr_hit[120] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_49_OFFSET);
Tests: T1 T2 T3
15689 1/1 addr_hit[121] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_50_OFFSET);
Tests: T1 T2 T3
15690 1/1 addr_hit[122] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_51_OFFSET);
Tests: T1 T2 T3
15691 1/1 addr_hit[123] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_52_OFFSET);
Tests: T1 T2 T3
15692 1/1 addr_hit[124] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_53_OFFSET);
Tests: T1 T2 T3
15693 1/1 addr_hit[125] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_54_OFFSET);
Tests: T1 T2 T3
15694 1/1 addr_hit[126] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_55_OFFSET);
Tests: T1 T2 T3
15695 1/1 addr_hit[127] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_56_OFFSET);
Tests: T1 T2 T3
15696 1/1 addr_hit[128] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_57_OFFSET);
Tests: T1 T2 T3
15697 1/1 addr_hit[129] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_58_OFFSET);
Tests: T1 T2 T3
15698 1/1 addr_hit[130] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_59_OFFSET);
Tests: T1 T2 T3
15699 1/1 addr_hit[131] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_60_OFFSET);
Tests: T1 T2 T3
15700 1/1 addr_hit[132] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_61_OFFSET);
Tests: T1 T2 T3
15701 1/1 addr_hit[133] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_62_OFFSET);
Tests: T1 T2 T3
15702 1/1 addr_hit[134] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_63_OFFSET);
Tests: T1 T2 T3
15703 1/1 addr_hit[135] = (reg_addr == ALERT_HANDLER_ALERT_EN_SHADOWED_64_OFFSET);
Tests: T1 T2 T3
15704 1/1 addr_hit[136] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_0_OFFSET);
Tests: T1 T2 T3
15705 1/1 addr_hit[137] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_1_OFFSET);
Tests: T1 T2 T3
15706 1/1 addr_hit[138] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_2_OFFSET);
Tests: T1 T2 T3
15707 1/1 addr_hit[139] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_3_OFFSET);
Tests: T1 T2 T3
15708 1/1 addr_hit[140] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_4_OFFSET);
Tests: T1 T2 T3
15709 1/1 addr_hit[141] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_5_OFFSET);
Tests: T1 T2 T3
15710 1/1 addr_hit[142] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_6_OFFSET);
Tests: T1 T2 T3
15711 1/1 addr_hit[143] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_7_OFFSET);
Tests: T1 T2 T3
15712 1/1 addr_hit[144] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_8_OFFSET);
Tests: T1 T2 T3
15713 1/1 addr_hit[145] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_9_OFFSET);
Tests: T1 T2 T3
15714 1/1 addr_hit[146] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_10_OFFSET);
Tests: T1 T2 T3
15715 1/1 addr_hit[147] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_11_OFFSET);
Tests: T1 T2 T3
15716 1/1 addr_hit[148] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_12_OFFSET);
Tests: T1 T2 T3
15717 1/1 addr_hit[149] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_13_OFFSET);
Tests: T1 T2 T3
15718 1/1 addr_hit[150] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_14_OFFSET);
Tests: T1 T2 T3
15719 1/1 addr_hit[151] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_15_OFFSET);
Tests: T1 T2 T3
15720 1/1 addr_hit[152] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_16_OFFSET);
Tests: T1 T2 T3
15721 1/1 addr_hit[153] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_17_OFFSET);
Tests: T1 T2 T3
15722 1/1 addr_hit[154] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_18_OFFSET);
Tests: T1 T2 T3
15723 1/1 addr_hit[155] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_19_OFFSET);
Tests: T1 T2 T3
15724 1/1 addr_hit[156] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_20_OFFSET);
Tests: T1 T2 T3
15725 1/1 addr_hit[157] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_21_OFFSET);
Tests: T1 T2 T3
15726 1/1 addr_hit[158] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_22_OFFSET);
Tests: T1 T2 T3
15727 1/1 addr_hit[159] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_23_OFFSET);
Tests: T1 T2 T3
15728 1/1 addr_hit[160] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_24_OFFSET);
Tests: T1 T2 T3
15729 1/1 addr_hit[161] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_25_OFFSET);
Tests: T1 T2 T3
15730 1/1 addr_hit[162] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_26_OFFSET);
Tests: T1 T2 T3
15731 1/1 addr_hit[163] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_27_OFFSET);
Tests: T1 T2 T3
15732 1/1 addr_hit[164] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_28_OFFSET);
Tests: T1 T2 T3
15733 1/1 addr_hit[165] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_29_OFFSET);
Tests: T1 T2 T3
15734 1/1 addr_hit[166] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_30_OFFSET);
Tests: T1 T2 T3
15735 1/1 addr_hit[167] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_31_OFFSET);
Tests: T1 T2 T3
15736 1/1 addr_hit[168] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_32_OFFSET);
Tests: T1 T2 T3
15737 1/1 addr_hit[169] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_33_OFFSET);
Tests: T1 T2 T3
15738 1/1 addr_hit[170] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_34_OFFSET);
Tests: T1 T2 T3
15739 1/1 addr_hit[171] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_35_OFFSET);
Tests: T1 T2 T3
15740 1/1 addr_hit[172] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_36_OFFSET);
Tests: T1 T2 T3
15741 1/1 addr_hit[173] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_37_OFFSET);
Tests: T1 T2 T3
15742 1/1 addr_hit[174] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_38_OFFSET);
Tests: T1 T2 T3
15743 1/1 addr_hit[175] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_39_OFFSET);
Tests: T1 T2 T3
15744 1/1 addr_hit[176] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_40_OFFSET);
Tests: T1 T2 T3
15745 1/1 addr_hit[177] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_41_OFFSET);
Tests: T1 T2 T3
15746 1/1 addr_hit[178] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_42_OFFSET);
Tests: T1 T2 T3
15747 1/1 addr_hit[179] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_43_OFFSET);
Tests: T1 T2 T3
15748 1/1 addr_hit[180] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_44_OFFSET);
Tests: T1 T2 T3
15749 1/1 addr_hit[181] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_45_OFFSET);
Tests: T1 T2 T3
15750 1/1 addr_hit[182] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_46_OFFSET);
Tests: T1 T2 T3
15751 1/1 addr_hit[183] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_47_OFFSET);
Tests: T1 T2 T3
15752 1/1 addr_hit[184] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_48_OFFSET);
Tests: T1 T2 T3
15753 1/1 addr_hit[185] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_49_OFFSET);
Tests: T1 T2 T3
15754 1/1 addr_hit[186] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_50_OFFSET);
Tests: T1 T2 T3
15755 1/1 addr_hit[187] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_51_OFFSET);
Tests: T1 T2 T3
15756 1/1 addr_hit[188] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_52_OFFSET);
Tests: T1 T2 T3
15757 1/1 addr_hit[189] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_53_OFFSET);
Tests: T1 T2 T3
15758 1/1 addr_hit[190] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_54_OFFSET);
Tests: T1 T2 T3
15759 1/1 addr_hit[191] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_55_OFFSET);
Tests: T1 T2 T3
15760 1/1 addr_hit[192] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_56_OFFSET);
Tests: T1 T2 T3
15761 1/1 addr_hit[193] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_57_OFFSET);
Tests: T1 T2 T3
15762 1/1 addr_hit[194] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_58_OFFSET);
Tests: T1 T2 T3
15763 1/1 addr_hit[195] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_59_OFFSET);
Tests: T1 T2 T3
15764 1/1 addr_hit[196] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_60_OFFSET);
Tests: T1 T2 T3
15765 1/1 addr_hit[197] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_61_OFFSET);
Tests: T1 T2 T3
15766 1/1 addr_hit[198] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_62_OFFSET);
Tests: T1 T2 T3
15767 1/1 addr_hit[199] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_63_OFFSET);
Tests: T1 T2 T3
15768 1/1 addr_hit[200] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_SHADOWED_64_OFFSET);
Tests: T1 T2 T3
15769 1/1 addr_hit[201] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_0_OFFSET);
Tests: T1 T2 T3
15770 1/1 addr_hit[202] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_1_OFFSET);
Tests: T1 T2 T3
15771 1/1 addr_hit[203] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_2_OFFSET);
Tests: T1 T2 T3
15772 1/1 addr_hit[204] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_3_OFFSET);
Tests: T1 T2 T3
15773 1/1 addr_hit[205] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_4_OFFSET);
Tests: T1 T2 T3
15774 1/1 addr_hit[206] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_5_OFFSET);
Tests: T1 T2 T3
15775 1/1 addr_hit[207] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_6_OFFSET);
Tests: T1 T2 T3
15776 1/1 addr_hit[208] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_7_OFFSET);
Tests: T1 T2 T3
15777 1/1 addr_hit[209] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_8_OFFSET);
Tests: T1 T2 T3
15778 1/1 addr_hit[210] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_9_OFFSET);
Tests: T1 T2 T3
15779 1/1 addr_hit[211] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_10_OFFSET);
Tests: T1 T2 T3
15780 1/1 addr_hit[212] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_11_OFFSET);
Tests: T1 T2 T3
15781 1/1 addr_hit[213] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_12_OFFSET);
Tests: T1 T2 T3
15782 1/1 addr_hit[214] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_13_OFFSET);
Tests: T1 T2 T3
15783 1/1 addr_hit[215] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_14_OFFSET);
Tests: T1 T2 T3
15784 1/1 addr_hit[216] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_15_OFFSET);
Tests: T1 T2 T3
15785 1/1 addr_hit[217] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_16_OFFSET);
Tests: T1 T2 T3
15786 1/1 addr_hit[218] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_17_OFFSET);
Tests: T1 T2 T3
15787 1/1 addr_hit[219] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_18_OFFSET);
Tests: T1 T2 T3
15788 1/1 addr_hit[220] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_19_OFFSET);
Tests: T1 T2 T3
15789 1/1 addr_hit[221] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_20_OFFSET);
Tests: T1 T2 T3
15790 1/1 addr_hit[222] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_21_OFFSET);
Tests: T1 T2 T3
15791 1/1 addr_hit[223] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_22_OFFSET);
Tests: T1 T2 T3
15792 1/1 addr_hit[224] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_23_OFFSET);
Tests: T1 T2 T3
15793 1/1 addr_hit[225] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_24_OFFSET);
Tests: T1 T2 T3
15794 1/1 addr_hit[226] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_25_OFFSET);
Tests: T1 T2 T3
15795 1/1 addr_hit[227] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_26_OFFSET);
Tests: T1 T2 T3
15796 1/1 addr_hit[228] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_27_OFFSET);
Tests: T1 T2 T3
15797 1/1 addr_hit[229] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_28_OFFSET);
Tests: T1 T2 T3
15798 1/1 addr_hit[230] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_29_OFFSET);
Tests: T1 T2 T3
15799 1/1 addr_hit[231] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_30_OFFSET);
Tests: T1 T2 T3
15800 1/1 addr_hit[232] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_31_OFFSET);
Tests: T1 T2 T3
15801 1/1 addr_hit[233] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_32_OFFSET);
Tests: T1 T2 T3
15802 1/1 addr_hit[234] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_33_OFFSET);
Tests: T1 T2 T3
15803 1/1 addr_hit[235] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_34_OFFSET);
Tests: T1 T2 T3
15804 1/1 addr_hit[236] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_35_OFFSET);
Tests: T1 T2 T3
15805 1/1 addr_hit[237] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_36_OFFSET);
Tests: T1 T2 T3
15806 1/1 addr_hit[238] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_37_OFFSET);
Tests: T1 T2 T3
15807 1/1 addr_hit[239] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_38_OFFSET);
Tests: T1 T2 T3
15808 1/1 addr_hit[240] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_39_OFFSET);
Tests: T1 T2 T3
15809 1/1 addr_hit[241] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_40_OFFSET);
Tests: T1 T2 T3
15810 1/1 addr_hit[242] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_41_OFFSET);
Tests: T1 T2 T3
15811 1/1 addr_hit[243] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_42_OFFSET);
Tests: T1 T2 T3
15812 1/1 addr_hit[244] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_43_OFFSET);
Tests: T1 T2 T3
15813 1/1 addr_hit[245] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_44_OFFSET);
Tests: T1 T2 T3
15814 1/1 addr_hit[246] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_45_OFFSET);
Tests: T1 T2 T3
15815 1/1 addr_hit[247] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_46_OFFSET);
Tests: T1 T2 T3
15816 1/1 addr_hit[248] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_47_OFFSET);
Tests: T1 T2 T3
15817 1/1 addr_hit[249] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_48_OFFSET);
Tests: T1 T2 T3
15818 1/1 addr_hit[250] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_49_OFFSET);
Tests: T1 T2 T3
15819 1/1 addr_hit[251] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_50_OFFSET);
Tests: T1 T2 T3
15820 1/1 addr_hit[252] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_51_OFFSET);
Tests: T1 T2 T3
15821 1/1 addr_hit[253] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_52_OFFSET);
Tests: T1 T2 T3
15822 1/1 addr_hit[254] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_53_OFFSET);
Tests: T1 T2 T3
15823 1/1 addr_hit[255] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_54_OFFSET);
Tests: T1 T2 T3
15824 1/1 addr_hit[256] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_55_OFFSET);
Tests: T1 T2 T3
15825 1/1 addr_hit[257] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_56_OFFSET);
Tests: T1 T2 T3
15826 1/1 addr_hit[258] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_57_OFFSET);
Tests: T1 T2 T3
15827 1/1 addr_hit[259] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_58_OFFSET);
Tests: T1 T2 T3
15828 1/1 addr_hit[260] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_59_OFFSET);
Tests: T1 T2 T3
15829 1/1 addr_hit[261] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_60_OFFSET);
Tests: T1 T2 T3
15830 1/1 addr_hit[262] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_61_OFFSET);
Tests: T1 T2 T3
15831 1/1 addr_hit[263] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_62_OFFSET);
Tests: T1 T2 T3
15832 1/1 addr_hit[264] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_63_OFFSET);
Tests: T1 T2 T3
15833 1/1 addr_hit[265] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_64_OFFSET);
Tests: T1 T2 T3
15834 1/1 addr_hit[266] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_0_OFFSET);
Tests: T1 T2 T3
15835 1/1 addr_hit[267] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_1_OFFSET);
Tests: T1 T2 T3
15836 1/1 addr_hit[268] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_2_OFFSET);
Tests: T1 T2 T3
15837 1/1 addr_hit[269] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_3_OFFSET);
Tests: T1 T2 T3
15838 1/1 addr_hit[270] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_4_OFFSET);
Tests: T1 T2 T3
15839 1/1 addr_hit[271] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_5_OFFSET);
Tests: T1 T2 T3
15840 1/1 addr_hit[272] = (reg_addr == ALERT_HANDLER_LOC_ALERT_REGWEN_6_OFFSET);
Tests: T1 T2 T3
15841 1/1 addr_hit[273] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_0_OFFSET);
Tests: T1 T2 T3
15842 1/1 addr_hit[274] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_1_OFFSET);
Tests: T1 T2 T3
15843 1/1 addr_hit[275] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_2_OFFSET);
Tests: T1 T2 T3
15844 1/1 addr_hit[276] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_3_OFFSET);
Tests: T1 T2 T3
15845 1/1 addr_hit[277] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_4_OFFSET);
Tests: T1 T2 T3
15846 1/1 addr_hit[278] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_5_OFFSET);
Tests: T1 T2 T3
15847 1/1 addr_hit[279] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_SHADOWED_6_OFFSET);
Tests: T1 T2 T3
15848 1/1 addr_hit[280] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_0_OFFSET);
Tests: T1 T2 T3
15849 1/1 addr_hit[281] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_1_OFFSET);
Tests: T1 T2 T3
15850 1/1 addr_hit[282] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_2_OFFSET);
Tests: T1 T2 T3
15851 1/1 addr_hit[283] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_3_OFFSET);
Tests: T1 T2 T3
15852 1/1 addr_hit[284] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_4_OFFSET);
Tests: T1 T2 T3
15853 1/1 addr_hit[285] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_5_OFFSET);
Tests: T1 T2 T3
15854 1/1 addr_hit[286] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_SHADOWED_6_OFFSET);
Tests: T1 T2 T3
15855 1/1 addr_hit[287] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_0_OFFSET);
Tests: T1 T2 T3
15856 1/1 addr_hit[288] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_1_OFFSET);
Tests: T1 T2 T3
15857 1/1 addr_hit[289] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_2_OFFSET);
Tests: T1 T2 T3
15858 1/1 addr_hit[290] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_3_OFFSET);
Tests: T1 T2 T3
15859 1/1 addr_hit[291] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_4_OFFSET);
Tests: T1 T2 T3
15860 1/1 addr_hit[292] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_5_OFFSET);
Tests: T1 T2 T3
15861 1/1 addr_hit[293] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_6_OFFSET);
Tests: T1 T2 T3
15862 1/1 addr_hit[294] = (reg_addr == ALERT_HANDLER_CLASSA_REGWEN_OFFSET);
Tests: T1 T2 T3
15863 1/1 addr_hit[295] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_SHADOWED_OFFSET);
Tests: T1 T2 T3
15864 1/1 addr_hit[296] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_REGWEN_OFFSET);
Tests: T1 T2 T3
15865 1/1 addr_hit[297] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_SHADOWED_OFFSET);
Tests: T1 T2 T3
15866 1/1 addr_hit[298] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
Tests: T1 T2 T3
15867 1/1 addr_hit[299] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_SHADOWED_OFFSET);
Tests: T1 T2 T3
15868 1/1 addr_hit[300] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15869 1/1 addr_hit[301] = (reg_addr == ALERT_HANDLER_CLASSA_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
Tests: T1 T2 T3
15870 1/1 addr_hit[302] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15871 1/1 addr_hit[303] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15872 1/1 addr_hit[304] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15873 1/1 addr_hit[305] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15874 1/1 addr_hit[306] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
Tests: T1 T2 T3
15875 1/1 addr_hit[307] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
Tests: T1 T2 T3
15876 1/1 addr_hit[308] = (reg_addr == ALERT_HANDLER_CLASSB_REGWEN_OFFSET);
Tests: T1 T2 T3
15877 1/1 addr_hit[309] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_SHADOWED_OFFSET);
Tests: T1 T2 T3
15878 1/1 addr_hit[310] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_REGWEN_OFFSET);
Tests: T1 T2 T3
15879 1/1 addr_hit[311] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_SHADOWED_OFFSET);
Tests: T1 T2 T3
15880 1/1 addr_hit[312] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
Tests: T1 T2 T3
15881 1/1 addr_hit[313] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_SHADOWED_OFFSET);
Tests: T1 T2 T3
15882 1/1 addr_hit[314] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15883 1/1 addr_hit[315] = (reg_addr == ALERT_HANDLER_CLASSB_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
Tests: T1 T2 T3
15884 1/1 addr_hit[316] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15885 1/1 addr_hit[317] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15886 1/1 addr_hit[318] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15887 1/1 addr_hit[319] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15888 1/1 addr_hit[320] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
Tests: T1 T2 T3
15889 1/1 addr_hit[321] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
Tests: T1 T2 T3
15890 1/1 addr_hit[322] = (reg_addr == ALERT_HANDLER_CLASSC_REGWEN_OFFSET);
Tests: T1 T2 T3
15891 1/1 addr_hit[323] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_SHADOWED_OFFSET);
Tests: T1 T2 T3
15892 1/1 addr_hit[324] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_REGWEN_OFFSET);
Tests: T1 T2 T3
15893 1/1 addr_hit[325] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_SHADOWED_OFFSET);
Tests: T1 T2 T3
15894 1/1 addr_hit[326] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
Tests: T1 T2 T3
15895 1/1 addr_hit[327] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_SHADOWED_OFFSET);
Tests: T1 T2 T3
15896 1/1 addr_hit[328] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15897 1/1 addr_hit[329] = (reg_addr == ALERT_HANDLER_CLASSC_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
Tests: T1 T2 T3
15898 1/1 addr_hit[330] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15899 1/1 addr_hit[331] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15900 1/1 addr_hit[332] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15901 1/1 addr_hit[333] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15902 1/1 addr_hit[334] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
Tests: T1 T2 T3
15903 1/1 addr_hit[335] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
Tests: T1 T2 T3
15904 1/1 addr_hit[336] = (reg_addr == ALERT_HANDLER_CLASSD_REGWEN_OFFSET);
Tests: T1 T2 T3
15905 1/1 addr_hit[337] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_SHADOWED_OFFSET);
Tests: T1 T2 T3
15906 1/1 addr_hit[338] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_REGWEN_OFFSET);
Tests: T1 T2 T3
15907 1/1 addr_hit[339] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_SHADOWED_OFFSET);
Tests: T1 T2 T3
15908 1/1 addr_hit[340] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
Tests: T1 T2 T3
15909 1/1 addr_hit[341] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_SHADOWED_OFFSET);
Tests: T1 T2 T3
15910 1/1 addr_hit[342] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15911 1/1 addr_hit[343] = (reg_addr == ALERT_HANDLER_CLASSD_CRASHDUMP_TRIGGER_SHADOWED_OFFSET);
Tests: T1 T2 T3
15912 1/1 addr_hit[344] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15913 1/1 addr_hit[345] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15914 1/1 addr_hit[346] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15915 1/1 addr_hit[347] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_SHADOWED_OFFSET);
Tests: T1 T2 T3
15916 1/1 addr_hit[348] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
Tests: T1 T2 T3
15917 1/1 addr_hit[349] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
Tests: T1 T2 T3
15918 end
15919
15920 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
15921
15922 // Check sub-word write is permitted
15923 always_comb begin
15924 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
15925 ((addr_hit[ 0] & (|(ALERT_HANDLER_PERMIT[ 0] & ~reg_be))) |
15926 (addr_hit[ 1] & (|(ALERT_HANDLER_PERMIT[ 1] & ~reg_be))) |
15927 (addr_hit[ 2] & (|(ALERT_HANDLER_PERMIT[ 2] & ~reg_be))) |
15928 (addr_hit[ 3] & (|(ALERT_HANDLER_PERMIT[ 3] & ~reg_be))) |
15929 (addr_hit[ 4] & (|(ALERT_HANDLER_PERMIT[ 4] & ~reg_be))) |
15930 (addr_hit[ 5] & (|(ALERT_HANDLER_PERMIT[ 5] & ~reg_be))) |
15931 (addr_hit[ 6] & (|(ALERT_HANDLER_PERMIT[ 6] & ~reg_be))) |
15932 (addr_hit[ 7] & (|(ALERT_HANDLER_PERMIT[ 7] & ~reg_be))) |
15933 (addr_hit[ 8] & (|(ALERT_HANDLER_PERMIT[ 8] & ~reg_be))) |
15934 (addr_hit[ 9] & (|(ALERT_HANDLER_PERMIT[ 9] & ~reg_be))) |
15935 (addr_hit[ 10] & (|(ALERT_HANDLER_PERMIT[ 10] & ~reg_be))) |
15936 (addr_hit[ 11] & (|(ALERT_HANDLER_PERMIT[ 11] & ~reg_be))) |
15937 (addr_hit[ 12] & (|(ALERT_HANDLER_PERMIT[ 12] & ~reg_be))) |
15938 (addr_hit[ 13] & (|(ALERT_HANDLER_PERMIT[ 13] & ~reg_be))) |
15939 (addr_hit[ 14] & (|(ALERT_HANDLER_PERMIT[ 14] & ~reg_be))) |
15940 (addr_hit[ 15] & (|(ALERT_HANDLER_PERMIT[ 15] & ~reg_be))) |
15941 (addr_hit[ 16] & (|(ALERT_HANDLER_PERMIT[ 16] & ~reg_be))) |
15942 (addr_hit[ 17] & (|(ALERT_HANDLER_PERMIT[ 17] & ~reg_be))) |
15943 (addr_hit[ 18] & (|(ALERT_HANDLER_PERMIT[ 18] & ~reg_be))) |
15944 (addr_hit[ 19] & (|(ALERT_HANDLER_PERMIT[ 19] & ~reg_be))) |
15945 (addr_hit[ 20] & (|(ALERT_HANDLER_PERMIT[ 20] & ~reg_be))) |
15946 (addr_hit[ 21] & (|(ALERT_HANDLER_PERMIT[ 21] & ~reg_be))) |
15947 (addr_hit[ 22] & (|(ALERT_HANDLER_PERMIT[ 22] & ~reg_be))) |
15948 (addr_hit[ 23] & (|(ALERT_HANDLER_PERMIT[ 23] & ~reg_be))) |
15949 (addr_hit[ 24] & (|(ALERT_HANDLER_PERMIT[ 24] & ~reg_be))) |
15950 (addr_hit[ 25] & (|(ALERT_HANDLER_PERMIT[ 25] & ~reg_be))) |
15951 (addr_hit[ 26] & (|(ALERT_HANDLER_PERMIT[ 26] & ~reg_be))) |
15952 (addr_hit[ 27] & (|(ALERT_HANDLER_PERMIT[ 27] & ~reg_be))) |
15953 (addr_hit[ 28] & (|(ALERT_HANDLER_PERMIT[ 28] & ~reg_be))) |
15954 (addr_hit[ 29] & (|(ALERT_HANDLER_PERMIT[ 29] & ~reg_be))) |
15955 (addr_hit[ 30] & (|(ALERT_HANDLER_PERMIT[ 30] & ~reg_be))) |
15956 (addr_hit[ 31] & (|(ALERT_HANDLER_PERMIT[ 31] & ~reg_be))) |
15957 (addr_hit[ 32] & (|(ALERT_HANDLER_PERMIT[ 32] & ~reg_be))) |
15958 (addr_hit[ 33] & (|(ALERT_HANDLER_PERMIT[ 33] & ~reg_be))) |
15959 (addr_hit[ 34] & (|(ALERT_HANDLER_PERMIT[ 34] & ~reg_be))) |
15960 (addr_hit[ 35] & (|(ALERT_HANDLER_PERMIT[ 35] & ~reg_be))) |
15961 (addr_hit[ 36] & (|(ALERT_HANDLER_PERMIT[ 36] & ~reg_be))) |
15962 (addr_hit[ 37] & (|(ALERT_HANDLER_PERMIT[ 37] & ~reg_be))) |
15963 (addr_hit[ 38] & (|(ALERT_HANDLER_PERMIT[ 38] & ~reg_be))) |
15964 (addr_hit[ 39] & (|(ALERT_HANDLER_PERMIT[ 39] & ~reg_be))) |
15965 (addr_hit[ 40] & (|(ALERT_HANDLER_PERMIT[ 40] & ~reg_be))) |
15966 (addr_hit[ 41] & (|(ALERT_HANDLER_PERMIT[ 41] & ~reg_be))) |
15967 (addr_hit[ 42] & (|(ALERT_HANDLER_PERMIT[ 42] & ~reg_be))) |
15968 (addr_hit[ 43] & (|(ALERT_HANDLER_PERMIT[ 43] & ~reg_be))) |
15969 (addr_hit[ 44] & (|(ALERT_HANDLER_PERMIT[ 44] & ~reg_be))) |
15970 (addr_hit[ 45] & (|(ALERT_HANDLER_PERMIT[ 45] & ~reg_be))) |
15971 (addr_hit[ 46] & (|(ALERT_HANDLER_PERMIT[ 46] & ~reg_be))) |
15972 (addr_hit[ 47] & (|(ALERT_HANDLER_PERMIT[ 47] & ~reg_be))) |
15973 (addr_hit[ 48] & (|(ALERT_HANDLER_PERMIT[ 48] & ~reg_be))) |
15974 (addr_hit[ 49] & (|(ALERT_HANDLER_PERMIT[ 49] & ~reg_be))) |
15975 (addr_hit[ 50] & (|(ALERT_HANDLER_PERMIT[ 50] & ~reg_be))) |
15976 (addr_hit[ 51] & (|(ALERT_HANDLER_PERMIT[ 51] & ~reg_be))) |
15977 (addr_hit[ 52] & (|(ALERT_HANDLER_PERMIT[ 52] & ~reg_be))) |
15978 (addr_hit[ 53] & (|(ALERT_HANDLER_PERMIT[ 53] & ~reg_be))) |
15979 (addr_hit[ 54] & (|(ALERT_HANDLER_PERMIT[ 54] & ~reg_be))) |
15980 (addr_hit[ 55] & (|(ALERT_HANDLER_PERMIT[ 55] & ~reg_be))) |
15981 (addr_hit[ 56] & (|(ALERT_HANDLER_PERMIT[ 56] & ~reg_be))) |
15982 (addr_hit[ 57] & (|(ALERT_HANDLER_PERMIT[ 57] & ~reg_be))) |
15983 (addr_hit[ 58] & (|(ALERT_HANDLER_PERMIT[ 58] & ~reg_be))) |
15984 (addr_hit[ 59] & (|(ALERT_HANDLER_PERMIT[ 59] & ~reg_be))) |
15985 (addr_hit[ 60] & (|(ALERT_HANDLER_PERMIT[ 60] & ~reg_be))) |
15986 (addr_hit[ 61] & (|(ALERT_HANDLER_PERMIT[ 61] & ~reg_be))) |
15987 (addr_hit[ 62] & (|(ALERT_HANDLER_PERMIT[ 62] & ~reg_be))) |
15988 (addr_hit[ 63] & (|(ALERT_HANDLER_PERMIT[ 63] & ~reg_be))) |
15989 (addr_hit[ 64] & (|(ALERT_HANDLER_PERMIT[ 64] & ~reg_be))) |
15990 (addr_hit[ 65] & (|(ALERT_HANDLER_PERMIT[ 65] & ~reg_be))) |
15991 (addr_hit[ 66] & (|(ALERT_HANDLER_PERMIT[ 66] & ~reg_be))) |
15992 (addr_hit[ 67] & (|(ALERT_HANDLER_PERMIT[ 67] & ~reg_be))) |
15993 (addr_hit[ 68] & (|(ALERT_HANDLER_PERMIT[ 68] & ~reg_be))) |
15994 (addr_hit[ 69] & (|(ALERT_HANDLER_PERMIT[ 69] & ~reg_be))) |
15995 (addr_hit[ 70] & (|(ALERT_HANDLER_PERMIT[ 70] & ~reg_be))) |
15996 (addr_hit[ 71] & (|(ALERT_HANDLER_PERMIT[ 71] & ~reg_be))) |
15997 (addr_hit[ 72] & (|(ALERT_HANDLER_PERMIT[ 72] & ~reg_be))) |
15998 (addr_hit[ 73] & (|(ALERT_HANDLER_PERMIT[ 73] & ~reg_be))) |
15999 (addr_hit[ 74] & (|(ALERT_HANDLER_PERMIT[ 74] & ~reg_be))) |
16000 (addr_hit[ 75] & (|(ALERT_HANDLER_PERMIT[ 75] & ~reg_be))) |
16001 (addr_hit[ 76] & (|(ALERT_HANDLER_PERMIT[ 76] & ~reg_be))) |
16002 (addr_hit[ 77] & (|(ALERT_HANDLER_PERMIT[ 77] & ~reg_be))) |
16003 (addr_hit[ 78] & (|(ALERT_HANDLER_PERMIT[ 78] & ~reg_be))) |
16004 (addr_hit[ 79] & (|(ALERT_HANDLER_PERMIT[ 79] & ~reg_be))) |
16005 (addr_hit[ 80] & (|(ALERT_HANDLER_PERMIT[ 80] & ~reg_be))) |
16006 (addr_hit[ 81] & (|(ALERT_HANDLER_PERMIT[ 81] & ~reg_be))) |
16007 (addr_hit[ 82] & (|(ALERT_HANDLER_PERMIT[ 82] & ~reg_be))) |
16008 (addr_hit[ 83] & (|(ALERT_HANDLER_PERMIT[ 83] & ~reg_be))) |
16009 (addr_hit[ 84] & (|(ALERT_HANDLER_PERMIT[ 84] & ~reg_be))) |
16010 (addr_hit[ 85] & (|(ALERT_HANDLER_PERMIT[ 85] & ~reg_be))) |
16011 (addr_hit[ 86] & (|(ALERT_HANDLER_PERMIT[ 86] & ~reg_be))) |
16012 (addr_hit[ 87] & (|(ALERT_HANDLER_PERMIT[ 87] & ~reg_be))) |
16013 (addr_hit[ 88] & (|(ALERT_HANDLER_PERMIT[ 88] & ~reg_be))) |
16014 (addr_hit[ 89] & (|(ALERT_HANDLER_PERMIT[ 89] & ~reg_be))) |
16015 (addr_hit[ 90] & (|(ALERT_HANDLER_PERMIT[ 90] & ~reg_be))) |
16016 (addr_hit[ 91] & (|(ALERT_HANDLER_PERMIT[ 91] & ~reg_be))) |
16017 (addr_hit[ 92] & (|(ALERT_HANDLER_PERMIT[ 92] & ~reg_be))) |
16018 (addr_hit[ 93] & (|(ALERT_HANDLER_PERMIT[ 93] & ~reg_be))) |
16019 (addr_hit[ 94] & (|(ALERT_HANDLER_PERMIT[ 94] & ~reg_be))) |
16020 (addr_hit[ 95] & (|(ALERT_HANDLER_PERMIT[ 95] & ~reg_be))) |
16021 (addr_hit[ 96] & (|(ALERT_HANDLER_PERMIT[ 96] & ~reg_be))) |
16022 (addr_hit[ 97] & (|(ALERT_HANDLER_PERMIT[ 97] & ~reg_be))) |
16023 (addr_hit[ 98] & (|(ALERT_HANDLER_PERMIT[ 98] & ~reg_be))) |
16024 (addr_hit[ 99] & (|(ALERT_HANDLER_PERMIT[ 99] & ~reg_be))) |
16025 (addr_hit[100] & (|(ALERT_HANDLER_PERMIT[100] & ~reg_be))) |
16026 (addr_hit[101] & (|(ALERT_HANDLER_PERMIT[101] & ~reg_be))) |
16027 (addr_hit[102] & (|(ALERT_HANDLER_PERMIT[102] & ~reg_be))) |
16028 (addr_hit[103] & (|(ALERT_HANDLER_PERMIT[103] & ~reg_be))) |
16029 (addr_hit[104] & (|(ALERT_HANDLER_PERMIT[104] & ~reg_be))) |
16030 (addr_hit[105] & (|(ALERT_HANDLER_PERMIT[105] & ~reg_be))) |
16031 (addr_hit[106] & (|(ALERT_HANDLER_PERMIT[106] & ~reg_be))) |
16032 (addr_hit[107] & (|(ALERT_HANDLER_PERMIT[107] & ~reg_be))) |
16033 (addr_hit[108] & (|(ALERT_HANDLER_PERMIT[108] & ~reg_be))) |
16034 (addr_hit[109] & (|(ALERT_HANDLER_PERMIT[109] & ~reg_be))) |
16035 (addr_hit[110] & (|(ALERT_HANDLER_PERMIT[110] & ~reg_be))) |
16036 (addr_hit[111] & (|(ALERT_HANDLER_PERMIT[111] & ~reg_be))) |
16037 (addr_hit[112] & (|(ALERT_HANDLER_PERMIT[112] & ~reg_be))) |
16038 (addr_hit[113] & (|(ALERT_HANDLER_PERMIT[113] & ~reg_be))) |
16039 (addr_hit[114] & (|(ALERT_HANDLER_PERMIT[114] & ~reg_be))) |
16040 (addr_hit[115] & (|(ALERT_HANDLER_PERMIT[115] & ~reg_be))) |
16041 (addr_hit[116] & (|(ALERT_HANDLER_PERMIT[116] & ~reg_be))) |
16042 (addr_hit[117] & (|(ALERT_HANDLER_PERMIT[117] & ~reg_be))) |
16043 (addr_hit[118] & (|(ALERT_HANDLER_PERMIT[118] & ~reg_be))) |
16044 (addr_hit[119] & (|(ALERT_HANDLER_PERMIT[119] & ~reg_be))) |
16045 (addr_hit[120] & (|(ALERT_HANDLER_PERMIT[120] & ~reg_be))) |
16046 (addr_hit[121] & (|(ALERT_HANDLER_PERMIT[121] & ~reg_be))) |
16047 (addr_hit[122] & (|(ALERT_HANDLER_PERMIT[122] & ~reg_be))) |
16048 (addr_hit[123] & (|(ALERT_HANDLER_PERMIT[123] & ~reg_be))) |
16049 (addr_hit[124] & (|(ALERT_HANDLER_PERMIT[124] & ~reg_be))) |
16050 (addr_hit[125] & (|(ALERT_HANDLER_PERMIT[125] & ~reg_be))) |
16051 (addr_hit[126] & (|(ALERT_HANDLER_PERMIT[126] & ~reg_be))) |
16052 (addr_hit[127] & (|(ALERT_HANDLER_PERMIT[127] & ~reg_be))) |
16053 (addr_hit[128] & (|(ALERT_HANDLER_PERMIT[128] & ~reg_be))) |
16054 (addr_hit[129] & (|(ALERT_HANDLER_PERMIT[129] & ~reg_be))) |
16055 (addr_hit[130] & (|(ALERT_HANDLER_PERMIT[130] & ~reg_be))) |
16056 (addr_hit[131] & (|(ALERT_HANDLER_PERMIT[131] & ~reg_be))) |
16057 (addr_hit[132] & (|(ALERT_HANDLER_PERMIT[132] & ~reg_be))) |
16058 (addr_hit[133] & (|(ALERT_HANDLER_PERMIT[133] & ~reg_be))) |
16059 (addr_hit[134] & (|(ALERT_HANDLER_PERMIT[134] & ~reg_be))) |
16060 (addr_hit[135] & (|(ALERT_HANDLER_PERMIT[135] & ~reg_be))) |
16061 (addr_hit[136] & (|(ALERT_HANDLER_PERMIT[136] & ~reg_be))) |
16062 (addr_hit[137] & (|(ALERT_HANDLER_PERMIT[137] & ~reg_be))) |
16063 (addr_hit[138] & (|(ALERT_HANDLER_PERMIT[138] & ~reg_be))) |
16064 (addr_hit[139] & (|(ALERT_HANDLER_PERMIT[139] & ~reg_be))) |
16065 (addr_hit[140] & (|(ALERT_HANDLER_PERMIT[140] & ~reg_be))) |
16066 (addr_hit[141] & (|(ALERT_HANDLER_PERMIT[141] & ~reg_be))) |
16067 (addr_hit[142] & (|(ALERT_HANDLER_PERMIT[142] & ~reg_be))) |
16068 (addr_hit[143] & (|(ALERT_HANDLER_PERMIT[143] & ~reg_be))) |
16069 (addr_hit[144] & (|(ALERT_HANDLER_PERMIT[144] & ~reg_be))) |
16070 (addr_hit[145] & (|(ALERT_HANDLER_PERMIT[145] & ~reg_be))) |
16071 (addr_hit[146] & (|(ALERT_HANDLER_PERMIT[146] & ~reg_be))) |
16072 (addr_hit[147] & (|(ALERT_HANDLER_PERMIT[147] & ~reg_be))) |
16073 (addr_hit[148] & (|(ALERT_HANDLER_PERMIT[148] & ~reg_be))) |
16074 (addr_hit[149] & (|(ALERT_HANDLER_PERMIT[149] & ~reg_be))) |
16075 (addr_hit[150] & (|(ALERT_HANDLER_PERMIT[150] & ~reg_be))) |
16076 (addr_hit[151] & (|(ALERT_HANDLER_PERMIT[151] & ~reg_be))) |
16077 (addr_hit[152] & (|(ALERT_HANDLER_PERMIT[152] & ~reg_be))) |
16078 (addr_hit[153] & (|(ALERT_HANDLER_PERMIT[153] & ~reg_be))) |
16079 (addr_hit[154] & (|(ALERT_HANDLER_PERMIT[154] & ~reg_be))) |
16080 (addr_hit[155] & (|(ALERT_HANDLER_PERMIT[155] & ~reg_be))) |
16081 (addr_hit[156] & (|(ALERT_HANDLER_PERMIT[156] & ~reg_be))) |
16082 (addr_hit[157] & (|(ALERT_HANDLER_PERMIT[157] & ~reg_be))) |
16083 (addr_hit[158] & (|(ALERT_HANDLER_PERMIT[158] & ~reg_be))) |
16084 (addr_hit[159] & (|(ALERT_HANDLER_PERMIT[159] & ~reg_be))) |
16085 (addr_hit[160] & (|(ALERT_HANDLER_PERMIT[160] & ~reg_be))) |
16086 (addr_hit[161] & (|(ALERT_HANDLER_PERMIT[161] & ~reg_be))) |
16087 (addr_hit[162] & (|(ALERT_HANDLER_PERMIT[162] & ~reg_be))) |
16088 (addr_hit[163] & (|(ALERT_HANDLER_PERMIT[163] & ~reg_be))) |
16089 (addr_hit[164] & (|(ALERT_HANDLER_PERMIT[164] & ~reg_be))) |
16090 (addr_hit[165] & (|(ALERT_HANDLER_PERMIT[165] & ~reg_be))) |
16091 (addr_hit[166] & (|(ALERT_HANDLER_PERMIT[166] & ~reg_be))) |
16092 (addr_hit[167] & (|(ALERT_HANDLER_PERMIT[167] & ~reg_be))) |
16093 (addr_hit[168] & (|(ALERT_HANDLER_PERMIT[168] & ~reg_be))) |
16094 (addr_hit[169] & (|(ALERT_HANDLER_PERMIT[169] & ~reg_be))) |
16095 (addr_hit[170] & (|(ALERT_HANDLER_PERMIT[170] & ~reg_be))) |
16096 (addr_hit[171] & (|(ALERT_HANDLER_PERMIT[171] & ~reg_be))) |
16097 (addr_hit[172] & (|(ALERT_HANDLER_PERMIT[172] & ~reg_be))) |
16098 (addr_hit[173] & (|(ALERT_HANDLER_PERMIT[173] & ~reg_be))) |
16099 (addr_hit[174] & (|(ALERT_HANDLER_PERMIT[174] & ~reg_be))) |
16100 (addr_hit[175] & (|(ALERT_HANDLER_PERMIT[175] & ~reg_be))) |
16101 (addr_hit[176] & (|(ALERT_HANDLER_PERMIT[176] & ~reg_be))) |
16102 (addr_hit[177] & (|(ALERT_HANDLER_PERMIT[177] & ~reg_be))) |
16103 (addr_hit[178] & (|(ALERT_HANDLER_PERMIT[178] & ~reg_be))) |
16104 (addr_hit[179] & (|(ALERT_HANDLER_PERMIT[179] & ~reg_be))) |
16105 (addr_hit[180] & (|(ALERT_HANDLER_PERMIT[180] & ~reg_be))) |
16106 (addr_hit[181] & (|(ALERT_HANDLER_PERMIT[181] & ~reg_be))) |
16107 (addr_hit[182] & (|(ALERT_HANDLER_PERMIT[182] & ~reg_be))) |
16108 (addr_hit[183] & (|(ALERT_HANDLER_PERMIT[183] & ~reg_be))) |
16109 (addr_hit[184] & (|(ALERT_HANDLER_PERMIT[184] & ~reg_be))) |
16110 (addr_hit[185] & (|(ALERT_HANDLER_PERMIT[185] & ~reg_be))) |
16111 (addr_hit[186] & (|(ALERT_HANDLER_PERMIT[186] & ~reg_be))) |
16112 (addr_hit[187] & (|(ALERT_HANDLER_PERMIT[187] & ~reg_be))) |
16113 (addr_hit[188] & (|(ALERT_HANDLER_PERMIT[188] & ~reg_be))) |
16114 (addr_hit[189] & (|(ALERT_HANDLER_PERMIT[189] & ~reg_be))) |
16115 (addr_hit[190] & (|(ALERT_HANDLER_PERMIT[190] & ~reg_be))) |
16116 (addr_hit[191] & (|(ALERT_HANDLER_PERMIT[191] & ~reg_be))) |
16117 (addr_hit[192] & (|(ALERT_HANDLER_PERMIT[192] & ~reg_be))) |
16118 (addr_hit[193] & (|(ALERT_HANDLER_PERMIT[193] & ~reg_be))) |
16119 (addr_hit[194] & (|(ALERT_HANDLER_PERMIT[194] & ~reg_be))) |
16120 (addr_hit[195] & (|(ALERT_HANDLER_PERMIT[195] & ~reg_be))) |
16121 (addr_hit[196] & (|(ALERT_HANDLER_PERMIT[196] & ~reg_be))) |
16122 (addr_hit[197] & (|(ALERT_HANDLER_PERMIT[197] & ~reg_be))) |
16123 (addr_hit[198] & (|(ALERT_HANDLER_PERMIT[198] & ~reg_be))) |
16124 (addr_hit[199] & (|(ALERT_HANDLER_PERMIT[199] & ~reg_be))) |
16125 (addr_hit[200] & (|(ALERT_HANDLER_PERMIT[200] & ~reg_be))) |
16126 (addr_hit[201] & (|(ALERT_HANDLER_PERMIT[201] & ~reg_be))) |
16127 (addr_hit[202] & (|(ALERT_HANDLER_PERMIT[202] & ~reg_be))) |
16128 (addr_hit[203] & (|(ALERT_HANDLER_PERMIT[203] & ~reg_be))) |
16129 (addr_hit[204] & (|(ALERT_HANDLER_PERMIT[204] & ~reg_be))) |
16130 (addr_hit[205] & (|(ALERT_HANDLER_PERMIT[205] & ~reg_be))) |
16131 (addr_hit[206] & (|(ALERT_HANDLER_PERMIT[206] & ~reg_be))) |
16132 (addr_hit[207] & (|(ALERT_HANDLER_PERMIT[207] & ~reg_be))) |
16133 (addr_hit[208] & (|(ALERT_HANDLER_PERMIT[208] & ~reg_be))) |
16134 (addr_hit[209] & (|(ALERT_HANDLER_PERMIT[209] & ~reg_be))) |
16135 (addr_hit[210] & (|(ALERT_HANDLER_PERMIT[210] & ~reg_be))) |
16136 (addr_hit[211] & (|(ALERT_HANDLER_PERMIT[211] & ~reg_be))) |
16137 (addr_hit[212] & (|(ALERT_HANDLER_PERMIT[212] & ~reg_be))) |
16138 (addr_hit[213] & (|(ALERT_HANDLER_PERMIT[213] & ~reg_be))) |
16139 (addr_hit[214] & (|(ALERT_HANDLER_PERMIT[214] & ~reg_be))) |
16140 (addr_hit[215] & (|(ALERT_HANDLER_PERMIT[215] & ~reg_be))) |
16141 (addr_hit[216] & (|(ALERT_HANDLER_PERMIT[216] & ~reg_be))) |
16142 (addr_hit[217] & (|(ALERT_HANDLER_PERMIT[217] & ~reg_be))) |
16143 (addr_hit[218] & (|(ALERT_HANDLER_PERMIT[218] & ~reg_be))) |
16144 (addr_hit[219] & (|(ALERT_HANDLER_PERMIT[219] & ~reg_be))) |
16145 (addr_hit[220] & (|(ALERT_HANDLER_PERMIT[220] & ~reg_be))) |
16146 (addr_hit[221] & (|(ALERT_HANDLER_PERMIT[221] & ~reg_be))) |
16147 (addr_hit[222] & (|(ALERT_HANDLER_PERMIT[222] & ~reg_be))) |
16148 (addr_hit[223] & (|(ALERT_HANDLER_PERMIT[223] & ~reg_be))) |
16149 (addr_hit[224] & (|(ALERT_HANDLER_PERMIT[224] & ~reg_be))) |
16150 (addr_hit[225] & (|(ALERT_HANDLER_PERMIT[225] & ~reg_be))) |
16151 (addr_hit[226] & (|(ALERT_HANDLER_PERMIT[226] & ~reg_be))) |
16152 (addr_hit[227] & (|(ALERT_HANDLER_PERMIT[227] & ~reg_be))) |
16153 (addr_hit[228] & (|(ALERT_HANDLER_PERMIT[228] & ~reg_be))) |
16154 (addr_hit[229] & (|(ALERT_HANDLER_PERMIT[229] & ~reg_be))) |
16155 (addr_hit[230] & (|(ALERT_HANDLER_PERMIT[230] & ~reg_be))) |
16156 (addr_hit[231] & (|(ALERT_HANDLER_PERMIT[231] & ~reg_be))) |
16157 (addr_hit[232] & (|(ALERT_HANDLER_PERMIT[232] & ~reg_be))) |
16158 (addr_hit[233] & (|(ALERT_HANDLER_PERMIT[233] & ~reg_be))) |
16159 (addr_hit[234] & (|(ALERT_HANDLER_PERMIT[234] & ~reg_be))) |
16160 (addr_hit[235] & (|(ALERT_HANDLER_PERMIT[235] & ~reg_be))) |
16161 (addr_hit[236] & (|(ALERT_HANDLER_PERMIT[236] & ~reg_be))) |
16162 (addr_hit[237] & (|(ALERT_HANDLER_PERMIT[237] & ~reg_be))) |
16163 (addr_hit[238] & (|(ALERT_HANDLER_PERMIT[238] & ~reg_be))) |
16164 (addr_hit[239] & (|(ALERT_HANDLER_PERMIT[239] & ~reg_be))) |
16165 (addr_hit[240] & (|(ALERT_HANDLER_PERMIT[240] & ~reg_be))) |
16166 (addr_hit[241] & (|(ALERT_HANDLER_PERMIT[241] & ~reg_be))) |
16167 (addr_hit[242] & (|(ALERT_HANDLER_PERMIT[242] & ~reg_be))) |
16168 (addr_hit[243] & (|(ALERT_HANDLER_PERMIT[243] & ~reg_be))) |
16169 (addr_hit[244] & (|(ALERT_HANDLER_PERMIT[244] & ~reg_be))) |
16170 (addr_hit[245] & (|(ALERT_HANDLER_PERMIT[245] & ~reg_be))) |
16171 (addr_hit[246] & (|(ALERT_HANDLER_PERMIT[246] & ~reg_be))) |
16172 (addr_hit[247] & (|(ALERT_HANDLER_PERMIT[247] & ~reg_be))) |
16173 (addr_hit[248] & (|(ALERT_HANDLER_PERMIT[248] & ~reg_be))) |
16174 (addr_hit[249] & (|(ALERT_HANDLER_PERMIT[249] & ~reg_be))) |
16175 (addr_hit[250] & (|(ALERT_HANDLER_PERMIT[250] & ~reg_be))) |
16176 (addr_hit[251] & (|(ALERT_HANDLER_PERMIT[251] & ~reg_be))) |
16177 (addr_hit[252] & (|(ALERT_HANDLER_PERMIT[252] & ~reg_be))) |
16178 (addr_hit[253] & (|(ALERT_HANDLER_PERMIT[253] & ~reg_be))) |
16179 (addr_hit[254] & (|(ALERT_HANDLER_PERMIT[254] & ~reg_be))) |
16180 (addr_hit[255] & (|(ALERT_HANDLER_PERMIT[255] & ~reg_be))) |
16181 (addr_hit[256] & (|(ALERT_HANDLER_PERMIT[256] & ~reg_be))) |
16182 (addr_hit[257] & (|(ALERT_HANDLER_PERMIT[257] & ~reg_be))) |
16183 (addr_hit[258] & (|(ALERT_HANDLER_PERMIT[258] & ~reg_be))) |
16184 (addr_hit[259] & (|(ALERT_HANDLER_PERMIT[259] & ~reg_be))) |
16185 (addr_hit[260] & (|(ALERT_HANDLER_PERMIT[260] & ~reg_be))) |
16186 (addr_hit[261] & (|(ALERT_HANDLER_PERMIT[261] & ~reg_be))) |
16187 (addr_hit[262] & (|(ALERT_HANDLER_PERMIT[262] & ~reg_be))) |
16188 (addr_hit[263] & (|(ALERT_HANDLER_PERMIT[263] & ~reg_be))) |
16189 (addr_hit[264] & (|(ALERT_HANDLER_PERMIT[264] & ~reg_be))) |
16190 (addr_hit[265] & (|(ALERT_HANDLER_PERMIT[265] & ~reg_be))) |
16191 (addr_hit[266] & (|(ALERT_HANDLER_PERMIT[266] & ~reg_be))) |
16192 (addr_hit[267] & (|(ALERT_HANDLER_PERMIT[267] & ~reg_be))) |
16193 (addr_hit[268] & (|(ALERT_HANDLER_PERMIT[268] & ~reg_be))) |
16194 (addr_hit[269] & (|(ALERT_HANDLER_PERMIT[269] & ~reg_be))) |
16195 (addr_hit[270] & (|(ALERT_HANDLER_PERMIT[270] & ~reg_be))) |
16196 (addr_hit[271] & (|(ALERT_HANDLER_PERMIT[271] & ~reg_be))) |
16197 (addr_hit[272] & (|(ALERT_HANDLER_PERMIT[272] & ~reg_be))) |
16198 (addr_hit[273] & (|(ALERT_HANDLER_PERMIT[273] & ~reg_be))) |
16199 (addr_hit[274] & (|(ALERT_HANDLER_PERMIT[274] & ~reg_be))) |
16200 (addr_hit[275] & (|(ALERT_HANDLER_PERMIT[275] & ~reg_be))) |
16201 (addr_hit[276] & (|(ALERT_HANDLER_PERMIT[276] & ~reg_be))) |
16202 (addr_hit[277] & (|(ALERT_HANDLER_PERMIT[277] & ~reg_be))) |
16203 (addr_hit[278] & (|(ALERT_HANDLER_PERMIT[278] & ~reg_be))) |
16204 (addr_hit[279] & (|(ALERT_HANDLER_PERMIT[279] & ~reg_be))) |
16205 (addr_hit[280] & (|(ALERT_HANDLER_PERMIT[280] & ~reg_be))) |
16206 (addr_hit[281] & (|(ALERT_HANDLER_PERMIT[281] & ~reg_be))) |
16207 (addr_hit[282] & (|(ALERT_HANDLER_PERMIT[282] & ~reg_be))) |
16208 (addr_hit[283] & (|(ALERT_HANDLER_PERMIT[283] & ~reg_be))) |
16209 (addr_hit[284] & (|(ALERT_HANDLER_PERMIT[284] & ~reg_be))) |
16210 (addr_hit[285] & (|(ALERT_HANDLER_PERMIT[285] & ~reg_be))) |
16211 (addr_hit[286] & (|(ALERT_HANDLER_PERMIT[286] & ~reg_be))) |
16212 (addr_hit[287] & (|(ALERT_HANDLER_PERMIT[287] & ~reg_be))) |
16213 (addr_hit[288] & (|(ALERT_HANDLER_PERMIT[288] & ~reg_be))) |
16214 (addr_hit[289] & (|(ALERT_HANDLER_PERMIT[289] & ~reg_be))) |
16215 (addr_hit[290] & (|(ALERT_HANDLER_PERMIT[290] & ~reg_be))) |
16216 (addr_hit[291] & (|(ALERT_HANDLER_PERMIT[291] & ~reg_be))) |
16217 (addr_hit[292] & (|(ALERT_HANDLER_PERMIT[292] & ~reg_be))) |
16218 (addr_hit[293] & (|(ALERT_HANDLER_PERMIT[293] & ~reg_be))) |
16219 (addr_hit[294] & (|(ALERT_HANDLER_PERMIT[294] & ~reg_be))) |
16220 (addr_hit[295] & (|(ALERT_HANDLER_PERMIT[295] & ~reg_be))) |
16221 (addr_hit[296] & (|(ALERT_HANDLER_PERMIT[296] & ~reg_be))) |
16222 (addr_hit[297] & (|(ALERT_HANDLER_PERMIT[297] & ~reg_be))) |
16223 (addr_hit[298] & (|(ALERT_HANDLER_PERMIT[298] & ~reg_be))) |
16224 (addr_hit[299] & (|(ALERT_HANDLER_PERMIT[299] & ~reg_be))) |
16225 (addr_hit[300] & (|(ALERT_HANDLER_PERMIT[300] & ~reg_be))) |
16226 (addr_hit[301] & (|(ALERT_HANDLER_PERMIT[301] & ~reg_be))) |
16227 (addr_hit[302] & (|(ALERT_HANDLER_PERMIT[302] & ~reg_be))) |
16228 (addr_hit[303] & (|(ALERT_HANDLER_PERMIT[303] & ~reg_be))) |
16229 (addr_hit[304] & (|(ALERT_HANDLER_PERMIT[304] & ~reg_be))) |
16230 (addr_hit[305] & (|(ALERT_HANDLER_PERMIT[305] & ~reg_be))) |
16231 (addr_hit[306] & (|(ALERT_HANDLER_PERMIT[306] & ~reg_be))) |
16232 (addr_hit[307] & (|(ALERT_HANDLER_PERMIT[307] & ~reg_be))) |
16233 (addr_hit[308] & (|(ALERT_HANDLER_PERMIT[308] & ~reg_be))) |
16234 (addr_hit[309] & (|(ALERT_HANDLER_PERMIT[309] & ~reg_be))) |
16235 (addr_hit[310] & (|(ALERT_HANDLER_PERMIT[310] & ~reg_be))) |
16236 (addr_hit[311] & (|(ALERT_HANDLER_PERMIT[311] & ~reg_be))) |
16237 (addr_hit[312] & (|(ALERT_HANDLER_PERMIT[312] & ~reg_be))) |
16238 (addr_hit[313] & (|(ALERT_HANDLER_PERMIT[313] & ~reg_be))) |
16239 (addr_hit[314] & (|(ALERT_HANDLER_PERMIT[314] & ~reg_be))) |
16240 (addr_hit[315] & (|(ALERT_HANDLER_PERMIT[315] & ~reg_be))) |
16241 (addr_hit[316] & (|(ALERT_HANDLER_PERMIT[316] & ~reg_be))) |
16242 (addr_hit[317] & (|(ALERT_HANDLER_PERMIT[317] & ~reg_be))) |
16243 (addr_hit[318] & (|(ALERT_HANDLER_PERMIT[318] & ~reg_be))) |
16244 (addr_hit[319] & (|(ALERT_HANDLER_PERMIT[319] & ~reg_be))) |
16245 (addr_hit[320] & (|(ALERT_HANDLER_PERMIT[320] & ~reg_be))) |
16246 (addr_hit[321] & (|(ALERT_HANDLER_PERMIT[321] & ~reg_be))) |
16247 (addr_hit[322] & (|(ALERT_HANDLER_PERMIT[322] & ~reg_be))) |
16248 (addr_hit[323] & (|(ALERT_HANDLER_PERMIT[323] & ~reg_be))) |
16249 (addr_hit[324] & (|(ALERT_HANDLER_PERMIT[324] & ~reg_be))) |
16250 (addr_hit[325] & (|(ALERT_HANDLER_PERMIT[325] & ~reg_be))) |
16251 (addr_hit[326] & (|(ALERT_HANDLER_PERMIT[326] & ~reg_be))) |
16252 (addr_hit[327] & (|(ALERT_HANDLER_PERMIT[327] & ~reg_be))) |
16253 (addr_hit[328] & (|(ALERT_HANDLER_PERMIT[328] & ~reg_be))) |
16254 (addr_hit[329] & (|(ALERT_HANDLER_PERMIT[329] & ~reg_be))) |
16255 (addr_hit[330] & (|(ALERT_HANDLER_PERMIT[330] & ~reg_be))) |
16256 (addr_hit[331] & (|(ALERT_HANDLER_PERMIT[331] & ~reg_be))) |
16257 (addr_hit[332] & (|(ALERT_HANDLER_PERMIT[332] & ~reg_be))) |
16258 (addr_hit[333] & (|(ALERT_HANDLER_PERMIT[333] & ~reg_be))) |
16259 (addr_hit[334] & (|(ALERT_HANDLER_PERMIT[334] & ~reg_be))) |
16260 (addr_hit[335] & (|(ALERT_HANDLER_PERMIT[335] & ~reg_be))) |
16261 (addr_hit[336] & (|(ALERT_HANDLER_PERMIT[336] & ~reg_be))) |
16262 (addr_hit[337] & (|(ALERT_HANDLER_PERMIT[337] & ~reg_be))) |
16263 (addr_hit[338] & (|(ALERT_HANDLER_PERMIT[338] & ~reg_be))) |
16264 (addr_hit[339] & (|(ALERT_HANDLER_PERMIT[339] & ~reg_be))) |
16265 (addr_hit[340] & (|(ALERT_HANDLER_PERMIT[340] & ~reg_be))) |
16266 (addr_hit[341] & (|(ALERT_HANDLER_PERMIT[341] & ~reg_be))) |
16267 (addr_hit[342] & (|(ALERT_HANDLER_PERMIT[342] & ~reg_be))) |
16268 (addr_hit[343] & (|(ALERT_HANDLER_PERMIT[343] & ~reg_be))) |
16269 (addr_hit[344] & (|(ALERT_HANDLER_PERMIT[344] & ~reg_be))) |
16270 (addr_hit[345] & (|(ALERT_HANDLER_PERMIT[345] & ~reg_be))) |
16271 (addr_hit[346] & (|(ALERT_HANDLER_PERMIT[346] & ~reg_be))) |
16272 (addr_hit[347] & (|(ALERT_HANDLER_PERMIT[347] & ~reg_be))) |
16273 (addr_hit[348] & (|(ALERT_HANDLER_PERMIT[348] & ~reg_be))) |
16274 (addr_hit[349] & (|(ALERT_HANDLER_PERMIT[349] & ~reg_be)))));
16275 end
16276
16277 // Generate write-enables
16278 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
16279
16280 1/1 assign intr_state_classa_wd = reg_wdata[0];
Tests: T1 T2 T3
16281
16282 1/1 assign intr_state_classb_wd = reg_wdata[1];
Tests: T1 T2 T3
16283
16284 1/1 assign intr_state_classc_wd = reg_wdata[2];
Tests: T1 T2 T3
16285
16286 1/1 assign intr_state_classd_wd = reg_wdata[3];
Tests: T1 T2 T3
16287 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
16288
16289 1/1 assign intr_enable_classa_wd = reg_wdata[0];
Tests: T1 T2 T3
16290
16291 1/1 assign intr_enable_classb_wd = reg_wdata[1];
Tests: T1 T2 T3
16292
16293 1/1 assign intr_enable_classc_wd = reg_wdata[2];
Tests: T1 T2 T3
16294
16295 1/1 assign intr_enable_classd_wd = reg_wdata[3];
Tests: T1 T2 T3
16296 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
16297
16298 1/1 assign intr_test_classa_wd = reg_wdata[0];
Tests: T1 T2 T3
16299
16300 1/1 assign intr_test_classb_wd = reg_wdata[1];
Tests: T1 T2 T3
16301
16302 1/1 assign intr_test_classc_wd = reg_wdata[2];
Tests: T1 T2 T3
16303
16304 1/1 assign intr_test_classd_wd = reg_wdata[3];
Tests: T1 T2 T3
16305 1/1 assign ping_timer_regwen_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
16306
16307 1/1 assign ping_timer_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
16308 1/1 assign ping_timeout_cyc_shadowed_re = addr_hit[4] & reg_re & !reg_error;
Tests: T1 T2 T3
16309 1/1 assign ping_timeout_cyc_shadowed_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
16310
16311 1/1 assign ping_timeout_cyc_shadowed_wd = reg_wdata[15:0];
Tests: T1 T2 T3
16312 1/1 assign ping_timer_en_shadowed_re = addr_hit[5] & reg_re & !reg_error;
Tests: T1 T2 T3
16313 1/1 assign ping_timer_en_shadowed_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
16314
16315 1/1 assign ping_timer_en_shadowed_wd = reg_wdata[0];
Tests: T1 T2 T3
16316 1/1 assign alert_regwen_0_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
16317
16318 1/1 assign alert_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
16319 1/1 assign alert_regwen_1_we = addr_hit[7] & reg_we & !reg_error;
Tests: T1 T2 T3
16320
16321 1/1 assign alert_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
16322 1/1 assign alert_regwen_2_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
16323
16324 1/1 assign alert_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
16325 1/1 assign alert_regwen_3_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
16326
16327 1/1 assign alert_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
16328 1/1 assign alert_regwen_4_we = addr_hit[10] & reg_we & !reg_error;
Tests: T1 T2 T3
16329
16330 1/1 assign alert_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
16331 1/1 assign alert_regwen_5_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
16332
16333 1/1 assign alert_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
16334 1/1 assign alert_regwen_6_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
16335
16336 1/1 assign alert_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
16337 1/1 assign alert_regwen_7_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
16338
16339 1/1 assign alert_regwen_7_wd = reg_wdata[0];
Tests: T1 T2 T3
16340 1/1 assign alert_regwen_8_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
16341
16342 1/1 assign alert_regwen_8_wd = reg_wdata[0];
Tests: T1 T2 T3
16343 1/1 assign alert_regwen_9_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
16344
16345 1/1 assign alert_regwen_9_wd = reg_wdata[0];
Tests: T1 T2 T3
16346 1/1 assign alert_regwen_10_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
16347
16348 1/1 assign alert_regwen_10_wd = reg_wdata[0];
Tests: T1 T2 T3
16349 1/1 assign alert_regwen_11_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
16350
16351 1/1 assign alert_regwen_11_wd = reg_wdata[0];
Tests: T1 T2 T3
16352 1/1 assign alert_regwen_12_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
16353
16354 1/1 assign alert_regwen_12_wd = reg_wdata[0];
Tests: T1 T2 T3
16355 1/1 assign alert_regwen_13_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
16356
16357 1/1 assign alert_regwen_13_wd = reg_wdata[0];
Tests: T1 T2 T3
16358 1/1 assign alert_regwen_14_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
16359
16360 1/1 assign alert_regwen_14_wd = reg_wdata[0];
Tests: T1 T2 T3
16361 1/1 assign alert_regwen_15_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
16362
16363 1/1 assign alert_regwen_15_wd = reg_wdata[0];
Tests: T1 T2 T3
16364 1/1 assign alert_regwen_16_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
16365
16366 1/1 assign alert_regwen_16_wd = reg_wdata[0];
Tests: T1 T2 T3
16367 1/1 assign alert_regwen_17_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
16368
16369 1/1 assign alert_regwen_17_wd = reg_wdata[0];
Tests: T1 T2 T3
16370 1/1 assign alert_regwen_18_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
16371
16372 1/1 assign alert_regwen_18_wd = reg_wdata[0];
Tests: T1 T2 T3
16373 1/1 assign alert_regwen_19_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
16374
16375 1/1 assign alert_regwen_19_wd = reg_wdata[0];
Tests: T1 T2 T3
16376 1/1 assign alert_regwen_20_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
16377
16378 1/1 assign alert_regwen_20_wd = reg_wdata[0];
Tests: T1 T2 T3
16379 1/1 assign alert_regwen_21_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
16380
16381 1/1 assign alert_regwen_21_wd = reg_wdata[0];
Tests: T1 T2 T3
16382 1/1 assign alert_regwen_22_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
16383
16384 1/1 assign alert_regwen_22_wd = reg_wdata[0];
Tests: T1 T2 T3
16385 1/1 assign alert_regwen_23_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
16386
16387 1/1 assign alert_regwen_23_wd = reg_wdata[0];
Tests: T1 T2 T3
16388 1/1 assign alert_regwen_24_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
16389
16390 1/1 assign alert_regwen_24_wd = reg_wdata[0];
Tests: T1 T2 T3
16391 1/1 assign alert_regwen_25_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
16392
16393 1/1 assign alert_regwen_25_wd = reg_wdata[0];
Tests: T1 T2 T3
16394 1/1 assign alert_regwen_26_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
16395
16396 1/1 assign alert_regwen_26_wd = reg_wdata[0];
Tests: T1 T2 T3
16397 1/1 assign alert_regwen_27_we = addr_hit[33] & reg_we & !reg_error;
Tests: T1 T2 T3
16398
16399 1/1 assign alert_regwen_27_wd = reg_wdata[0];
Tests: T1 T2 T3
16400 1/1 assign alert_regwen_28_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
16401
16402 1/1 assign alert_regwen_28_wd = reg_wdata[0];
Tests: T1 T2 T3
16403 1/1 assign alert_regwen_29_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
16404
16405 1/1 assign alert_regwen_29_wd = reg_wdata[0];
Tests: T1 T2 T3
16406 1/1 assign alert_regwen_30_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T3
16407
16408 1/1 assign alert_regwen_30_wd = reg_wdata[0];
Tests: T1 T2 T3
16409 1/1 assign alert_regwen_31_we = addr_hit[37] & reg_we & !reg_error;
Tests: T1 T2 T3
16410
16411 1/1 assign alert_regwen_31_wd = reg_wdata[0];
Tests: T1 T2 T3
16412 1/1 assign alert_regwen_32_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T3
16413
16414 1/1 assign alert_regwen_32_wd = reg_wdata[0];
Tests: T1 T2 T3
16415 1/1 assign alert_regwen_33_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
16416
16417 1/1 assign alert_regwen_33_wd = reg_wdata[0];
Tests: T1 T2 T3
16418 1/1 assign alert_regwen_34_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T3
16419
16420 1/1 assign alert_regwen_34_wd = reg_wdata[0];
Tests: T1 T2 T3
16421 1/1 assign alert_regwen_35_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T3
16422
16423 1/1 assign alert_regwen_35_wd = reg_wdata[0];
Tests: T1 T2 T3
16424 1/1 assign alert_regwen_36_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T2 T3
16425
16426 1/1 assign alert_regwen_36_wd = reg_wdata[0];
Tests: T1 T2 T3
16427 1/1 assign alert_regwen_37_we = addr_hit[43] & reg_we & !reg_error;
Tests: T1 T2 T3
16428
16429 1/1 assign alert_regwen_37_wd = reg_wdata[0];
Tests: T1 T2 T3
16430 1/1 assign alert_regwen_38_we = addr_hit[44] & reg_we & !reg_error;
Tests: T1 T2 T3
16431
16432 1/1 assign alert_regwen_38_wd = reg_wdata[0];
Tests: T1 T2 T3
16433 1/1 assign alert_regwen_39_we = addr_hit[45] & reg_we & !reg_error;
Tests: T1 T2 T3
16434
16435 1/1 assign alert_regwen_39_wd = reg_wdata[0];
Tests: T1 T2 T3
16436 1/1 assign alert_regwen_40_we = addr_hit[46] & reg_we & !reg_error;
Tests: T1 T2 T3
16437
16438 1/1 assign alert_regwen_40_wd = reg_wdata[0];
Tests: T1 T2 T3
16439 1/1 assign alert_regwen_41_we = addr_hit[47] & reg_we & !reg_error;
Tests: T1 T2 T3
16440
16441 1/1 assign alert_regwen_41_wd = reg_wdata[0];
Tests: T1 T2 T3
16442 1/1 assign alert_regwen_42_we = addr_hit[48] & reg_we & !reg_error;
Tests: T1 T2 T3
16443
16444 1/1 assign alert_regwen_42_wd = reg_wdata[0];
Tests: T1 T2 T3
16445 1/1 assign alert_regwen_43_we = addr_hit[49] & reg_we & !reg_error;
Tests: T1 T2 T3
16446
16447 1/1 assign alert_regwen_43_wd = reg_wdata[0];
Tests: T1 T2 T3
16448 1/1 assign alert_regwen_44_we = addr_hit[50] & reg_we & !reg_error;
Tests: T1 T2 T3
16449
16450 1/1 assign alert_regwen_44_wd = reg_wdata[0];
Tests: T1 T2 T3
16451 1/1 assign alert_regwen_45_we = addr_hit[51] & reg_we & !reg_error;
Tests: T1 T2 T3
16452
16453 1/1 assign alert_regwen_45_wd = reg_wdata[0];
Tests: T1 T2 T3
16454 1/1 assign alert_regwen_46_we = addr_hit[52] & reg_we & !reg_error;
Tests: T1 T2 T3
16455
16456 1/1 assign alert_regwen_46_wd = reg_wdata[0];
Tests: T1 T2 T3
16457 1/1 assign alert_regwen_47_we = addr_hit[53] & reg_we & !reg_error;
Tests: T1 T2 T3
16458
16459 1/1 assign alert_regwen_47_wd = reg_wdata[0];
Tests: T1 T2 T3
16460 1/1 assign alert_regwen_48_we = addr_hit[54] & reg_we & !reg_error;
Tests: T1 T2 T3
16461
16462 1/1 assign alert_regwen_48_wd = reg_wdata[0];
Tests: T1 T2 T3
16463 1/1 assign alert_regwen_49_we = addr_hit[55] & reg_we & !reg_error;
Tests: T1 T2 T3
16464
16465 1/1 assign alert_regwen_49_wd = reg_wdata[0];
Tests: T1 T2 T3
16466 1/1 assign alert_regwen_50_we = addr_hit[56] & reg_we & !reg_error;
Tests: T1 T2 T3
16467
16468 1/1 assign alert_regwen_50_wd = reg_wdata[0];
Tests: T1 T2 T3
16469 1/1 assign alert_regwen_51_we = addr_hit[57] & reg_we & !reg_error;
Tests: T1 T2 T3
16470
16471 1/1 assign alert_regwen_51_wd = reg_wdata[0];
Tests: T1 T2 T3
16472 1/1 assign alert_regwen_52_we = addr_hit[58] & reg_we & !reg_error;
Tests: T1 T2 T3
16473
16474 1/1 assign alert_regwen_52_wd = reg_wdata[0];
Tests: T1 T2 T3
16475 1/1 assign alert_regwen_53_we = addr_hit[59] & reg_we & !reg_error;
Tests: T1 T2 T3
16476
16477 1/1 assign alert_regwen_53_wd = reg_wdata[0];
Tests: T1 T2 T3
16478 1/1 assign alert_regwen_54_we = addr_hit[60] & reg_we & !reg_error;
Tests: T1 T2 T3
16479
16480 1/1 assign alert_regwen_54_wd = reg_wdata[0];
Tests: T1 T2 T3
16481 1/1 assign alert_regwen_55_we = addr_hit[61] & reg_we & !reg_error;
Tests: T1 T2 T3
16482
16483 1/1 assign alert_regwen_55_wd = reg_wdata[0];
Tests: T1 T2 T3
16484 1/1 assign alert_regwen_56_we = addr_hit[62] & reg_we & !reg_error;
Tests: T1 T2 T3
16485
16486 1/1 assign alert_regwen_56_wd = reg_wdata[0];
Tests: T1 T2 T3
16487 1/1 assign alert_regwen_57_we = addr_hit[63] & reg_we & !reg_error;
Tests: T1 T2 T3
16488
16489 1/1 assign alert_regwen_57_wd = reg_wdata[0];
Tests: T1 T2 T3
16490 1/1 assign alert_regwen_58_we = addr_hit[64] & reg_we & !reg_error;
Tests: T1 T2 T3
16491
16492 1/1 assign alert_regwen_58_wd = reg_wdata[0];
Tests: T1 T2 T3
16493 1/1 assign alert_regwen_59_we = addr_hit[65] & reg_we & !reg_error;
Tests: T1 T2 T3
16494
16495 1/1 assign alert_regwen_59_wd = reg_wdata[0];
Tests: T1 T2 T3
16496 1/1 assign alert_regwen_60_we = addr_hit[66] & reg_we & !reg_error;
Tests: T1 T2 T3
16497
16498 1/1 assign alert_regwen_60_wd = reg_wdata[0];
Tests: T1 T2 T3
16499 1/1 assign alert_regwen_61_we = addr_hit[67] & reg_we & !reg_error;
Tests: T1 T2 T3
16500
16501 1/1 assign alert_regwen_61_wd = reg_wdata[0];
Tests: T1 T2 T3
16502 1/1 assign alert_regwen_62_we = addr_hit[68] & reg_we & !reg_error;
Tests: T1 T2 T3
16503
16504 1/1 assign alert_regwen_62_wd = reg_wdata[0];
Tests: T1 T2 T3
16505 1/1 assign alert_regwen_63_we = addr_hit[69] & reg_we & !reg_error;
Tests: T1 T2 T3
16506
16507 1/1 assign alert_regwen_63_wd = reg_wdata[0];
Tests: T1 T2 T3
16508 1/1 assign alert_regwen_64_we = addr_hit[70] & reg_we & !reg_error;
Tests: T1 T2 T3
16509
16510 1/1 assign alert_regwen_64_wd = reg_wdata[0];
Tests: T1 T2 T3
16511 1/1 assign alert_en_shadowed_0_re = addr_hit[71] & reg_re & !reg_error;
Tests: T1 T2 T3
16512 1/1 assign alert_en_shadowed_0_we = addr_hit[71] & reg_we & !reg_error;
Tests: T1 T2 T3
16513
16514 1/1 assign alert_en_shadowed_0_wd = reg_wdata[0];
Tests: T1 T2 T3
16515 1/1 assign alert_en_shadowed_1_re = addr_hit[72] & reg_re & !reg_error;
Tests: T1 T2 T3
16516 1/1 assign alert_en_shadowed_1_we = addr_hit[72] & reg_we & !reg_error;
Tests: T1 T2 T3
16517
16518 1/1 assign alert_en_shadowed_1_wd = reg_wdata[0];
Tests: T1 T2 T3
16519 1/1 assign alert_en_shadowed_2_re = addr_hit[73] & reg_re & !reg_error;
Tests: T1 T2 T3
16520 1/1 assign alert_en_shadowed_2_we = addr_hit[73] & reg_we & !reg_error;
Tests: T1 T2 T3
16521
16522 1/1 assign alert_en_shadowed_2_wd = reg_wdata[0];
Tests: T1 T2 T3
16523 1/1 assign alert_en_shadowed_3_re = addr_hit[74] & reg_re & !reg_error;
Tests: T1 T2 T3
16524 1/1 assign alert_en_shadowed_3_we = addr_hit[74] & reg_we & !reg_error;
Tests: T1 T2 T3
16525
16526 1/1 assign alert_en_shadowed_3_wd = reg_wdata[0];
Tests: T1 T2 T3
16527 1/1 assign alert_en_shadowed_4_re = addr_hit[75] & reg_re & !reg_error;
Tests: T1 T2 T3
16528 1/1 assign alert_en_shadowed_4_we = addr_hit[75] & reg_we & !reg_error;
Tests: T1 T2 T3
16529
16530 1/1 assign alert_en_shadowed_4_wd = reg_wdata[0];
Tests: T1 T2 T3
16531 1/1 assign alert_en_shadowed_5_re = addr_hit[76] & reg_re & !reg_error;
Tests: T1 T2 T3
16532 1/1 assign alert_en_shadowed_5_we = addr_hit[76] & reg_we & !reg_error;
Tests: T1 T2 T3
16533
16534 1/1 assign alert_en_shadowed_5_wd = reg_wdata[0];
Tests: T1 T2 T3
16535 1/1 assign alert_en_shadowed_6_re = addr_hit[77] & reg_re & !reg_error;
Tests: T1 T2 T3
16536 1/1 assign alert_en_shadowed_6_we = addr_hit[77] & reg_we & !reg_error;
Tests: T1 T2 T3
16537
16538 1/1 assign alert_en_shadowed_6_wd = reg_wdata[0];
Tests: T1 T2 T3
16539 1/1 assign alert_en_shadowed_7_re = addr_hit[78] & reg_re & !reg_error;
Tests: T1 T2 T3
16540 1/1 assign alert_en_shadowed_7_we = addr_hit[78] & reg_we & !reg_error;
Tests: T1 T2 T3
16541
16542 1/1 assign alert_en_shadowed_7_wd = reg_wdata[0];
Tests: T1 T2 T3
16543 1/1 assign alert_en_shadowed_8_re = addr_hit[79] & reg_re & !reg_error;
Tests: T1 T2 T3
16544 1/1 assign alert_en_shadowed_8_we = addr_hit[79] & reg_we & !reg_error;
Tests: T1 T2 T3
16545
16546 1/1 assign alert_en_shadowed_8_wd = reg_wdata[0];
Tests: T1 T2 T3
16547 1/1 assign alert_en_shadowed_9_re = addr_hit[80] & reg_re & !reg_error;
Tests: T1 T2 T3
16548 1/1 assign alert_en_shadowed_9_we = addr_hit[80] & reg_we & !reg_error;
Tests: T1 T2 T3
16549
16550 1/1 assign alert_en_shadowed_9_wd = reg_wdata[0];
Tests: T1 T2 T3
16551 1/1 assign alert_en_shadowed_10_re = addr_hit[81] & reg_re & !reg_error;
Tests: T1 T2 T3
16552 1/1 assign alert_en_shadowed_10_we = addr_hit[81] & reg_we & !reg_error;
Tests: T1 T2 T3
16553
16554 1/1 assign alert_en_shadowed_10_wd = reg_wdata[0];
Tests: T1 T2 T3
16555 1/1 assign alert_en_shadowed_11_re = addr_hit[82] & reg_re & !reg_error;
Tests: T1 T2 T3
16556 1/1 assign alert_en_shadowed_11_we = addr_hit[82] & reg_we & !reg_error;
Tests: T1 T2 T3
16557
16558 1/1 assign alert_en_shadowed_11_wd = reg_wdata[0];
Tests: T1 T2 T3
16559 1/1 assign alert_en_shadowed_12_re = addr_hit[83] & reg_re & !reg_error;
Tests: T1 T2 T3
16560 1/1 assign alert_en_shadowed_12_we = addr_hit[83] & reg_we & !reg_error;
Tests: T1 T2 T3
16561
16562 1/1 assign alert_en_shadowed_12_wd = reg_wdata[0];
Tests: T1 T2 T3
16563 1/1 assign alert_en_shadowed_13_re = addr_hit[84] & reg_re & !reg_error;
Tests: T1 T2 T3
16564 1/1 assign alert_en_shadowed_13_we = addr_hit[84] & reg_we & !reg_error;
Tests: T1 T2 T3
16565
16566 1/1 assign alert_en_shadowed_13_wd = reg_wdata[0];
Tests: T1 T2 T3
16567 1/1 assign alert_en_shadowed_14_re = addr_hit[85] & reg_re & !reg_error;
Tests: T1 T2 T3
16568 1/1 assign alert_en_shadowed_14_we = addr_hit[85] & reg_we & !reg_error;
Tests: T1 T2 T3
16569
16570 1/1 assign alert_en_shadowed_14_wd = reg_wdata[0];
Tests: T1 T2 T3
16571 1/1 assign alert_en_shadowed_15_re = addr_hit[86] & reg_re & !reg_error;
Tests: T1 T2 T3
16572 1/1 assign alert_en_shadowed_15_we = addr_hit[86] & reg_we & !reg_error;
Tests: T1 T2 T3
16573
16574 1/1 assign alert_en_shadowed_15_wd = reg_wdata[0];
Tests: T1 T2 T3
16575 1/1 assign alert_en_shadowed_16_re = addr_hit[87] & reg_re & !reg_error;
Tests: T1 T2 T3
16576 1/1 assign alert_en_shadowed_16_we = addr_hit[87] & reg_we & !reg_error;
Tests: T1 T2 T3
16577
16578 1/1 assign alert_en_shadowed_16_wd = reg_wdata[0];
Tests: T1 T2 T3
16579 1/1 assign alert_en_shadowed_17_re = addr_hit[88] & reg_re & !reg_error;
Tests: T1 T2 T3
16580 1/1 assign alert_en_shadowed_17_we = addr_hit[88] & reg_we & !reg_error;
Tests: T1 T2 T3
16581
16582 1/1 assign alert_en_shadowed_17_wd = reg_wdata[0];
Tests: T1 T2 T3
16583 1/1 assign alert_en_shadowed_18_re = addr_hit[89] & reg_re & !reg_error;
Tests: T1 T2 T3
16584 1/1 assign alert_en_shadowed_18_we = addr_hit[89] & reg_we & !reg_error;
Tests: T1 T2 T3
16585
16586 1/1 assign alert_en_shadowed_18_wd = reg_wdata[0];
Tests: T1 T2 T3
16587 1/1 assign alert_en_shadowed_19_re = addr_hit[90] & reg_re & !reg_error;
Tests: T1 T2 T3
16588 1/1 assign alert_en_shadowed_19_we = addr_hit[90] & reg_we & !reg_error;
Tests: T1 T2 T3
16589
16590 1/1 assign alert_en_shadowed_19_wd = reg_wdata[0];
Tests: T1 T2 T3
16591 1/1 assign alert_en_shadowed_20_re = addr_hit[91] & reg_re & !reg_error;
Tests: T1 T2 T3
16592 1/1 assign alert_en_shadowed_20_we = addr_hit[91] & reg_we & !reg_error;
Tests: T1 T2 T3
16593
16594 1/1 assign alert_en_shadowed_20_wd = reg_wdata[0];
Tests: T1 T2 T3
16595 1/1 assign alert_en_shadowed_21_re = addr_hit[92] & reg_re & !reg_error;
Tests: T1 T2 T3
16596 1/1 assign alert_en_shadowed_21_we = addr_hit[92] & reg_we & !reg_error;
Tests: T1 T2 T3
16597
16598 1/1 assign alert_en_shadowed_21_wd = reg_wdata[0];
Tests: T1 T2 T3
16599 1/1 assign alert_en_shadowed_22_re = addr_hit[93] & reg_re & !reg_error;
Tests: T1 T2 T3
16600 1/1 assign alert_en_shadowed_22_we = addr_hit[93] & reg_we & !reg_error;
Tests: T1 T2 T3
16601
16602 1/1 assign alert_en_shadowed_22_wd = reg_wdata[0];
Tests: T1 T2 T3
16603 1/1 assign alert_en_shadowed_23_re = addr_hit[94] & reg_re & !reg_error;
Tests: T1 T2 T3
16604 1/1 assign alert_en_shadowed_23_we = addr_hit[94] & reg_we & !reg_error;
Tests: T1 T2 T3
16605
16606 1/1 assign alert_en_shadowed_23_wd = reg_wdata[0];
Tests: T1 T2 T3
16607 1/1 assign alert_en_shadowed_24_re = addr_hit[95] & reg_re & !reg_error;
Tests: T1 T2 T3
16608 1/1 assign alert_en_shadowed_24_we = addr_hit[95] & reg_we & !reg_error;
Tests: T1 T2 T3
16609
16610 1/1 assign alert_en_shadowed_24_wd = reg_wdata[0];
Tests: T1 T2 T3
16611 1/1 assign alert_en_shadowed_25_re = addr_hit[96] & reg_re & !reg_error;
Tests: T1 T2 T3
16612 1/1 assign alert_en_shadowed_25_we = addr_hit[96] & reg_we & !reg_error;
Tests: T1 T2 T3
16613
16614 1/1 assign alert_en_shadowed_25_wd = reg_wdata[0];
Tests: T1 T2 T3
16615 1/1 assign alert_en_shadowed_26_re = addr_hit[97] & reg_re & !reg_error;
Tests: T1 T2 T3
16616 1/1 assign alert_en_shadowed_26_we = addr_hit[97] & reg_we & !reg_error;
Tests: T1 T2 T3
16617
16618 1/1 assign alert_en_shadowed_26_wd = reg_wdata[0];
Tests: T1 T2 T3
16619 1/1 assign alert_en_shadowed_27_re = addr_hit[98] & reg_re & !reg_error;
Tests: T1 T2 T3
16620 1/1 assign alert_en_shadowed_27_we = addr_hit[98] & reg_we & !reg_error;
Tests: T1 T2 T3
16621
16622 1/1 assign alert_en_shadowed_27_wd = reg_wdata[0];
Tests: T1 T2 T3
16623 1/1 assign alert_en_shadowed_28_re = addr_hit[99] & reg_re & !reg_error;
Tests: T1 T2 T3
16624 1/1 assign alert_en_shadowed_28_we = addr_hit[99] & reg_we & !reg_error;
Tests: T1 T2 T3
16625
16626 1/1 assign alert_en_shadowed_28_wd = reg_wdata[0];
Tests: T1 T2 T3
16627 1/1 assign alert_en_shadowed_29_re = addr_hit[100] & reg_re & !reg_error;
Tests: T1 T2 T3
16628 1/1 assign alert_en_shadowed_29_we = addr_hit[100] & reg_we & !reg_error;
Tests: T1 T2 T3
16629
16630 1/1 assign alert_en_shadowed_29_wd = reg_wdata[0];
Tests: T1 T2 T3
16631 1/1 assign alert_en_shadowed_30_re = addr_hit[101] & reg_re & !reg_error;
Tests: T1 T2 T3
16632 1/1 assign alert_en_shadowed_30_we = addr_hit[101] & reg_we & !reg_error;
Tests: T1 T2 T3
16633
16634 1/1 assign alert_en_shadowed_30_wd = reg_wdata[0];
Tests: T1 T2 T3
16635 1/1 assign alert_en_shadowed_31_re = addr_hit[102] & reg_re & !reg_error;
Tests: T1 T2 T3
16636 1/1 assign alert_en_shadowed_31_we = addr_hit[102] & reg_we & !reg_error;
Tests: T1 T2 T3
16637
16638 1/1 assign alert_en_shadowed_31_wd = reg_wdata[0];
Tests: T1 T2 T3
16639 1/1 assign alert_en_shadowed_32_re = addr_hit[103] & reg_re & !reg_error;
Tests: T1 T2 T3
16640 1/1 assign alert_en_shadowed_32_we = addr_hit[103] & reg_we & !reg_error;
Tests: T1 T2 T3
16641
16642 1/1 assign alert_en_shadowed_32_wd = reg_wdata[0];
Tests: T1 T2 T3
16643 1/1 assign alert_en_shadowed_33_re = addr_hit[104] & reg_re & !reg_error;
Tests: T1 T2 T3
16644 1/1 assign alert_en_shadowed_33_we = addr_hit[104] & reg_we & !reg_error;
Tests: T1 T2 T3
16645
16646 1/1 assign alert_en_shadowed_33_wd = reg_wdata[0];
Tests: T1 T2 T3
16647 1/1 assign alert_en_shadowed_34_re = addr_hit[105] & reg_re & !reg_error;
Tests: T1 T2 T3
16648 1/1 assign alert_en_shadowed_34_we = addr_hit[105] & reg_we & !reg_error;
Tests: T1 T2 T3
16649
16650 1/1 assign alert_en_shadowed_34_wd = reg_wdata[0];
Tests: T1 T2 T3
16651 1/1 assign alert_en_shadowed_35_re = addr_hit[106] & reg_re & !reg_error;
Tests: T1 T2 T3
16652 1/1 assign alert_en_shadowed_35_we = addr_hit[106] & reg_we & !reg_error;
Tests: T1 T2 T3
16653
16654 1/1 assign alert_en_shadowed_35_wd = reg_wdata[0];
Tests: T1 T2 T3
16655 1/1 assign alert_en_shadowed_36_re = addr_hit[107] & reg_re & !reg_error;
Tests: T1 T2 T3
16656 1/1 assign alert_en_shadowed_36_we = addr_hit[107] & reg_we & !reg_error;
Tests: T1 T2 T3
16657
16658 1/1 assign alert_en_shadowed_36_wd = reg_wdata[0];
Tests: T1 T2 T3
16659 1/1 assign alert_en_shadowed_37_re = addr_hit[108] & reg_re & !reg_error;
Tests: T1 T2 T3
16660 1/1 assign alert_en_shadowed_37_we = addr_hit[108] & reg_we & !reg_error;
Tests: T1 T2 T3
16661
16662 1/1 assign alert_en_shadowed_37_wd = reg_wdata[0];
Tests: T1 T2 T3
16663 1/1 assign alert_en_shadowed_38_re = addr_hit[109] & reg_re & !reg_error;
Tests: T1 T2 T3
16664 1/1 assign alert_en_shadowed_38_we = addr_hit[109] & reg_we & !reg_error;
Tests: T1 T2 T3
16665
16666 1/1 assign alert_en_shadowed_38_wd = reg_wdata[0];
Tests: T1 T2 T3
16667 1/1 assign alert_en_shadowed_39_re = addr_hit[110] & reg_re & !reg_error;
Tests: T1 T2 T3
16668 1/1 assign alert_en_shadowed_39_we = addr_hit[110] & reg_we & !reg_error;
Tests: T1 T2 T3
16669
16670 1/1 assign alert_en_shadowed_39_wd = reg_wdata[0];
Tests: T1 T2 T3
16671 1/1 assign alert_en_shadowed_40_re = addr_hit[111] & reg_re & !reg_error;
Tests: T1 T2 T3
16672 1/1 assign alert_en_shadowed_40_we = addr_hit[111] & reg_we & !reg_error;
Tests: T1 T2 T3
16673
16674 1/1 assign alert_en_shadowed_40_wd = reg_wdata[0];
Tests: T1 T2 T3
16675 1/1 assign alert_en_shadowed_41_re = addr_hit[112] & reg_re & !reg_error;
Tests: T1 T2 T3
16676 1/1 assign alert_en_shadowed_41_we = addr_hit[112] & reg_we & !reg_error;
Tests: T1 T2 T3
16677
16678 1/1 assign alert_en_shadowed_41_wd = reg_wdata[0];
Tests: T1 T2 T3
16679 1/1 assign alert_en_shadowed_42_re = addr_hit[113] & reg_re & !reg_error;
Tests: T1 T2 T3
16680 1/1 assign alert_en_shadowed_42_we = addr_hit[113] & reg_we & !reg_error;
Tests: T1 T2 T3
16681
16682 1/1 assign alert_en_shadowed_42_wd = reg_wdata[0];
Tests: T1 T2 T3
16683 1/1 assign alert_en_shadowed_43_re = addr_hit[114] & reg_re & !reg_error;
Tests: T1 T2 T3
16684 1/1 assign alert_en_shadowed_43_we = addr_hit[114] & reg_we & !reg_error;
Tests: T1 T2 T3
16685
16686 1/1 assign alert_en_shadowed_43_wd = reg_wdata[0];
Tests: T1 T2 T3
16687 1/1 assign alert_en_shadowed_44_re = addr_hit[115] & reg_re & !reg_error;
Tests: T1 T2 T3
16688 1/1 assign alert_en_shadowed_44_we = addr_hit[115] & reg_we & !reg_error;
Tests: T1 T2 T3
16689
16690 1/1 assign alert_en_shadowed_44_wd = reg_wdata[0];
Tests: T1 T2 T3
16691 1/1 assign alert_en_shadowed_45_re = addr_hit[116] & reg_re & !reg_error;
Tests: T1 T2 T3
16692 1/1 assign alert_en_shadowed_45_we = addr_hit[116] & reg_we & !reg_error;
Tests: T1 T2 T3
16693
16694 1/1 assign alert_en_shadowed_45_wd = reg_wdata[0];
Tests: T1 T2 T3
16695 1/1 assign alert_en_shadowed_46_re = addr_hit[117] & reg_re & !reg_error;
Tests: T1 T2 T3
16696 1/1 assign alert_en_shadowed_46_we = addr_hit[117] & reg_we & !reg_error;
Tests: T1 T2 T3
16697
16698 1/1 assign alert_en_shadowed_46_wd = reg_wdata[0];
Tests: T1 T2 T3
16699 1/1 assign alert_en_shadowed_47_re = addr_hit[118] & reg_re & !reg_error;
Tests: T1 T2 T3
16700 1/1 assign alert_en_shadowed_47_we = addr_hit[118] & reg_we & !reg_error;
Tests: T1 T2 T3
16701
16702 1/1 assign alert_en_shadowed_47_wd = reg_wdata[0];
Tests: T1 T2 T3
16703 1/1 assign alert_en_shadowed_48_re = addr_hit[119] & reg_re & !reg_error;
Tests: T1 T2 T3
16704 1/1 assign alert_en_shadowed_48_we = addr_hit[119] & reg_we & !reg_error;
Tests: T1 T2 T3
16705
16706 1/1 assign alert_en_shadowed_48_wd = reg_wdata[0];
Tests: T1 T2 T3
16707 1/1 assign alert_en_shadowed_49_re = addr_hit[120] & reg_re & !reg_error;
Tests: T1 T2 T3
16708 1/1 assign alert_en_shadowed_49_we = addr_hit[120] & reg_we & !reg_error;
Tests: T1 T2 T3
16709
16710 1/1 assign alert_en_shadowed_49_wd = reg_wdata[0];
Tests: T1 T2 T3
16711 1/1 assign alert_en_shadowed_50_re = addr_hit[121] & reg_re & !reg_error;
Tests: T1 T2 T3
16712 1/1 assign alert_en_shadowed_50_we = addr_hit[121] & reg_we & !reg_error;
Tests: T1 T2 T3
16713
16714 1/1 assign alert_en_shadowed_50_wd = reg_wdata[0];
Tests: T1 T2 T3
16715 1/1 assign alert_en_shadowed_51_re = addr_hit[122] & reg_re & !reg_error;
Tests: T1 T2 T3
16716 1/1 assign alert_en_shadowed_51_we = addr_hit[122] & reg_we & !reg_error;
Tests: T1 T2 T3
16717
16718 1/1 assign alert_en_shadowed_51_wd = reg_wdata[0];
Tests: T1 T2 T3
16719 1/1 assign alert_en_shadowed_52_re = addr_hit[123] & reg_re & !reg_error;
Tests: T1 T2 T3
16720 1/1 assign alert_en_shadowed_52_we = addr_hit[123] & reg_we & !reg_error;
Tests: T1 T2 T3
16721
16722 1/1 assign alert_en_shadowed_52_wd = reg_wdata[0];
Tests: T1 T2 T3
16723 1/1 assign alert_en_shadowed_53_re = addr_hit[124] & reg_re & !reg_error;
Tests: T1 T2 T3
16724 1/1 assign alert_en_shadowed_53_we = addr_hit[124] & reg_we & !reg_error;
Tests: T1 T2 T3
16725
16726 1/1 assign alert_en_shadowed_53_wd = reg_wdata[0];
Tests: T1 T2 T3
16727 1/1 assign alert_en_shadowed_54_re = addr_hit[125] & reg_re & !reg_error;
Tests: T1 T2 T3
16728 1/1 assign alert_en_shadowed_54_we = addr_hit[125] & reg_we & !reg_error;
Tests: T1 T2 T3
16729
16730 1/1 assign alert_en_shadowed_54_wd = reg_wdata[0];
Tests: T1 T2 T3
16731 1/1 assign alert_en_shadowed_55_re = addr_hit[126] & reg_re & !reg_error;
Tests: T1 T2 T3
16732 1/1 assign alert_en_shadowed_55_we = addr_hit[126] & reg_we & !reg_error;
Tests: T1 T2 T3
16733
16734 1/1 assign alert_en_shadowed_55_wd = reg_wdata[0];
Tests: T1 T2 T3
16735 1/1 assign alert_en_shadowed_56_re = addr_hit[127] & reg_re & !reg_error;
Tests: T1 T2 T3
16736 1/1 assign alert_en_shadowed_56_we = addr_hit[127] & reg_we & !reg_error;
Tests: T1 T2 T3
16737
16738 1/1 assign alert_en_shadowed_56_wd = reg_wdata[0];
Tests: T1 T2 T3
16739 1/1 assign alert_en_shadowed_57_re = addr_hit[128] & reg_re & !reg_error;
Tests: T1 T2 T3
16740 1/1 assign alert_en_shadowed_57_we = addr_hit[128] & reg_we & !reg_error;
Tests: T1 T2 T3
16741
16742 1/1 assign alert_en_shadowed_57_wd = reg_wdata[0];
Tests: T1 T2 T3
16743 1/1 assign alert_en_shadowed_58_re = addr_hit[129] & reg_re & !reg_error;
Tests: T1 T2 T3
16744 1/1 assign alert_en_shadowed_58_we = addr_hit[129] & reg_we & !reg_error;
Tests: T1 T2 T3
16745
16746 1/1 assign alert_en_shadowed_58_wd = reg_wdata[0];
Tests: T1 T2 T3
16747 1/1 assign alert_en_shadowed_59_re = addr_hit[130] & reg_re & !reg_error;
Tests: T1 T2 T3
16748 1/1 assign alert_en_shadowed_59_we = addr_hit[130] & reg_we & !reg_error;
Tests: T1 T2 T3
16749
16750 1/1 assign alert_en_shadowed_59_wd = reg_wdata[0];
Tests: T1 T2 T3
16751 1/1 assign alert_en_shadowed_60_re = addr_hit[131] & reg_re & !reg_error;
Tests: T1 T2 T3
16752 1/1 assign alert_en_shadowed_60_we = addr_hit[131] & reg_we & !reg_error;
Tests: T1 T2 T3
16753
16754 1/1 assign alert_en_shadowed_60_wd = reg_wdata[0];
Tests: T1 T2 T3
16755 1/1 assign alert_en_shadowed_61_re = addr_hit[132] & reg_re & !reg_error;
Tests: T1 T2 T3
16756 1/1 assign alert_en_shadowed_61_we = addr_hit[132] & reg_we & !reg_error;
Tests: T1 T2 T3
16757
16758 1/1 assign alert_en_shadowed_61_wd = reg_wdata[0];
Tests: T1 T2 T3
16759 1/1 assign alert_en_shadowed_62_re = addr_hit[133] & reg_re & !reg_error;
Tests: T1 T2 T3
16760 1/1 assign alert_en_shadowed_62_we = addr_hit[133] & reg_we & !reg_error;
Tests: T1 T2 T3
16761
16762 1/1 assign alert_en_shadowed_62_wd = reg_wdata[0];
Tests: T1 T2 T3
16763 1/1 assign alert_en_shadowed_63_re = addr_hit[134] & reg_re & !reg_error;
Tests: T1 T2 T3
16764 1/1 assign alert_en_shadowed_63_we = addr_hit[134] & reg_we & !reg_error;
Tests: T1 T2 T3
16765
16766 1/1 assign alert_en_shadowed_63_wd = reg_wdata[0];
Tests: T1 T2 T3
16767 1/1 assign alert_en_shadowed_64_re = addr_hit[135] & reg_re & !reg_error;
Tests: T1 T2 T3
16768 1/1 assign alert_en_shadowed_64_we = addr_hit[135] & reg_we & !reg_error;
Tests: T1 T2 T3
16769
16770 1/1 assign alert_en_shadowed_64_wd = reg_wdata[0];
Tests: T1 T2 T3
16771 1/1 assign alert_class_shadowed_0_re = addr_hit[136] & reg_re & !reg_error;
Tests: T1 T2 T3
16772 1/1 assign alert_class_shadowed_0_we = addr_hit[136] & reg_we & !reg_error;
Tests: T1 T2 T3
16773
16774 1/1 assign alert_class_shadowed_0_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16775 1/1 assign alert_class_shadowed_1_re = addr_hit[137] & reg_re & !reg_error;
Tests: T1 T2 T3
16776 1/1 assign alert_class_shadowed_1_we = addr_hit[137] & reg_we & !reg_error;
Tests: T1 T2 T3
16777
16778 1/1 assign alert_class_shadowed_1_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16779 1/1 assign alert_class_shadowed_2_re = addr_hit[138] & reg_re & !reg_error;
Tests: T1 T2 T3
16780 1/1 assign alert_class_shadowed_2_we = addr_hit[138] & reg_we & !reg_error;
Tests: T1 T2 T3
16781
16782 1/1 assign alert_class_shadowed_2_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16783 1/1 assign alert_class_shadowed_3_re = addr_hit[139] & reg_re & !reg_error;
Tests: T1 T2 T3
16784 1/1 assign alert_class_shadowed_3_we = addr_hit[139] & reg_we & !reg_error;
Tests: T1 T2 T3
16785
16786 1/1 assign alert_class_shadowed_3_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16787 1/1 assign alert_class_shadowed_4_re = addr_hit[140] & reg_re & !reg_error;
Tests: T1 T2 T3
16788 1/1 assign alert_class_shadowed_4_we = addr_hit[140] & reg_we & !reg_error;
Tests: T1 T2 T3
16789
16790 1/1 assign alert_class_shadowed_4_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16791 1/1 assign alert_class_shadowed_5_re = addr_hit[141] & reg_re & !reg_error;
Tests: T1 T2 T3
16792 1/1 assign alert_class_shadowed_5_we = addr_hit[141] & reg_we & !reg_error;
Tests: T1 T2 T3
16793
16794 1/1 assign alert_class_shadowed_5_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16795 1/1 assign alert_class_shadowed_6_re = addr_hit[142] & reg_re & !reg_error;
Tests: T1 T2 T3
16796 1/1 assign alert_class_shadowed_6_we = addr_hit[142] & reg_we & !reg_error;
Tests: T1 T2 T3
16797
16798 1/1 assign alert_class_shadowed_6_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16799 1/1 assign alert_class_shadowed_7_re = addr_hit[143] & reg_re & !reg_error;
Tests: T1 T2 T3
16800 1/1 assign alert_class_shadowed_7_we = addr_hit[143] & reg_we & !reg_error;
Tests: T1 T2 T3
16801
16802 1/1 assign alert_class_shadowed_7_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16803 1/1 assign alert_class_shadowed_8_re = addr_hit[144] & reg_re & !reg_error;
Tests: T1 T2 T3
16804 1/1 assign alert_class_shadowed_8_we = addr_hit[144] & reg_we & !reg_error;
Tests: T1 T2 T3
16805
16806 1/1 assign alert_class_shadowed_8_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16807 1/1 assign alert_class_shadowed_9_re = addr_hit[145] & reg_re & !reg_error;
Tests: T1 T2 T3
16808 1/1 assign alert_class_shadowed_9_we = addr_hit[145] & reg_we & !reg_error;
Tests: T1 T2 T3
16809
16810 1/1 assign alert_class_shadowed_9_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16811 1/1 assign alert_class_shadowed_10_re = addr_hit[146] & reg_re & !reg_error;
Tests: T1 T2 T3
16812 1/1 assign alert_class_shadowed_10_we = addr_hit[146] & reg_we & !reg_error;
Tests: T1 T2 T3
16813
16814 1/1 assign alert_class_shadowed_10_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16815 1/1 assign alert_class_shadowed_11_re = addr_hit[147] & reg_re & !reg_error;
Tests: T1 T2 T3
16816 1/1 assign alert_class_shadowed_11_we = addr_hit[147] & reg_we & !reg_error;
Tests: T1 T2 T3
16817
16818 1/1 assign alert_class_shadowed_11_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16819 1/1 assign alert_class_shadowed_12_re = addr_hit[148] & reg_re & !reg_error;
Tests: T1 T2 T3
16820 1/1 assign alert_class_shadowed_12_we = addr_hit[148] & reg_we & !reg_error;
Tests: T1 T2 T3
16821
16822 1/1 assign alert_class_shadowed_12_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16823 1/1 assign alert_class_shadowed_13_re = addr_hit[149] & reg_re & !reg_error;
Tests: T1 T2 T3
16824 1/1 assign alert_class_shadowed_13_we = addr_hit[149] & reg_we & !reg_error;
Tests: T1 T2 T3
16825
16826 1/1 assign alert_class_shadowed_13_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16827 1/1 assign alert_class_shadowed_14_re = addr_hit[150] & reg_re & !reg_error;
Tests: T1 T2 T3
16828 1/1 assign alert_class_shadowed_14_we = addr_hit[150] & reg_we & !reg_error;
Tests: T1 T2 T3
16829
16830 1/1 assign alert_class_shadowed_14_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16831 1/1 assign alert_class_shadowed_15_re = addr_hit[151] & reg_re & !reg_error;
Tests: T1 T2 T3
16832 1/1 assign alert_class_shadowed_15_we = addr_hit[151] & reg_we & !reg_error;
Tests: T1 T2 T3
16833
16834 1/1 assign alert_class_shadowed_15_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16835 1/1 assign alert_class_shadowed_16_re = addr_hit[152] & reg_re & !reg_error;
Tests: T1 T2 T3
16836 1/1 assign alert_class_shadowed_16_we = addr_hit[152] & reg_we & !reg_error;
Tests: T1 T2 T3
16837
16838 1/1 assign alert_class_shadowed_16_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16839 1/1 assign alert_class_shadowed_17_re = addr_hit[153] & reg_re & !reg_error;
Tests: T1 T2 T3
16840 1/1 assign alert_class_shadowed_17_we = addr_hit[153] & reg_we & !reg_error;
Tests: T1 T2 T3
16841
16842 1/1 assign alert_class_shadowed_17_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16843 1/1 assign alert_class_shadowed_18_re = addr_hit[154] & reg_re & !reg_error;
Tests: T1 T2 T3
16844 1/1 assign alert_class_shadowed_18_we = addr_hit[154] & reg_we & !reg_error;
Tests: T1 T2 T3
16845
16846 1/1 assign alert_class_shadowed_18_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16847 1/1 assign alert_class_shadowed_19_re = addr_hit[155] & reg_re & !reg_error;
Tests: T1 T2 T3
16848 1/1 assign alert_class_shadowed_19_we = addr_hit[155] & reg_we & !reg_error;
Tests: T1 T2 T3
16849
16850 1/1 assign alert_class_shadowed_19_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16851 1/1 assign alert_class_shadowed_20_re = addr_hit[156] & reg_re & !reg_error;
Tests: T1 T2 T3
16852 1/1 assign alert_class_shadowed_20_we = addr_hit[156] & reg_we & !reg_error;
Tests: T1 T2 T3
16853
16854 1/1 assign alert_class_shadowed_20_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16855 1/1 assign alert_class_shadowed_21_re = addr_hit[157] & reg_re & !reg_error;
Tests: T1 T2 T3
16856 1/1 assign alert_class_shadowed_21_we = addr_hit[157] & reg_we & !reg_error;
Tests: T1 T2 T3
16857
16858 1/1 assign alert_class_shadowed_21_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16859 1/1 assign alert_class_shadowed_22_re = addr_hit[158] & reg_re & !reg_error;
Tests: T1 T2 T3
16860 1/1 assign alert_class_shadowed_22_we = addr_hit[158] & reg_we & !reg_error;
Tests: T1 T2 T3
16861
16862 1/1 assign alert_class_shadowed_22_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16863 1/1 assign alert_class_shadowed_23_re = addr_hit[159] & reg_re & !reg_error;
Tests: T1 T2 T3
16864 1/1 assign alert_class_shadowed_23_we = addr_hit[159] & reg_we & !reg_error;
Tests: T1 T2 T3
16865
16866 1/1 assign alert_class_shadowed_23_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16867 1/1 assign alert_class_shadowed_24_re = addr_hit[160] & reg_re & !reg_error;
Tests: T1 T2 T3
16868 1/1 assign alert_class_shadowed_24_we = addr_hit[160] & reg_we & !reg_error;
Tests: T1 T2 T3
16869
16870 1/1 assign alert_class_shadowed_24_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16871 1/1 assign alert_class_shadowed_25_re = addr_hit[161] & reg_re & !reg_error;
Tests: T1 T2 T3
16872 1/1 assign alert_class_shadowed_25_we = addr_hit[161] & reg_we & !reg_error;
Tests: T1 T2 T3
16873
16874 1/1 assign alert_class_shadowed_25_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16875 1/1 assign alert_class_shadowed_26_re = addr_hit[162] & reg_re & !reg_error;
Tests: T1 T2 T3
16876 1/1 assign alert_class_shadowed_26_we = addr_hit[162] & reg_we & !reg_error;
Tests: T1 T2 T3
16877
16878 1/1 assign alert_class_shadowed_26_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16879 1/1 assign alert_class_shadowed_27_re = addr_hit[163] & reg_re & !reg_error;
Tests: T1 T2 T3
16880 1/1 assign alert_class_shadowed_27_we = addr_hit[163] & reg_we & !reg_error;
Tests: T1 T2 T3
16881
16882 1/1 assign alert_class_shadowed_27_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16883 1/1 assign alert_class_shadowed_28_re = addr_hit[164] & reg_re & !reg_error;
Tests: T1 T2 T3
16884 1/1 assign alert_class_shadowed_28_we = addr_hit[164] & reg_we & !reg_error;
Tests: T1 T2 T3
16885
16886 1/1 assign alert_class_shadowed_28_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16887 1/1 assign alert_class_shadowed_29_re = addr_hit[165] & reg_re & !reg_error;
Tests: T1 T2 T3
16888 1/1 assign alert_class_shadowed_29_we = addr_hit[165] & reg_we & !reg_error;
Tests: T1 T2 T3
16889
16890 1/1 assign alert_class_shadowed_29_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16891 1/1 assign alert_class_shadowed_30_re = addr_hit[166] & reg_re & !reg_error;
Tests: T1 T2 T3
16892 1/1 assign alert_class_shadowed_30_we = addr_hit[166] & reg_we & !reg_error;
Tests: T1 T2 T3
16893
16894 1/1 assign alert_class_shadowed_30_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16895 1/1 assign alert_class_shadowed_31_re = addr_hit[167] & reg_re & !reg_error;
Tests: T1 T2 T3
16896 1/1 assign alert_class_shadowed_31_we = addr_hit[167] & reg_we & !reg_error;
Tests: T1 T2 T3
16897
16898 1/1 assign alert_class_shadowed_31_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16899 1/1 assign alert_class_shadowed_32_re = addr_hit[168] & reg_re & !reg_error;
Tests: T1 T2 T3
16900 1/1 assign alert_class_shadowed_32_we = addr_hit[168] & reg_we & !reg_error;
Tests: T1 T2 T3
16901
16902 1/1 assign alert_class_shadowed_32_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16903 1/1 assign alert_class_shadowed_33_re = addr_hit[169] & reg_re & !reg_error;
Tests: T1 T2 T3
16904 1/1 assign alert_class_shadowed_33_we = addr_hit[169] & reg_we & !reg_error;
Tests: T1 T2 T3
16905
16906 1/1 assign alert_class_shadowed_33_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16907 1/1 assign alert_class_shadowed_34_re = addr_hit[170] & reg_re & !reg_error;
Tests: T1 T2 T3
16908 1/1 assign alert_class_shadowed_34_we = addr_hit[170] & reg_we & !reg_error;
Tests: T1 T2 T3
16909
16910 1/1 assign alert_class_shadowed_34_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16911 1/1 assign alert_class_shadowed_35_re = addr_hit[171] & reg_re & !reg_error;
Tests: T1 T2 T3
16912 1/1 assign alert_class_shadowed_35_we = addr_hit[171] & reg_we & !reg_error;
Tests: T1 T2 T3
16913
16914 1/1 assign alert_class_shadowed_35_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16915 1/1 assign alert_class_shadowed_36_re = addr_hit[172] & reg_re & !reg_error;
Tests: T1 T2 T3
16916 1/1 assign alert_class_shadowed_36_we = addr_hit[172] & reg_we & !reg_error;
Tests: T1 T2 T3
16917
16918 1/1 assign alert_class_shadowed_36_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16919 1/1 assign alert_class_shadowed_37_re = addr_hit[173] & reg_re & !reg_error;
Tests: T1 T2 T3
16920 1/1 assign alert_class_shadowed_37_we = addr_hit[173] & reg_we & !reg_error;
Tests: T1 T2 T3
16921
16922 1/1 assign alert_class_shadowed_37_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16923 1/1 assign alert_class_shadowed_38_re = addr_hit[174] & reg_re & !reg_error;
Tests: T1 T2 T3
16924 1/1 assign alert_class_shadowed_38_we = addr_hit[174] & reg_we & !reg_error;
Tests: T1 T2 T3
16925
16926 1/1 assign alert_class_shadowed_38_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16927 1/1 assign alert_class_shadowed_39_re = addr_hit[175] & reg_re & !reg_error;
Tests: T1 T2 T3
16928 1/1 assign alert_class_shadowed_39_we = addr_hit[175] & reg_we & !reg_error;
Tests: T1 T2 T3
16929
16930 1/1 assign alert_class_shadowed_39_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16931 1/1 assign alert_class_shadowed_40_re = addr_hit[176] & reg_re & !reg_error;
Tests: T1 T2 T3
16932 1/1 assign alert_class_shadowed_40_we = addr_hit[176] & reg_we & !reg_error;
Tests: T1 T2 T3
16933
16934 1/1 assign alert_class_shadowed_40_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16935 1/1 assign alert_class_shadowed_41_re = addr_hit[177] & reg_re & !reg_error;
Tests: T1 T2 T3
16936 1/1 assign alert_class_shadowed_41_we = addr_hit[177] & reg_we & !reg_error;
Tests: T1 T2 T3
16937
16938 1/1 assign alert_class_shadowed_41_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16939 1/1 assign alert_class_shadowed_42_re = addr_hit[178] & reg_re & !reg_error;
Tests: T1 T2 T3
16940 1/1 assign alert_class_shadowed_42_we = addr_hit[178] & reg_we & !reg_error;
Tests: T1 T2 T3
16941
16942 1/1 assign alert_class_shadowed_42_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16943 1/1 assign alert_class_shadowed_43_re = addr_hit[179] & reg_re & !reg_error;
Tests: T1 T2 T3
16944 1/1 assign alert_class_shadowed_43_we = addr_hit[179] & reg_we & !reg_error;
Tests: T1 T2 T3
16945
16946 1/1 assign alert_class_shadowed_43_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16947 1/1 assign alert_class_shadowed_44_re = addr_hit[180] & reg_re & !reg_error;
Tests: T1 T2 T3
16948 1/1 assign alert_class_shadowed_44_we = addr_hit[180] & reg_we & !reg_error;
Tests: T1 T2 T3
16949
16950 1/1 assign alert_class_shadowed_44_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16951 1/1 assign alert_class_shadowed_45_re = addr_hit[181] & reg_re & !reg_error;
Tests: T1 T2 T3
16952 1/1 assign alert_class_shadowed_45_we = addr_hit[181] & reg_we & !reg_error;
Tests: T1 T2 T3
16953
16954 1/1 assign alert_class_shadowed_45_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16955 1/1 assign alert_class_shadowed_46_re = addr_hit[182] & reg_re & !reg_error;
Tests: T1 T2 T3
16956 1/1 assign alert_class_shadowed_46_we = addr_hit[182] & reg_we & !reg_error;
Tests: T1 T2 T3
16957
16958 1/1 assign alert_class_shadowed_46_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16959 1/1 assign alert_class_shadowed_47_re = addr_hit[183] & reg_re & !reg_error;
Tests: T1 T2 T3
16960 1/1 assign alert_class_shadowed_47_we = addr_hit[183] & reg_we & !reg_error;
Tests: T1 T2 T3
16961
16962 1/1 assign alert_class_shadowed_47_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16963 1/1 assign alert_class_shadowed_48_re = addr_hit[184] & reg_re & !reg_error;
Tests: T1 T2 T3
16964 1/1 assign alert_class_shadowed_48_we = addr_hit[184] & reg_we & !reg_error;
Tests: T1 T2 T3
16965
16966 1/1 assign alert_class_shadowed_48_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16967 1/1 assign alert_class_shadowed_49_re = addr_hit[185] & reg_re & !reg_error;
Tests: T1 T2 T3
16968 1/1 assign alert_class_shadowed_49_we = addr_hit[185] & reg_we & !reg_error;
Tests: T1 T2 T3
16969
16970 1/1 assign alert_class_shadowed_49_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16971 1/1 assign alert_class_shadowed_50_re = addr_hit[186] & reg_re & !reg_error;
Tests: T1 T2 T3
16972 1/1 assign alert_class_shadowed_50_we = addr_hit[186] & reg_we & !reg_error;
Tests: T1 T2 T3
16973
16974 1/1 assign alert_class_shadowed_50_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16975 1/1 assign alert_class_shadowed_51_re = addr_hit[187] & reg_re & !reg_error;
Tests: T1 T2 T3
16976 1/1 assign alert_class_shadowed_51_we = addr_hit[187] & reg_we & !reg_error;
Tests: T1 T2 T3
16977
16978 1/1 assign alert_class_shadowed_51_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16979 1/1 assign alert_class_shadowed_52_re = addr_hit[188] & reg_re & !reg_error;
Tests: T1 T2 T3
16980 1/1 assign alert_class_shadowed_52_we = addr_hit[188] & reg_we & !reg_error;
Tests: T1 T2 T3
16981
16982 1/1 assign alert_class_shadowed_52_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16983 1/1 assign alert_class_shadowed_53_re = addr_hit[189] & reg_re & !reg_error;
Tests: T1 T2 T3
16984 1/1 assign alert_class_shadowed_53_we = addr_hit[189] & reg_we & !reg_error;
Tests: T1 T2 T3
16985
16986 1/1 assign alert_class_shadowed_53_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16987 1/1 assign alert_class_shadowed_54_re = addr_hit[190] & reg_re & !reg_error;
Tests: T1 T2 T3
16988 1/1 assign alert_class_shadowed_54_we = addr_hit[190] & reg_we & !reg_error;
Tests: T1 T2 T3
16989
16990 1/1 assign alert_class_shadowed_54_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16991 1/1 assign alert_class_shadowed_55_re = addr_hit[191] & reg_re & !reg_error;
Tests: T1 T2 T3
16992 1/1 assign alert_class_shadowed_55_we = addr_hit[191] & reg_we & !reg_error;
Tests: T1 T2 T3
16993
16994 1/1 assign alert_class_shadowed_55_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16995 1/1 assign alert_class_shadowed_56_re = addr_hit[192] & reg_re & !reg_error;
Tests: T1 T2 T3
16996 1/1 assign alert_class_shadowed_56_we = addr_hit[192] & reg_we & !reg_error;
Tests: T1 T2 T3
16997
16998 1/1 assign alert_class_shadowed_56_wd = reg_wdata[1:0];
Tests: T1 T2 T3
16999 1/1 assign alert_class_shadowed_57_re = addr_hit[193] & reg_re & !reg_error;
Tests: T1 T2 T3
17000 1/1 assign alert_class_shadowed_57_we = addr_hit[193] & reg_we & !reg_error;
Tests: T1 T2 T3
17001
17002 1/1 assign alert_class_shadowed_57_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17003 1/1 assign alert_class_shadowed_58_re = addr_hit[194] & reg_re & !reg_error;
Tests: T1 T2 T3
17004 1/1 assign alert_class_shadowed_58_we = addr_hit[194] & reg_we & !reg_error;
Tests: T1 T2 T3
17005
17006 1/1 assign alert_class_shadowed_58_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17007 1/1 assign alert_class_shadowed_59_re = addr_hit[195] & reg_re & !reg_error;
Tests: T1 T2 T3
17008 1/1 assign alert_class_shadowed_59_we = addr_hit[195] & reg_we & !reg_error;
Tests: T1 T2 T3
17009
17010 1/1 assign alert_class_shadowed_59_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17011 1/1 assign alert_class_shadowed_60_re = addr_hit[196] & reg_re & !reg_error;
Tests: T1 T2 T3
17012 1/1 assign alert_class_shadowed_60_we = addr_hit[196] & reg_we & !reg_error;
Tests: T1 T2 T3
17013
17014 1/1 assign alert_class_shadowed_60_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17015 1/1 assign alert_class_shadowed_61_re = addr_hit[197] & reg_re & !reg_error;
Tests: T1 T2 T3
17016 1/1 assign alert_class_shadowed_61_we = addr_hit[197] & reg_we & !reg_error;
Tests: T1 T2 T3
17017
17018 1/1 assign alert_class_shadowed_61_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17019 1/1 assign alert_class_shadowed_62_re = addr_hit[198] & reg_re & !reg_error;
Tests: T1 T2 T3
17020 1/1 assign alert_class_shadowed_62_we = addr_hit[198] & reg_we & !reg_error;
Tests: T1 T2 T3
17021
17022 1/1 assign alert_class_shadowed_62_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17023 1/1 assign alert_class_shadowed_63_re = addr_hit[199] & reg_re & !reg_error;
Tests: T1 T2 T3
17024 1/1 assign alert_class_shadowed_63_we = addr_hit[199] & reg_we & !reg_error;
Tests: T1 T2 T3
17025
17026 1/1 assign alert_class_shadowed_63_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17027 1/1 assign alert_class_shadowed_64_re = addr_hit[200] & reg_re & !reg_error;
Tests: T1 T2 T3
17028 1/1 assign alert_class_shadowed_64_we = addr_hit[200] & reg_we & !reg_error;
Tests: T1 T2 T3
17029
17030 1/1 assign alert_class_shadowed_64_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17031 1/1 assign alert_cause_0_we = addr_hit[201] & reg_we & !reg_error;
Tests: T1 T2 T3
17032
17033 1/1 assign alert_cause_0_wd = reg_wdata[0];
Tests: T1 T2 T3
17034 1/1 assign alert_cause_1_we = addr_hit[202] & reg_we & !reg_error;
Tests: T1 T2 T3
17035
17036 1/1 assign alert_cause_1_wd = reg_wdata[0];
Tests: T1 T2 T3
17037 1/1 assign alert_cause_2_we = addr_hit[203] & reg_we & !reg_error;
Tests: T1 T2 T3
17038
17039 1/1 assign alert_cause_2_wd = reg_wdata[0];
Tests: T1 T2 T3
17040 1/1 assign alert_cause_3_we = addr_hit[204] & reg_we & !reg_error;
Tests: T1 T2 T3
17041
17042 1/1 assign alert_cause_3_wd = reg_wdata[0];
Tests: T1 T2 T3
17043 1/1 assign alert_cause_4_we = addr_hit[205] & reg_we & !reg_error;
Tests: T1 T2 T3
17044
17045 1/1 assign alert_cause_4_wd = reg_wdata[0];
Tests: T1 T2 T3
17046 1/1 assign alert_cause_5_we = addr_hit[206] & reg_we & !reg_error;
Tests: T1 T2 T3
17047
17048 1/1 assign alert_cause_5_wd = reg_wdata[0];
Tests: T1 T2 T3
17049 1/1 assign alert_cause_6_we = addr_hit[207] & reg_we & !reg_error;
Tests: T1 T2 T3
17050
17051 1/1 assign alert_cause_6_wd = reg_wdata[0];
Tests: T1 T2 T3
17052 1/1 assign alert_cause_7_we = addr_hit[208] & reg_we & !reg_error;
Tests: T1 T2 T3
17053
17054 1/1 assign alert_cause_7_wd = reg_wdata[0];
Tests: T1 T2 T3
17055 1/1 assign alert_cause_8_we = addr_hit[209] & reg_we & !reg_error;
Tests: T1 T2 T3
17056
17057 1/1 assign alert_cause_8_wd = reg_wdata[0];
Tests: T1 T2 T3
17058 1/1 assign alert_cause_9_we = addr_hit[210] & reg_we & !reg_error;
Tests: T1 T2 T3
17059
17060 1/1 assign alert_cause_9_wd = reg_wdata[0];
Tests: T1 T2 T3
17061 1/1 assign alert_cause_10_we = addr_hit[211] & reg_we & !reg_error;
Tests: T1 T2 T3
17062
17063 1/1 assign alert_cause_10_wd = reg_wdata[0];
Tests: T1 T2 T3
17064 1/1 assign alert_cause_11_we = addr_hit[212] & reg_we & !reg_error;
Tests: T1 T2 T3
17065
17066 1/1 assign alert_cause_11_wd = reg_wdata[0];
Tests: T1 T2 T3
17067 1/1 assign alert_cause_12_we = addr_hit[213] & reg_we & !reg_error;
Tests: T1 T2 T3
17068
17069 1/1 assign alert_cause_12_wd = reg_wdata[0];
Tests: T1 T2 T3
17070 1/1 assign alert_cause_13_we = addr_hit[214] & reg_we & !reg_error;
Tests: T1 T2 T3
17071
17072 1/1 assign alert_cause_13_wd = reg_wdata[0];
Tests: T1 T2 T3
17073 1/1 assign alert_cause_14_we = addr_hit[215] & reg_we & !reg_error;
Tests: T1 T2 T3
17074
17075 1/1 assign alert_cause_14_wd = reg_wdata[0];
Tests: T1 T2 T3
17076 1/1 assign alert_cause_15_we = addr_hit[216] & reg_we & !reg_error;
Tests: T1 T2 T3
17077
17078 1/1 assign alert_cause_15_wd = reg_wdata[0];
Tests: T1 T2 T3
17079 1/1 assign alert_cause_16_we = addr_hit[217] & reg_we & !reg_error;
Tests: T1 T2 T3
17080
17081 1/1 assign alert_cause_16_wd = reg_wdata[0];
Tests: T1 T2 T3
17082 1/1 assign alert_cause_17_we = addr_hit[218] & reg_we & !reg_error;
Tests: T1 T2 T3
17083
17084 1/1 assign alert_cause_17_wd = reg_wdata[0];
Tests: T1 T2 T3
17085 1/1 assign alert_cause_18_we = addr_hit[219] & reg_we & !reg_error;
Tests: T1 T2 T3
17086
17087 1/1 assign alert_cause_18_wd = reg_wdata[0];
Tests: T1 T2 T3
17088 1/1 assign alert_cause_19_we = addr_hit[220] & reg_we & !reg_error;
Tests: T1 T2 T3
17089
17090 1/1 assign alert_cause_19_wd = reg_wdata[0];
Tests: T1 T2 T3
17091 1/1 assign alert_cause_20_we = addr_hit[221] & reg_we & !reg_error;
Tests: T1 T2 T3
17092
17093 1/1 assign alert_cause_20_wd = reg_wdata[0];
Tests: T1 T2 T3
17094 1/1 assign alert_cause_21_we = addr_hit[222] & reg_we & !reg_error;
Tests: T1 T2 T3
17095
17096 1/1 assign alert_cause_21_wd = reg_wdata[0];
Tests: T1 T2 T3
17097 1/1 assign alert_cause_22_we = addr_hit[223] & reg_we & !reg_error;
Tests: T1 T2 T3
17098
17099 1/1 assign alert_cause_22_wd = reg_wdata[0];
Tests: T1 T2 T3
17100 1/1 assign alert_cause_23_we = addr_hit[224] & reg_we & !reg_error;
Tests: T1 T2 T3
17101
17102 1/1 assign alert_cause_23_wd = reg_wdata[0];
Tests: T1 T2 T3
17103 1/1 assign alert_cause_24_we = addr_hit[225] & reg_we & !reg_error;
Tests: T1 T2 T3
17104
17105 1/1 assign alert_cause_24_wd = reg_wdata[0];
Tests: T1 T2 T3
17106 1/1 assign alert_cause_25_we = addr_hit[226] & reg_we & !reg_error;
Tests: T1 T2 T3
17107
17108 1/1 assign alert_cause_25_wd = reg_wdata[0];
Tests: T1 T2 T3
17109 1/1 assign alert_cause_26_we = addr_hit[227] & reg_we & !reg_error;
Tests: T1 T2 T3
17110
17111 1/1 assign alert_cause_26_wd = reg_wdata[0];
Tests: T1 T2 T3
17112 1/1 assign alert_cause_27_we = addr_hit[228] & reg_we & !reg_error;
Tests: T1 T2 T3
17113
17114 1/1 assign alert_cause_27_wd = reg_wdata[0];
Tests: T1 T2 T3
17115 1/1 assign alert_cause_28_we = addr_hit[229] & reg_we & !reg_error;
Tests: T1 T2 T3
17116
17117 1/1 assign alert_cause_28_wd = reg_wdata[0];
Tests: T1 T2 T3
17118 1/1 assign alert_cause_29_we = addr_hit[230] & reg_we & !reg_error;
Tests: T1 T2 T3
17119
17120 1/1 assign alert_cause_29_wd = reg_wdata[0];
Tests: T1 T2 T3
17121 1/1 assign alert_cause_30_we = addr_hit[231] & reg_we & !reg_error;
Tests: T1 T2 T3
17122
17123 1/1 assign alert_cause_30_wd = reg_wdata[0];
Tests: T1 T2 T3
17124 1/1 assign alert_cause_31_we = addr_hit[232] & reg_we & !reg_error;
Tests: T1 T2 T3
17125
17126 1/1 assign alert_cause_31_wd = reg_wdata[0];
Tests: T1 T2 T3
17127 1/1 assign alert_cause_32_we = addr_hit[233] & reg_we & !reg_error;
Tests: T1 T2 T3
17128
17129 1/1 assign alert_cause_32_wd = reg_wdata[0];
Tests: T1 T2 T3
17130 1/1 assign alert_cause_33_we = addr_hit[234] & reg_we & !reg_error;
Tests: T1 T2 T3
17131
17132 1/1 assign alert_cause_33_wd = reg_wdata[0];
Tests: T1 T2 T3
17133 1/1 assign alert_cause_34_we = addr_hit[235] & reg_we & !reg_error;
Tests: T1 T2 T3
17134
17135 1/1 assign alert_cause_34_wd = reg_wdata[0];
Tests: T1 T2 T3
17136 1/1 assign alert_cause_35_we = addr_hit[236] & reg_we & !reg_error;
Tests: T1 T2 T3
17137
17138 1/1 assign alert_cause_35_wd = reg_wdata[0];
Tests: T1 T2 T3
17139 1/1 assign alert_cause_36_we = addr_hit[237] & reg_we & !reg_error;
Tests: T1 T2 T3
17140
17141 1/1 assign alert_cause_36_wd = reg_wdata[0];
Tests: T1 T2 T3
17142 1/1 assign alert_cause_37_we = addr_hit[238] & reg_we & !reg_error;
Tests: T1 T2 T3
17143
17144 1/1 assign alert_cause_37_wd = reg_wdata[0];
Tests: T1 T2 T3
17145 1/1 assign alert_cause_38_we = addr_hit[239] & reg_we & !reg_error;
Tests: T1 T2 T3
17146
17147 1/1 assign alert_cause_38_wd = reg_wdata[0];
Tests: T1 T2 T3
17148 1/1 assign alert_cause_39_we = addr_hit[240] & reg_we & !reg_error;
Tests: T1 T2 T3
17149
17150 1/1 assign alert_cause_39_wd = reg_wdata[0];
Tests: T1 T2 T3
17151 1/1 assign alert_cause_40_we = addr_hit[241] & reg_we & !reg_error;
Tests: T1 T2 T3
17152
17153 1/1 assign alert_cause_40_wd = reg_wdata[0];
Tests: T1 T2 T3
17154 1/1 assign alert_cause_41_we = addr_hit[242] & reg_we & !reg_error;
Tests: T1 T2 T3
17155
17156 1/1 assign alert_cause_41_wd = reg_wdata[0];
Tests: T1 T2 T3
17157 1/1 assign alert_cause_42_we = addr_hit[243] & reg_we & !reg_error;
Tests: T1 T2 T3
17158
17159 1/1 assign alert_cause_42_wd = reg_wdata[0];
Tests: T1 T2 T3
17160 1/1 assign alert_cause_43_we = addr_hit[244] & reg_we & !reg_error;
Tests: T1 T2 T3
17161
17162 1/1 assign alert_cause_43_wd = reg_wdata[0];
Tests: T1 T2 T3
17163 1/1 assign alert_cause_44_we = addr_hit[245] & reg_we & !reg_error;
Tests: T1 T2 T3
17164
17165 1/1 assign alert_cause_44_wd = reg_wdata[0];
Tests: T1 T2 T3
17166 1/1 assign alert_cause_45_we = addr_hit[246] & reg_we & !reg_error;
Tests: T1 T2 T3
17167
17168 1/1 assign alert_cause_45_wd = reg_wdata[0];
Tests: T1 T2 T3
17169 1/1 assign alert_cause_46_we = addr_hit[247] & reg_we & !reg_error;
Tests: T1 T2 T3
17170
17171 1/1 assign alert_cause_46_wd = reg_wdata[0];
Tests: T1 T2 T3
17172 1/1 assign alert_cause_47_we = addr_hit[248] & reg_we & !reg_error;
Tests: T1 T2 T3
17173
17174 1/1 assign alert_cause_47_wd = reg_wdata[0];
Tests: T1 T2 T3
17175 1/1 assign alert_cause_48_we = addr_hit[249] & reg_we & !reg_error;
Tests: T1 T2 T3
17176
17177 1/1 assign alert_cause_48_wd = reg_wdata[0];
Tests: T1 T2 T3
17178 1/1 assign alert_cause_49_we = addr_hit[250] & reg_we & !reg_error;
Tests: T1 T2 T3
17179
17180 1/1 assign alert_cause_49_wd = reg_wdata[0];
Tests: T1 T2 T3
17181 1/1 assign alert_cause_50_we = addr_hit[251] & reg_we & !reg_error;
Tests: T1 T2 T3
17182
17183 1/1 assign alert_cause_50_wd = reg_wdata[0];
Tests: T1 T2 T3
17184 1/1 assign alert_cause_51_we = addr_hit[252] & reg_we & !reg_error;
Tests: T1 T2 T3
17185
17186 1/1 assign alert_cause_51_wd = reg_wdata[0];
Tests: T1 T2 T3
17187 1/1 assign alert_cause_52_we = addr_hit[253] & reg_we & !reg_error;
Tests: T1 T2 T3
17188
17189 1/1 assign alert_cause_52_wd = reg_wdata[0];
Tests: T1 T2 T3
17190 1/1 assign alert_cause_53_we = addr_hit[254] & reg_we & !reg_error;
Tests: T1 T2 T3
17191
17192 1/1 assign alert_cause_53_wd = reg_wdata[0];
Tests: T1 T2 T3
17193 1/1 assign alert_cause_54_we = addr_hit[255] & reg_we & !reg_error;
Tests: T1 T2 T3
17194
17195 1/1 assign alert_cause_54_wd = reg_wdata[0];
Tests: T1 T2 T3
17196 1/1 assign alert_cause_55_we = addr_hit[256] & reg_we & !reg_error;
Tests: T1 T2 T3
17197
17198 1/1 assign alert_cause_55_wd = reg_wdata[0];
Tests: T1 T2 T3
17199 1/1 assign alert_cause_56_we = addr_hit[257] & reg_we & !reg_error;
Tests: T1 T2 T3
17200
17201 1/1 assign alert_cause_56_wd = reg_wdata[0];
Tests: T1 T2 T3
17202 1/1 assign alert_cause_57_we = addr_hit[258] & reg_we & !reg_error;
Tests: T1 T2 T3
17203
17204 1/1 assign alert_cause_57_wd = reg_wdata[0];
Tests: T1 T2 T3
17205 1/1 assign alert_cause_58_we = addr_hit[259] & reg_we & !reg_error;
Tests: T1 T2 T3
17206
17207 1/1 assign alert_cause_58_wd = reg_wdata[0];
Tests: T1 T2 T3
17208 1/1 assign alert_cause_59_we = addr_hit[260] & reg_we & !reg_error;
Tests: T1 T2 T3
17209
17210 1/1 assign alert_cause_59_wd = reg_wdata[0];
Tests: T1 T2 T3
17211 1/1 assign alert_cause_60_we = addr_hit[261] & reg_we & !reg_error;
Tests: T1 T2 T3
17212
17213 1/1 assign alert_cause_60_wd = reg_wdata[0];
Tests: T1 T2 T3
17214 1/1 assign alert_cause_61_we = addr_hit[262] & reg_we & !reg_error;
Tests: T1 T2 T3
17215
17216 1/1 assign alert_cause_61_wd = reg_wdata[0];
Tests: T1 T2 T3
17217 1/1 assign alert_cause_62_we = addr_hit[263] & reg_we & !reg_error;
Tests: T1 T2 T3
17218
17219 1/1 assign alert_cause_62_wd = reg_wdata[0];
Tests: T1 T2 T3
17220 1/1 assign alert_cause_63_we = addr_hit[264] & reg_we & !reg_error;
Tests: T1 T2 T3
17221
17222 1/1 assign alert_cause_63_wd = reg_wdata[0];
Tests: T1 T2 T3
17223 1/1 assign alert_cause_64_we = addr_hit[265] & reg_we & !reg_error;
Tests: T1 T2 T3
17224
17225 1/1 assign alert_cause_64_wd = reg_wdata[0];
Tests: T1 T2 T3
17226 1/1 assign loc_alert_regwen_0_we = addr_hit[266] & reg_we & !reg_error;
Tests: T1 T2 T3
17227
17228 1/1 assign loc_alert_regwen_0_wd = reg_wdata[0];
Tests: T1 T2 T3
17229 1/1 assign loc_alert_regwen_1_we = addr_hit[267] & reg_we & !reg_error;
Tests: T1 T2 T3
17230
17231 1/1 assign loc_alert_regwen_1_wd = reg_wdata[0];
Tests: T1 T2 T3
17232 1/1 assign loc_alert_regwen_2_we = addr_hit[268] & reg_we & !reg_error;
Tests: T1 T2 T3
17233
17234 1/1 assign loc_alert_regwen_2_wd = reg_wdata[0];
Tests: T1 T2 T3
17235 1/1 assign loc_alert_regwen_3_we = addr_hit[269] & reg_we & !reg_error;
Tests: T1 T2 T3
17236
17237 1/1 assign loc_alert_regwen_3_wd = reg_wdata[0];
Tests: T1 T2 T3
17238 1/1 assign loc_alert_regwen_4_we = addr_hit[270] & reg_we & !reg_error;
Tests: T1 T2 T3
17239
17240 1/1 assign loc_alert_regwen_4_wd = reg_wdata[0];
Tests: T1 T2 T3
17241 1/1 assign loc_alert_regwen_5_we = addr_hit[271] & reg_we & !reg_error;
Tests: T1 T2 T3
17242
17243 1/1 assign loc_alert_regwen_5_wd = reg_wdata[0];
Tests: T1 T2 T3
17244 1/1 assign loc_alert_regwen_6_we = addr_hit[272] & reg_we & !reg_error;
Tests: T1 T2 T3
17245
17246 1/1 assign loc_alert_regwen_6_wd = reg_wdata[0];
Tests: T1 T2 T3
17247 1/1 assign loc_alert_en_shadowed_0_re = addr_hit[273] & reg_re & !reg_error;
Tests: T1 T2 T3
17248 1/1 assign loc_alert_en_shadowed_0_we = addr_hit[273] & reg_we & !reg_error;
Tests: T1 T2 T3
17249
17250 1/1 assign loc_alert_en_shadowed_0_wd = reg_wdata[0];
Tests: T1 T2 T3
17251 1/1 assign loc_alert_en_shadowed_1_re = addr_hit[274] & reg_re & !reg_error;
Tests: T1 T2 T3
17252 1/1 assign loc_alert_en_shadowed_1_we = addr_hit[274] & reg_we & !reg_error;
Tests: T1 T2 T3
17253
17254 1/1 assign loc_alert_en_shadowed_1_wd = reg_wdata[0];
Tests: T1 T2 T3
17255 1/1 assign loc_alert_en_shadowed_2_re = addr_hit[275] & reg_re & !reg_error;
Tests: T1 T2 T3
17256 1/1 assign loc_alert_en_shadowed_2_we = addr_hit[275] & reg_we & !reg_error;
Tests: T1 T2 T3
17257
17258 1/1 assign loc_alert_en_shadowed_2_wd = reg_wdata[0];
Tests: T1 T2 T3
17259 1/1 assign loc_alert_en_shadowed_3_re = addr_hit[276] & reg_re & !reg_error;
Tests: T1 T2 T3
17260 1/1 assign loc_alert_en_shadowed_3_we = addr_hit[276] & reg_we & !reg_error;
Tests: T1 T2 T3
17261
17262 1/1 assign loc_alert_en_shadowed_3_wd = reg_wdata[0];
Tests: T1 T2 T3
17263 1/1 assign loc_alert_en_shadowed_4_re = addr_hit[277] & reg_re & !reg_error;
Tests: T1 T2 T3
17264 1/1 assign loc_alert_en_shadowed_4_we = addr_hit[277] & reg_we & !reg_error;
Tests: T1 T2 T3
17265
17266 1/1 assign loc_alert_en_shadowed_4_wd = reg_wdata[0];
Tests: T1 T2 T3
17267 1/1 assign loc_alert_en_shadowed_5_re = addr_hit[278] & reg_re & !reg_error;
Tests: T1 T2 T3
17268 1/1 assign loc_alert_en_shadowed_5_we = addr_hit[278] & reg_we & !reg_error;
Tests: T1 T2 T3
17269
17270 1/1 assign loc_alert_en_shadowed_5_wd = reg_wdata[0];
Tests: T1 T2 T3
17271 1/1 assign loc_alert_en_shadowed_6_re = addr_hit[279] & reg_re & !reg_error;
Tests: T1 T2 T3
17272 1/1 assign loc_alert_en_shadowed_6_we = addr_hit[279] & reg_we & !reg_error;
Tests: T1 T2 T3
17273
17274 1/1 assign loc_alert_en_shadowed_6_wd = reg_wdata[0];
Tests: T1 T2 T3
17275 1/1 assign loc_alert_class_shadowed_0_re = addr_hit[280] & reg_re & !reg_error;
Tests: T1 T2 T3
17276 1/1 assign loc_alert_class_shadowed_0_we = addr_hit[280] & reg_we & !reg_error;
Tests: T1 T2 T3
17277
17278 1/1 assign loc_alert_class_shadowed_0_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17279 1/1 assign loc_alert_class_shadowed_1_re = addr_hit[281] & reg_re & !reg_error;
Tests: T1 T2 T3
17280 1/1 assign loc_alert_class_shadowed_1_we = addr_hit[281] & reg_we & !reg_error;
Tests: T1 T2 T3
17281
17282 1/1 assign loc_alert_class_shadowed_1_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17283 1/1 assign loc_alert_class_shadowed_2_re = addr_hit[282] & reg_re & !reg_error;
Tests: T1 T2 T3
17284 1/1 assign loc_alert_class_shadowed_2_we = addr_hit[282] & reg_we & !reg_error;
Tests: T1 T2 T3
17285
17286 1/1 assign loc_alert_class_shadowed_2_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17287 1/1 assign loc_alert_class_shadowed_3_re = addr_hit[283] & reg_re & !reg_error;
Tests: T1 T2 T3
17288 1/1 assign loc_alert_class_shadowed_3_we = addr_hit[283] & reg_we & !reg_error;
Tests: T1 T2 T3
17289
17290 1/1 assign loc_alert_class_shadowed_3_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17291 1/1 assign loc_alert_class_shadowed_4_re = addr_hit[284] & reg_re & !reg_error;
Tests: T1 T2 T3
17292 1/1 assign loc_alert_class_shadowed_4_we = addr_hit[284] & reg_we & !reg_error;
Tests: T1 T2 T3
17293
17294 1/1 assign loc_alert_class_shadowed_4_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17295 1/1 assign loc_alert_class_shadowed_5_re = addr_hit[285] & reg_re & !reg_error;
Tests: T1 T2 T3
17296 1/1 assign loc_alert_class_shadowed_5_we = addr_hit[285] & reg_we & !reg_error;
Tests: T1 T2 T3
17297
17298 1/1 assign loc_alert_class_shadowed_5_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17299 1/1 assign loc_alert_class_shadowed_6_re = addr_hit[286] & reg_re & !reg_error;
Tests: T1 T2 T3
17300 1/1 assign loc_alert_class_shadowed_6_we = addr_hit[286] & reg_we & !reg_error;
Tests: T1 T2 T3
17301
17302 1/1 assign loc_alert_class_shadowed_6_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17303 1/1 assign loc_alert_cause_0_we = addr_hit[287] & reg_we & !reg_error;
Tests: T1 T2 T3
17304
17305 1/1 assign loc_alert_cause_0_wd = reg_wdata[0];
Tests: T1 T2 T3
17306 1/1 assign loc_alert_cause_1_we = addr_hit[288] & reg_we & !reg_error;
Tests: T1 T2 T3
17307
17308 1/1 assign loc_alert_cause_1_wd = reg_wdata[0];
Tests: T1 T2 T3
17309 1/1 assign loc_alert_cause_2_we = addr_hit[289] & reg_we & !reg_error;
Tests: T1 T2 T3
17310
17311 1/1 assign loc_alert_cause_2_wd = reg_wdata[0];
Tests: T1 T2 T3
17312 1/1 assign loc_alert_cause_3_we = addr_hit[290] & reg_we & !reg_error;
Tests: T1 T2 T3
17313
17314 1/1 assign loc_alert_cause_3_wd = reg_wdata[0];
Tests: T1 T2 T3
17315 1/1 assign loc_alert_cause_4_we = addr_hit[291] & reg_we & !reg_error;
Tests: T1 T2 T3
17316
17317 1/1 assign loc_alert_cause_4_wd = reg_wdata[0];
Tests: T1 T2 T3
17318 1/1 assign loc_alert_cause_5_we = addr_hit[292] & reg_we & !reg_error;
Tests: T1 T2 T3
17319
17320 1/1 assign loc_alert_cause_5_wd = reg_wdata[0];
Tests: T1 T2 T3
17321 1/1 assign loc_alert_cause_6_we = addr_hit[293] & reg_we & !reg_error;
Tests: T1 T2 T3
17322
17323 1/1 assign loc_alert_cause_6_wd = reg_wdata[0];
Tests: T1 T2 T3
17324 1/1 assign classa_regwen_we = addr_hit[294] & reg_we & !reg_error;
Tests: T1 T2 T3
17325
17326 1/1 assign classa_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17327 1/1 assign classa_ctrl_shadowed_re = addr_hit[295] & reg_re & !reg_error;
Tests: T1 T2 T3
17328 1/1 assign classa_ctrl_shadowed_we = addr_hit[295] & reg_we & !reg_error;
Tests: T1 T2 T3
17329
17330 1/1 assign classa_ctrl_shadowed_en_wd = reg_wdata[0];
Tests: T1 T2 T3
17331
17332 1/1 assign classa_ctrl_shadowed_lock_wd = reg_wdata[1];
Tests: T1 T2 T3
17333
17334 1/1 assign classa_ctrl_shadowed_en_e0_wd = reg_wdata[2];
Tests: T1 T2 T3
17335
17336 1/1 assign classa_ctrl_shadowed_en_e1_wd = reg_wdata[3];
Tests: T1 T2 T3
17337
17338 1/1 assign classa_ctrl_shadowed_en_e2_wd = reg_wdata[4];
Tests: T1 T2 T3
17339
17340 1/1 assign classa_ctrl_shadowed_en_e3_wd = reg_wdata[5];
Tests: T1 T2 T3
17341
17342 1/1 assign classa_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
Tests: T1 T2 T3
17343
17344 1/1 assign classa_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
Tests: T1 T2 T3
17345
17346 1/1 assign classa_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
Tests: T1 T2 T3
17347
17348 1/1 assign classa_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
Tests: T1 T2 T3
17349 1/1 assign classa_clr_regwen_we = addr_hit[296] & reg_we & !reg_error;
Tests: T1 T2 T3
17350
17351 1/1 assign classa_clr_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17352 1/1 assign classa_clr_shadowed_re = addr_hit[297] & reg_re & !reg_error;
Tests: T1 T2 T3
17353 1/1 assign classa_clr_shadowed_we = addr_hit[297] & reg_we & !reg_error;
Tests: T1 T2 T3
17354
17355 1/1 assign classa_clr_shadowed_wd = reg_wdata[0];
Tests: T1 T2 T3
17356 1/1 assign classa_accum_cnt_re = addr_hit[298] & reg_re & !reg_error;
Tests: T1 T2 T3
17357 1/1 assign classa_accum_thresh_shadowed_re = addr_hit[299] & reg_re & !reg_error;
Tests: T1 T2 T3
17358 1/1 assign classa_accum_thresh_shadowed_we = addr_hit[299] & reg_we & !reg_error;
Tests: T1 T2 T3
17359
17360 1/1 assign classa_accum_thresh_shadowed_wd = reg_wdata[15:0];
Tests: T1 T2 T3
17361 1/1 assign classa_timeout_cyc_shadowed_re = addr_hit[300] & reg_re & !reg_error;
Tests: T1 T2 T3
17362 1/1 assign classa_timeout_cyc_shadowed_we = addr_hit[300] & reg_we & !reg_error;
Tests: T1 T2 T3
17363
17364 1/1 assign classa_timeout_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17365 1/1 assign classa_crashdump_trigger_shadowed_re = addr_hit[301] & reg_re & !reg_error;
Tests: T1 T2 T3
17366 1/1 assign classa_crashdump_trigger_shadowed_we = addr_hit[301] & reg_we & !reg_error;
Tests: T1 T2 T3
17367
17368 1/1 assign classa_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17369 1/1 assign classa_phase0_cyc_shadowed_re = addr_hit[302] & reg_re & !reg_error;
Tests: T1 T2 T3
17370 1/1 assign classa_phase0_cyc_shadowed_we = addr_hit[302] & reg_we & !reg_error;
Tests: T1 T2 T3
17371
17372 1/1 assign classa_phase0_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17373 1/1 assign classa_phase1_cyc_shadowed_re = addr_hit[303] & reg_re & !reg_error;
Tests: T1 T2 T3
17374 1/1 assign classa_phase1_cyc_shadowed_we = addr_hit[303] & reg_we & !reg_error;
Tests: T1 T2 T3
17375
17376 1/1 assign classa_phase1_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17377 1/1 assign classa_phase2_cyc_shadowed_re = addr_hit[304] & reg_re & !reg_error;
Tests: T1 T2 T3
17378 1/1 assign classa_phase2_cyc_shadowed_we = addr_hit[304] & reg_we & !reg_error;
Tests: T1 T2 T3
17379
17380 1/1 assign classa_phase2_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17381 1/1 assign classa_phase3_cyc_shadowed_re = addr_hit[305] & reg_re & !reg_error;
Tests: T1 T2 T3
17382 1/1 assign classa_phase3_cyc_shadowed_we = addr_hit[305] & reg_we & !reg_error;
Tests: T1 T2 T3
17383
17384 1/1 assign classa_phase3_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17385 1/1 assign classa_esc_cnt_re = addr_hit[306] & reg_re & !reg_error;
Tests: T1 T2 T3
17386 1/1 assign classa_state_re = addr_hit[307] & reg_re & !reg_error;
Tests: T1 T2 T3
17387 1/1 assign classb_regwen_we = addr_hit[308] & reg_we & !reg_error;
Tests: T1 T2 T3
17388
17389 1/1 assign classb_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17390 1/1 assign classb_ctrl_shadowed_re = addr_hit[309] & reg_re & !reg_error;
Tests: T1 T2 T3
17391 1/1 assign classb_ctrl_shadowed_we = addr_hit[309] & reg_we & !reg_error;
Tests: T1 T2 T3
17392
17393 1/1 assign classb_ctrl_shadowed_en_wd = reg_wdata[0];
Tests: T1 T2 T3
17394
17395 1/1 assign classb_ctrl_shadowed_lock_wd = reg_wdata[1];
Tests: T1 T2 T3
17396
17397 1/1 assign classb_ctrl_shadowed_en_e0_wd = reg_wdata[2];
Tests: T1 T2 T3
17398
17399 1/1 assign classb_ctrl_shadowed_en_e1_wd = reg_wdata[3];
Tests: T1 T2 T3
17400
17401 1/1 assign classb_ctrl_shadowed_en_e2_wd = reg_wdata[4];
Tests: T1 T2 T3
17402
17403 1/1 assign classb_ctrl_shadowed_en_e3_wd = reg_wdata[5];
Tests: T1 T2 T3
17404
17405 1/1 assign classb_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
Tests: T1 T2 T3
17406
17407 1/1 assign classb_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
Tests: T1 T2 T3
17408
17409 1/1 assign classb_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
Tests: T1 T2 T3
17410
17411 1/1 assign classb_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
Tests: T1 T2 T3
17412 1/1 assign classb_clr_regwen_we = addr_hit[310] & reg_we & !reg_error;
Tests: T1 T2 T3
17413
17414 1/1 assign classb_clr_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17415 1/1 assign classb_clr_shadowed_re = addr_hit[311] & reg_re & !reg_error;
Tests: T1 T2 T3
17416 1/1 assign classb_clr_shadowed_we = addr_hit[311] & reg_we & !reg_error;
Tests: T1 T2 T3
17417
17418 1/1 assign classb_clr_shadowed_wd = reg_wdata[0];
Tests: T1 T2 T3
17419 1/1 assign classb_accum_cnt_re = addr_hit[312] & reg_re & !reg_error;
Tests: T1 T2 T3
17420 1/1 assign classb_accum_thresh_shadowed_re = addr_hit[313] & reg_re & !reg_error;
Tests: T1 T2 T3
17421 1/1 assign classb_accum_thresh_shadowed_we = addr_hit[313] & reg_we & !reg_error;
Tests: T1 T2 T3
17422
17423 1/1 assign classb_accum_thresh_shadowed_wd = reg_wdata[15:0];
Tests: T1 T2 T3
17424 1/1 assign classb_timeout_cyc_shadowed_re = addr_hit[314] & reg_re & !reg_error;
Tests: T1 T2 T3
17425 1/1 assign classb_timeout_cyc_shadowed_we = addr_hit[314] & reg_we & !reg_error;
Tests: T1 T2 T3
17426
17427 1/1 assign classb_timeout_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17428 1/1 assign classb_crashdump_trigger_shadowed_re = addr_hit[315] & reg_re & !reg_error;
Tests: T1 T2 T3
17429 1/1 assign classb_crashdump_trigger_shadowed_we = addr_hit[315] & reg_we & !reg_error;
Tests: T1 T2 T3
17430
17431 1/1 assign classb_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17432 1/1 assign classb_phase0_cyc_shadowed_re = addr_hit[316] & reg_re & !reg_error;
Tests: T1 T2 T3
17433 1/1 assign classb_phase0_cyc_shadowed_we = addr_hit[316] & reg_we & !reg_error;
Tests: T1 T2 T3
17434
17435 1/1 assign classb_phase0_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17436 1/1 assign classb_phase1_cyc_shadowed_re = addr_hit[317] & reg_re & !reg_error;
Tests: T1 T2 T3
17437 1/1 assign classb_phase1_cyc_shadowed_we = addr_hit[317] & reg_we & !reg_error;
Tests: T1 T2 T3
17438
17439 1/1 assign classb_phase1_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17440 1/1 assign classb_phase2_cyc_shadowed_re = addr_hit[318] & reg_re & !reg_error;
Tests: T1 T2 T3
17441 1/1 assign classb_phase2_cyc_shadowed_we = addr_hit[318] & reg_we & !reg_error;
Tests: T1 T2 T3
17442
17443 1/1 assign classb_phase2_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17444 1/1 assign classb_phase3_cyc_shadowed_re = addr_hit[319] & reg_re & !reg_error;
Tests: T1 T2 T3
17445 1/1 assign classb_phase3_cyc_shadowed_we = addr_hit[319] & reg_we & !reg_error;
Tests: T1 T2 T3
17446
17447 1/1 assign classb_phase3_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17448 1/1 assign classb_esc_cnt_re = addr_hit[320] & reg_re & !reg_error;
Tests: T1 T2 T3
17449 1/1 assign classb_state_re = addr_hit[321] & reg_re & !reg_error;
Tests: T1 T2 T3
17450 1/1 assign classc_regwen_we = addr_hit[322] & reg_we & !reg_error;
Tests: T1 T2 T3
17451
17452 1/1 assign classc_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17453 1/1 assign classc_ctrl_shadowed_re = addr_hit[323] & reg_re & !reg_error;
Tests: T1 T2 T3
17454 1/1 assign classc_ctrl_shadowed_we = addr_hit[323] & reg_we & !reg_error;
Tests: T1 T2 T3
17455
17456 1/1 assign classc_ctrl_shadowed_en_wd = reg_wdata[0];
Tests: T1 T2 T3
17457
17458 1/1 assign classc_ctrl_shadowed_lock_wd = reg_wdata[1];
Tests: T1 T2 T3
17459
17460 1/1 assign classc_ctrl_shadowed_en_e0_wd = reg_wdata[2];
Tests: T1 T2 T3
17461
17462 1/1 assign classc_ctrl_shadowed_en_e1_wd = reg_wdata[3];
Tests: T1 T2 T3
17463
17464 1/1 assign classc_ctrl_shadowed_en_e2_wd = reg_wdata[4];
Tests: T1 T2 T3
17465
17466 1/1 assign classc_ctrl_shadowed_en_e3_wd = reg_wdata[5];
Tests: T1 T2 T3
17467
17468 1/1 assign classc_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
Tests: T1 T2 T3
17469
17470 1/1 assign classc_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
Tests: T1 T2 T3
17471
17472 1/1 assign classc_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
Tests: T1 T2 T3
17473
17474 1/1 assign classc_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
Tests: T1 T2 T3
17475 1/1 assign classc_clr_regwen_we = addr_hit[324] & reg_we & !reg_error;
Tests: T1 T2 T3
17476
17477 1/1 assign classc_clr_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17478 1/1 assign classc_clr_shadowed_re = addr_hit[325] & reg_re & !reg_error;
Tests: T1 T2 T3
17479 1/1 assign classc_clr_shadowed_we = addr_hit[325] & reg_we & !reg_error;
Tests: T1 T2 T3
17480
17481 1/1 assign classc_clr_shadowed_wd = reg_wdata[0];
Tests: T1 T2 T3
17482 1/1 assign classc_accum_cnt_re = addr_hit[326] & reg_re & !reg_error;
Tests: T1 T2 T3
17483 1/1 assign classc_accum_thresh_shadowed_re = addr_hit[327] & reg_re & !reg_error;
Tests: T1 T2 T3
17484 1/1 assign classc_accum_thresh_shadowed_we = addr_hit[327] & reg_we & !reg_error;
Tests: T1 T2 T3
17485
17486 1/1 assign classc_accum_thresh_shadowed_wd = reg_wdata[15:0];
Tests: T1 T2 T3
17487 1/1 assign classc_timeout_cyc_shadowed_re = addr_hit[328] & reg_re & !reg_error;
Tests: T1 T2 T3
17488 1/1 assign classc_timeout_cyc_shadowed_we = addr_hit[328] & reg_we & !reg_error;
Tests: T1 T2 T3
17489
17490 1/1 assign classc_timeout_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17491 1/1 assign classc_crashdump_trigger_shadowed_re = addr_hit[329] & reg_re & !reg_error;
Tests: T1 T2 T3
17492 1/1 assign classc_crashdump_trigger_shadowed_we = addr_hit[329] & reg_we & !reg_error;
Tests: T1 T2 T3
17493
17494 1/1 assign classc_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17495 1/1 assign classc_phase0_cyc_shadowed_re = addr_hit[330] & reg_re & !reg_error;
Tests: T1 T2 T3
17496 1/1 assign classc_phase0_cyc_shadowed_we = addr_hit[330] & reg_we & !reg_error;
Tests: T1 T2 T3
17497
17498 1/1 assign classc_phase0_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17499 1/1 assign classc_phase1_cyc_shadowed_re = addr_hit[331] & reg_re & !reg_error;
Tests: T1 T2 T3
17500 1/1 assign classc_phase1_cyc_shadowed_we = addr_hit[331] & reg_we & !reg_error;
Tests: T1 T2 T3
17501
17502 1/1 assign classc_phase1_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17503 1/1 assign classc_phase2_cyc_shadowed_re = addr_hit[332] & reg_re & !reg_error;
Tests: T1 T2 T3
17504 1/1 assign classc_phase2_cyc_shadowed_we = addr_hit[332] & reg_we & !reg_error;
Tests: T1 T2 T3
17505
17506 1/1 assign classc_phase2_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17507 1/1 assign classc_phase3_cyc_shadowed_re = addr_hit[333] & reg_re & !reg_error;
Tests: T1 T2 T3
17508 1/1 assign classc_phase3_cyc_shadowed_we = addr_hit[333] & reg_we & !reg_error;
Tests: T1 T2 T3
17509
17510 1/1 assign classc_phase3_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17511 1/1 assign classc_esc_cnt_re = addr_hit[334] & reg_re & !reg_error;
Tests: T1 T2 T3
17512 1/1 assign classc_state_re = addr_hit[335] & reg_re & !reg_error;
Tests: T1 T2 T3
17513 1/1 assign classd_regwen_we = addr_hit[336] & reg_we & !reg_error;
Tests: T1 T2 T3
17514
17515 1/1 assign classd_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17516 1/1 assign classd_ctrl_shadowed_re = addr_hit[337] & reg_re & !reg_error;
Tests: T1 T2 T3
17517 1/1 assign classd_ctrl_shadowed_we = addr_hit[337] & reg_we & !reg_error;
Tests: T1 T2 T3
17518
17519 1/1 assign classd_ctrl_shadowed_en_wd = reg_wdata[0];
Tests: T1 T2 T3
17520
17521 1/1 assign classd_ctrl_shadowed_lock_wd = reg_wdata[1];
Tests: T1 T2 T3
17522
17523 1/1 assign classd_ctrl_shadowed_en_e0_wd = reg_wdata[2];
Tests: T1 T2 T3
17524
17525 1/1 assign classd_ctrl_shadowed_en_e1_wd = reg_wdata[3];
Tests: T1 T2 T3
17526
17527 1/1 assign classd_ctrl_shadowed_en_e2_wd = reg_wdata[4];
Tests: T1 T2 T3
17528
17529 1/1 assign classd_ctrl_shadowed_en_e3_wd = reg_wdata[5];
Tests: T1 T2 T3
17530
17531 1/1 assign classd_ctrl_shadowed_map_e0_wd = reg_wdata[7:6];
Tests: T1 T2 T3
17532
17533 1/1 assign classd_ctrl_shadowed_map_e1_wd = reg_wdata[9:8];
Tests: T1 T2 T3
17534
17535 1/1 assign classd_ctrl_shadowed_map_e2_wd = reg_wdata[11:10];
Tests: T1 T2 T3
17536
17537 1/1 assign classd_ctrl_shadowed_map_e3_wd = reg_wdata[13:12];
Tests: T1 T2 T3
17538 1/1 assign classd_clr_regwen_we = addr_hit[338] & reg_we & !reg_error;
Tests: T1 T2 T3
17539
17540 1/1 assign classd_clr_regwen_wd = reg_wdata[0];
Tests: T1 T2 T3
17541 1/1 assign classd_clr_shadowed_re = addr_hit[339] & reg_re & !reg_error;
Tests: T1 T2 T3
17542 1/1 assign classd_clr_shadowed_we = addr_hit[339] & reg_we & !reg_error;
Tests: T1 T2 T3
17543
17544 1/1 assign classd_clr_shadowed_wd = reg_wdata[0];
Tests: T1 T2 T3
17545 1/1 assign classd_accum_cnt_re = addr_hit[340] & reg_re & !reg_error;
Tests: T1 T2 T3
17546 1/1 assign classd_accum_thresh_shadowed_re = addr_hit[341] & reg_re & !reg_error;
Tests: T1 T2 T3
17547 1/1 assign classd_accum_thresh_shadowed_we = addr_hit[341] & reg_we & !reg_error;
Tests: T1 T2 T3
17548
17549 1/1 assign classd_accum_thresh_shadowed_wd = reg_wdata[15:0];
Tests: T1 T2 T3
17550 1/1 assign classd_timeout_cyc_shadowed_re = addr_hit[342] & reg_re & !reg_error;
Tests: T1 T2 T3
17551 1/1 assign classd_timeout_cyc_shadowed_we = addr_hit[342] & reg_we & !reg_error;
Tests: T1 T2 T3
17552
17553 1/1 assign classd_timeout_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17554 1/1 assign classd_crashdump_trigger_shadowed_re = addr_hit[343] & reg_re & !reg_error;
Tests: T1 T2 T3
17555 1/1 assign classd_crashdump_trigger_shadowed_we = addr_hit[343] & reg_we & !reg_error;
Tests: T1 T2 T3
17556
17557 1/1 assign classd_crashdump_trigger_shadowed_wd = reg_wdata[1:0];
Tests: T1 T2 T3
17558 1/1 assign classd_phase0_cyc_shadowed_re = addr_hit[344] & reg_re & !reg_error;
Tests: T1 T2 T3
17559 1/1 assign classd_phase0_cyc_shadowed_we = addr_hit[344] & reg_we & !reg_error;
Tests: T1 T2 T3
17560
17561 1/1 assign classd_phase0_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17562 1/1 assign classd_phase1_cyc_shadowed_re = addr_hit[345] & reg_re & !reg_error;
Tests: T1 T2 T3
17563 1/1 assign classd_phase1_cyc_shadowed_we = addr_hit[345] & reg_we & !reg_error;
Tests: T1 T2 T3
17564
17565 1/1 assign classd_phase1_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17566 1/1 assign classd_phase2_cyc_shadowed_re = addr_hit[346] & reg_re & !reg_error;
Tests: T1 T2 T3
17567 1/1 assign classd_phase2_cyc_shadowed_we = addr_hit[346] & reg_we & !reg_error;
Tests: T1 T2 T3
17568
17569 1/1 assign classd_phase2_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17570 1/1 assign classd_phase3_cyc_shadowed_re = addr_hit[347] & reg_re & !reg_error;
Tests: T1 T2 T3
17571 1/1 assign classd_phase3_cyc_shadowed_we = addr_hit[347] & reg_we & !reg_error;
Tests: T1 T2 T3
17572
17573 1/1 assign classd_phase3_cyc_shadowed_wd = reg_wdata[31:0];
Tests: T1 T2 T3
17574 1/1 assign classd_esc_cnt_re = addr_hit[348] & reg_re & !reg_error;
Tests: T1 T2 T3
17575 1/1 assign classd_state_re = addr_hit[349] & reg_re & !reg_error;
Tests: T1 T2 T3
17576
17577 // Assign write-enables to checker logic vector.
17578 always_comb begin
17579 1/1 reg_we_check = '0;
Tests: T1 T2 T3
17580 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
17581 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
17582 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
17583 1/1 reg_we_check[3] = ping_timer_regwen_we;
Tests: T1 T2 T3
17584 1/1 reg_we_check[4] = ping_timeout_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17585 1/1 reg_we_check[5] = ping_timer_en_shadowed_gated_we;
Tests: T1 T2 T3
17586 1/1 reg_we_check[6] = alert_regwen_0_we;
Tests: T1 T2 T3
17587 1/1 reg_we_check[7] = alert_regwen_1_we;
Tests: T1 T2 T3
17588 1/1 reg_we_check[8] = alert_regwen_2_we;
Tests: T1 T2 T3
17589 1/1 reg_we_check[9] = alert_regwen_3_we;
Tests: T1 T2 T3
17590 1/1 reg_we_check[10] = alert_regwen_4_we;
Tests: T1 T2 T3
17591 1/1 reg_we_check[11] = alert_regwen_5_we;
Tests: T1 T2 T3
17592 1/1 reg_we_check[12] = alert_regwen_6_we;
Tests: T1 T2 T3
17593 1/1 reg_we_check[13] = alert_regwen_7_we;
Tests: T1 T2 T3
17594 1/1 reg_we_check[14] = alert_regwen_8_we;
Tests: T1 T2 T3
17595 1/1 reg_we_check[15] = alert_regwen_9_we;
Tests: T1 T2 T3
17596 1/1 reg_we_check[16] = alert_regwen_10_we;
Tests: T1 T2 T3
17597 1/1 reg_we_check[17] = alert_regwen_11_we;
Tests: T1 T2 T3
17598 1/1 reg_we_check[18] = alert_regwen_12_we;
Tests: T1 T2 T3
17599 1/1 reg_we_check[19] = alert_regwen_13_we;
Tests: T1 T2 T3
17600 1/1 reg_we_check[20] = alert_regwen_14_we;
Tests: T1 T2 T3
17601 1/1 reg_we_check[21] = alert_regwen_15_we;
Tests: T1 T2 T3
17602 1/1 reg_we_check[22] = alert_regwen_16_we;
Tests: T1 T2 T3
17603 1/1 reg_we_check[23] = alert_regwen_17_we;
Tests: T1 T2 T3
17604 1/1 reg_we_check[24] = alert_regwen_18_we;
Tests: T1 T2 T3
17605 1/1 reg_we_check[25] = alert_regwen_19_we;
Tests: T1 T2 T3
17606 1/1 reg_we_check[26] = alert_regwen_20_we;
Tests: T1 T2 T3
17607 1/1 reg_we_check[27] = alert_regwen_21_we;
Tests: T1 T2 T3
17608 1/1 reg_we_check[28] = alert_regwen_22_we;
Tests: T1 T2 T3
17609 1/1 reg_we_check[29] = alert_regwen_23_we;
Tests: T1 T2 T3
17610 1/1 reg_we_check[30] = alert_regwen_24_we;
Tests: T1 T2 T3
17611 1/1 reg_we_check[31] = alert_regwen_25_we;
Tests: T1 T2 T3
17612 1/1 reg_we_check[32] = alert_regwen_26_we;
Tests: T1 T2 T3
17613 1/1 reg_we_check[33] = alert_regwen_27_we;
Tests: T1 T2 T3
17614 1/1 reg_we_check[34] = alert_regwen_28_we;
Tests: T1 T2 T3
17615 1/1 reg_we_check[35] = alert_regwen_29_we;
Tests: T1 T2 T3
17616 1/1 reg_we_check[36] = alert_regwen_30_we;
Tests: T1 T2 T3
17617 1/1 reg_we_check[37] = alert_regwen_31_we;
Tests: T1 T2 T3
17618 1/1 reg_we_check[38] = alert_regwen_32_we;
Tests: T1 T2 T3
17619 1/1 reg_we_check[39] = alert_regwen_33_we;
Tests: T1 T2 T3
17620 1/1 reg_we_check[40] = alert_regwen_34_we;
Tests: T1 T2 T3
17621 1/1 reg_we_check[41] = alert_regwen_35_we;
Tests: T1 T2 T3
17622 1/1 reg_we_check[42] = alert_regwen_36_we;
Tests: T1 T2 T3
17623 1/1 reg_we_check[43] = alert_regwen_37_we;
Tests: T1 T2 T3
17624 1/1 reg_we_check[44] = alert_regwen_38_we;
Tests: T1 T2 T3
17625 1/1 reg_we_check[45] = alert_regwen_39_we;
Tests: T1 T2 T3
17626 1/1 reg_we_check[46] = alert_regwen_40_we;
Tests: T1 T2 T3
17627 1/1 reg_we_check[47] = alert_regwen_41_we;
Tests: T1 T2 T3
17628 1/1 reg_we_check[48] = alert_regwen_42_we;
Tests: T1 T2 T3
17629 1/1 reg_we_check[49] = alert_regwen_43_we;
Tests: T1 T2 T3
17630 1/1 reg_we_check[50] = alert_regwen_44_we;
Tests: T1 T2 T3
17631 1/1 reg_we_check[51] = alert_regwen_45_we;
Tests: T1 T2 T3
17632 1/1 reg_we_check[52] = alert_regwen_46_we;
Tests: T1 T2 T3
17633 1/1 reg_we_check[53] = alert_regwen_47_we;
Tests: T1 T2 T3
17634 1/1 reg_we_check[54] = alert_regwen_48_we;
Tests: T1 T2 T3
17635 1/1 reg_we_check[55] = alert_regwen_49_we;
Tests: T1 T2 T3
17636 1/1 reg_we_check[56] = alert_regwen_50_we;
Tests: T1 T2 T3
17637 1/1 reg_we_check[57] = alert_regwen_51_we;
Tests: T1 T2 T3
17638 1/1 reg_we_check[58] = alert_regwen_52_we;
Tests: T1 T2 T3
17639 1/1 reg_we_check[59] = alert_regwen_53_we;
Tests: T1 T2 T3
17640 1/1 reg_we_check[60] = alert_regwen_54_we;
Tests: T1 T2 T3
17641 1/1 reg_we_check[61] = alert_regwen_55_we;
Tests: T1 T2 T3
17642 1/1 reg_we_check[62] = alert_regwen_56_we;
Tests: T1 T2 T3
17643 1/1 reg_we_check[63] = alert_regwen_57_we;
Tests: T1 T2 T3
17644 1/1 reg_we_check[64] = alert_regwen_58_we;
Tests: T1 T2 T3
17645 1/1 reg_we_check[65] = alert_regwen_59_we;
Tests: T1 T2 T3
17646 1/1 reg_we_check[66] = alert_regwen_60_we;
Tests: T1 T2 T3
17647 1/1 reg_we_check[67] = alert_regwen_61_we;
Tests: T1 T2 T3
17648 1/1 reg_we_check[68] = alert_regwen_62_we;
Tests: T1 T2 T3
17649 1/1 reg_we_check[69] = alert_regwen_63_we;
Tests: T1 T2 T3
17650 1/1 reg_we_check[70] = alert_regwen_64_we;
Tests: T1 T2 T3
17651 1/1 reg_we_check[71] = alert_en_shadowed_0_gated_we;
Tests: T1 T2 T3
17652 1/1 reg_we_check[72] = alert_en_shadowed_1_gated_we;
Tests: T1 T2 T3
17653 1/1 reg_we_check[73] = alert_en_shadowed_2_gated_we;
Tests: T1 T2 T3
17654 1/1 reg_we_check[74] = alert_en_shadowed_3_gated_we;
Tests: T1 T2 T3
17655 1/1 reg_we_check[75] = alert_en_shadowed_4_gated_we;
Tests: T1 T2 T3
17656 1/1 reg_we_check[76] = alert_en_shadowed_5_gated_we;
Tests: T1 T2 T3
17657 1/1 reg_we_check[77] = alert_en_shadowed_6_gated_we;
Tests: T1 T2 T3
17658 1/1 reg_we_check[78] = alert_en_shadowed_7_gated_we;
Tests: T1 T2 T3
17659 1/1 reg_we_check[79] = alert_en_shadowed_8_gated_we;
Tests: T1 T2 T3
17660 1/1 reg_we_check[80] = alert_en_shadowed_9_gated_we;
Tests: T1 T2 T3
17661 1/1 reg_we_check[81] = alert_en_shadowed_10_gated_we;
Tests: T1 T2 T3
17662 1/1 reg_we_check[82] = alert_en_shadowed_11_gated_we;
Tests: T1 T2 T3
17663 1/1 reg_we_check[83] = alert_en_shadowed_12_gated_we;
Tests: T1 T2 T3
17664 1/1 reg_we_check[84] = alert_en_shadowed_13_gated_we;
Tests: T1 T2 T3
17665 1/1 reg_we_check[85] = alert_en_shadowed_14_gated_we;
Tests: T1 T2 T3
17666 1/1 reg_we_check[86] = alert_en_shadowed_15_gated_we;
Tests: T1 T2 T3
17667 1/1 reg_we_check[87] = alert_en_shadowed_16_gated_we;
Tests: T1 T2 T3
17668 1/1 reg_we_check[88] = alert_en_shadowed_17_gated_we;
Tests: T1 T2 T3
17669 1/1 reg_we_check[89] = alert_en_shadowed_18_gated_we;
Tests: T1 T2 T3
17670 1/1 reg_we_check[90] = alert_en_shadowed_19_gated_we;
Tests: T1 T2 T3
17671 1/1 reg_we_check[91] = alert_en_shadowed_20_gated_we;
Tests: T1 T2 T3
17672 1/1 reg_we_check[92] = alert_en_shadowed_21_gated_we;
Tests: T1 T2 T3
17673 1/1 reg_we_check[93] = alert_en_shadowed_22_gated_we;
Tests: T1 T2 T3
17674 1/1 reg_we_check[94] = alert_en_shadowed_23_gated_we;
Tests: T1 T2 T3
17675 1/1 reg_we_check[95] = alert_en_shadowed_24_gated_we;
Tests: T1 T2 T3
17676 1/1 reg_we_check[96] = alert_en_shadowed_25_gated_we;
Tests: T1 T2 T3
17677 1/1 reg_we_check[97] = alert_en_shadowed_26_gated_we;
Tests: T1 T2 T3
17678 1/1 reg_we_check[98] = alert_en_shadowed_27_gated_we;
Tests: T1 T2 T3
17679 1/1 reg_we_check[99] = alert_en_shadowed_28_gated_we;
Tests: T1 T2 T3
17680 1/1 reg_we_check[100] = alert_en_shadowed_29_gated_we;
Tests: T1 T2 T3
17681 1/1 reg_we_check[101] = alert_en_shadowed_30_gated_we;
Tests: T1 T2 T3
17682 1/1 reg_we_check[102] = alert_en_shadowed_31_gated_we;
Tests: T1 T2 T3
17683 1/1 reg_we_check[103] = alert_en_shadowed_32_gated_we;
Tests: T1 T2 T3
17684 1/1 reg_we_check[104] = alert_en_shadowed_33_gated_we;
Tests: T1 T2 T3
17685 1/1 reg_we_check[105] = alert_en_shadowed_34_gated_we;
Tests: T1 T2 T3
17686 1/1 reg_we_check[106] = alert_en_shadowed_35_gated_we;
Tests: T1 T2 T3
17687 1/1 reg_we_check[107] = alert_en_shadowed_36_gated_we;
Tests: T1 T2 T3
17688 1/1 reg_we_check[108] = alert_en_shadowed_37_gated_we;
Tests: T1 T2 T3
17689 1/1 reg_we_check[109] = alert_en_shadowed_38_gated_we;
Tests: T1 T2 T3
17690 1/1 reg_we_check[110] = alert_en_shadowed_39_gated_we;
Tests: T1 T2 T3
17691 1/1 reg_we_check[111] = alert_en_shadowed_40_gated_we;
Tests: T1 T2 T3
17692 1/1 reg_we_check[112] = alert_en_shadowed_41_gated_we;
Tests: T1 T2 T3
17693 1/1 reg_we_check[113] = alert_en_shadowed_42_gated_we;
Tests: T1 T2 T3
17694 1/1 reg_we_check[114] = alert_en_shadowed_43_gated_we;
Tests: T1 T2 T3
17695 1/1 reg_we_check[115] = alert_en_shadowed_44_gated_we;
Tests: T1 T2 T3
17696 1/1 reg_we_check[116] = alert_en_shadowed_45_gated_we;
Tests: T1 T2 T3
17697 1/1 reg_we_check[117] = alert_en_shadowed_46_gated_we;
Tests: T1 T2 T3
17698 1/1 reg_we_check[118] = alert_en_shadowed_47_gated_we;
Tests: T1 T2 T3
17699 1/1 reg_we_check[119] = alert_en_shadowed_48_gated_we;
Tests: T1 T2 T3
17700 1/1 reg_we_check[120] = alert_en_shadowed_49_gated_we;
Tests: T1 T2 T3
17701 1/1 reg_we_check[121] = alert_en_shadowed_50_gated_we;
Tests: T1 T2 T3
17702 1/1 reg_we_check[122] = alert_en_shadowed_51_gated_we;
Tests: T1 T2 T3
17703 1/1 reg_we_check[123] = alert_en_shadowed_52_gated_we;
Tests: T1 T2 T3
17704 1/1 reg_we_check[124] = alert_en_shadowed_53_gated_we;
Tests: T1 T2 T3
17705 1/1 reg_we_check[125] = alert_en_shadowed_54_gated_we;
Tests: T1 T2 T3
17706 1/1 reg_we_check[126] = alert_en_shadowed_55_gated_we;
Tests: T1 T2 T3
17707 1/1 reg_we_check[127] = alert_en_shadowed_56_gated_we;
Tests: T1 T2 T3
17708 1/1 reg_we_check[128] = alert_en_shadowed_57_gated_we;
Tests: T1 T2 T3
17709 1/1 reg_we_check[129] = alert_en_shadowed_58_gated_we;
Tests: T1 T2 T3
17710 1/1 reg_we_check[130] = alert_en_shadowed_59_gated_we;
Tests: T1 T2 T3
17711 1/1 reg_we_check[131] = alert_en_shadowed_60_gated_we;
Tests: T1 T2 T3
17712 1/1 reg_we_check[132] = alert_en_shadowed_61_gated_we;
Tests: T1 T2 T3
17713 1/1 reg_we_check[133] = alert_en_shadowed_62_gated_we;
Tests: T1 T2 T3
17714 1/1 reg_we_check[134] = alert_en_shadowed_63_gated_we;
Tests: T1 T2 T3
17715 1/1 reg_we_check[135] = alert_en_shadowed_64_gated_we;
Tests: T1 T2 T3
17716 1/1 reg_we_check[136] = alert_class_shadowed_0_gated_we;
Tests: T1 T2 T3
17717 1/1 reg_we_check[137] = alert_class_shadowed_1_gated_we;
Tests: T1 T2 T3
17718 1/1 reg_we_check[138] = alert_class_shadowed_2_gated_we;
Tests: T1 T2 T3
17719 1/1 reg_we_check[139] = alert_class_shadowed_3_gated_we;
Tests: T1 T2 T3
17720 1/1 reg_we_check[140] = alert_class_shadowed_4_gated_we;
Tests: T1 T2 T3
17721 1/1 reg_we_check[141] = alert_class_shadowed_5_gated_we;
Tests: T1 T2 T3
17722 1/1 reg_we_check[142] = alert_class_shadowed_6_gated_we;
Tests: T1 T2 T3
17723 1/1 reg_we_check[143] = alert_class_shadowed_7_gated_we;
Tests: T1 T2 T3
17724 1/1 reg_we_check[144] = alert_class_shadowed_8_gated_we;
Tests: T1 T2 T3
17725 1/1 reg_we_check[145] = alert_class_shadowed_9_gated_we;
Tests: T1 T2 T3
17726 1/1 reg_we_check[146] = alert_class_shadowed_10_gated_we;
Tests: T1 T2 T3
17727 1/1 reg_we_check[147] = alert_class_shadowed_11_gated_we;
Tests: T1 T2 T3
17728 1/1 reg_we_check[148] = alert_class_shadowed_12_gated_we;
Tests: T1 T2 T3
17729 1/1 reg_we_check[149] = alert_class_shadowed_13_gated_we;
Tests: T1 T2 T3
17730 1/1 reg_we_check[150] = alert_class_shadowed_14_gated_we;
Tests: T1 T2 T3
17731 1/1 reg_we_check[151] = alert_class_shadowed_15_gated_we;
Tests: T1 T2 T3
17732 1/1 reg_we_check[152] = alert_class_shadowed_16_gated_we;
Tests: T1 T2 T3
17733 1/1 reg_we_check[153] = alert_class_shadowed_17_gated_we;
Tests: T1 T2 T3
17734 1/1 reg_we_check[154] = alert_class_shadowed_18_gated_we;
Tests: T1 T2 T3
17735 1/1 reg_we_check[155] = alert_class_shadowed_19_gated_we;
Tests: T1 T2 T3
17736 1/1 reg_we_check[156] = alert_class_shadowed_20_gated_we;
Tests: T1 T2 T3
17737 1/1 reg_we_check[157] = alert_class_shadowed_21_gated_we;
Tests: T1 T2 T3
17738 1/1 reg_we_check[158] = alert_class_shadowed_22_gated_we;
Tests: T1 T2 T3
17739 1/1 reg_we_check[159] = alert_class_shadowed_23_gated_we;
Tests: T1 T2 T3
17740 1/1 reg_we_check[160] = alert_class_shadowed_24_gated_we;
Tests: T1 T2 T3
17741 1/1 reg_we_check[161] = alert_class_shadowed_25_gated_we;
Tests: T1 T2 T3
17742 1/1 reg_we_check[162] = alert_class_shadowed_26_gated_we;
Tests: T1 T2 T3
17743 1/1 reg_we_check[163] = alert_class_shadowed_27_gated_we;
Tests: T1 T2 T3
17744 1/1 reg_we_check[164] = alert_class_shadowed_28_gated_we;
Tests: T1 T2 T3
17745 1/1 reg_we_check[165] = alert_class_shadowed_29_gated_we;
Tests: T1 T2 T3
17746 1/1 reg_we_check[166] = alert_class_shadowed_30_gated_we;
Tests: T1 T2 T3
17747 1/1 reg_we_check[167] = alert_class_shadowed_31_gated_we;
Tests: T1 T2 T3
17748 1/1 reg_we_check[168] = alert_class_shadowed_32_gated_we;
Tests: T1 T2 T3
17749 1/1 reg_we_check[169] = alert_class_shadowed_33_gated_we;
Tests: T1 T2 T3
17750 1/1 reg_we_check[170] = alert_class_shadowed_34_gated_we;
Tests: T1 T2 T3
17751 1/1 reg_we_check[171] = alert_class_shadowed_35_gated_we;
Tests: T1 T2 T3
17752 1/1 reg_we_check[172] = alert_class_shadowed_36_gated_we;
Tests: T1 T2 T3
17753 1/1 reg_we_check[173] = alert_class_shadowed_37_gated_we;
Tests: T1 T2 T3
17754 1/1 reg_we_check[174] = alert_class_shadowed_38_gated_we;
Tests: T1 T2 T3
17755 1/1 reg_we_check[175] = alert_class_shadowed_39_gated_we;
Tests: T1 T2 T3
17756 1/1 reg_we_check[176] = alert_class_shadowed_40_gated_we;
Tests: T1 T2 T3
17757 1/1 reg_we_check[177] = alert_class_shadowed_41_gated_we;
Tests: T1 T2 T3
17758 1/1 reg_we_check[178] = alert_class_shadowed_42_gated_we;
Tests: T1 T2 T3
17759 1/1 reg_we_check[179] = alert_class_shadowed_43_gated_we;
Tests: T1 T2 T3
17760 1/1 reg_we_check[180] = alert_class_shadowed_44_gated_we;
Tests: T1 T2 T3
17761 1/1 reg_we_check[181] = alert_class_shadowed_45_gated_we;
Tests: T1 T2 T3
17762 1/1 reg_we_check[182] = alert_class_shadowed_46_gated_we;
Tests: T1 T2 T3
17763 1/1 reg_we_check[183] = alert_class_shadowed_47_gated_we;
Tests: T1 T2 T3
17764 1/1 reg_we_check[184] = alert_class_shadowed_48_gated_we;
Tests: T1 T2 T3
17765 1/1 reg_we_check[185] = alert_class_shadowed_49_gated_we;
Tests: T1 T2 T3
17766 1/1 reg_we_check[186] = alert_class_shadowed_50_gated_we;
Tests: T1 T2 T3
17767 1/1 reg_we_check[187] = alert_class_shadowed_51_gated_we;
Tests: T1 T2 T3
17768 1/1 reg_we_check[188] = alert_class_shadowed_52_gated_we;
Tests: T1 T2 T3
17769 1/1 reg_we_check[189] = alert_class_shadowed_53_gated_we;
Tests: T1 T2 T3
17770 1/1 reg_we_check[190] = alert_class_shadowed_54_gated_we;
Tests: T1 T2 T3
17771 1/1 reg_we_check[191] = alert_class_shadowed_55_gated_we;
Tests: T1 T2 T3
17772 1/1 reg_we_check[192] = alert_class_shadowed_56_gated_we;
Tests: T1 T2 T3
17773 1/1 reg_we_check[193] = alert_class_shadowed_57_gated_we;
Tests: T1 T2 T3
17774 1/1 reg_we_check[194] = alert_class_shadowed_58_gated_we;
Tests: T1 T2 T3
17775 1/1 reg_we_check[195] = alert_class_shadowed_59_gated_we;
Tests: T1 T2 T3
17776 1/1 reg_we_check[196] = alert_class_shadowed_60_gated_we;
Tests: T1 T2 T3
17777 1/1 reg_we_check[197] = alert_class_shadowed_61_gated_we;
Tests: T1 T2 T3
17778 1/1 reg_we_check[198] = alert_class_shadowed_62_gated_we;
Tests: T1 T2 T3
17779 1/1 reg_we_check[199] = alert_class_shadowed_63_gated_we;
Tests: T1 T2 T3
17780 1/1 reg_we_check[200] = alert_class_shadowed_64_gated_we;
Tests: T1 T2 T3
17781 1/1 reg_we_check[201] = alert_cause_0_we;
Tests: T1 T2 T3
17782 1/1 reg_we_check[202] = alert_cause_1_we;
Tests: T1 T2 T3
17783 1/1 reg_we_check[203] = alert_cause_2_we;
Tests: T1 T2 T3
17784 1/1 reg_we_check[204] = alert_cause_3_we;
Tests: T1 T2 T3
17785 1/1 reg_we_check[205] = alert_cause_4_we;
Tests: T1 T2 T3
17786 1/1 reg_we_check[206] = alert_cause_5_we;
Tests: T1 T2 T3
17787 1/1 reg_we_check[207] = alert_cause_6_we;
Tests: T1 T2 T3
17788 1/1 reg_we_check[208] = alert_cause_7_we;
Tests: T1 T2 T3
17789 1/1 reg_we_check[209] = alert_cause_8_we;
Tests: T1 T2 T3
17790 1/1 reg_we_check[210] = alert_cause_9_we;
Tests: T1 T2 T3
17791 1/1 reg_we_check[211] = alert_cause_10_we;
Tests: T1 T2 T3
17792 1/1 reg_we_check[212] = alert_cause_11_we;
Tests: T1 T2 T3
17793 1/1 reg_we_check[213] = alert_cause_12_we;
Tests: T1 T2 T3
17794 1/1 reg_we_check[214] = alert_cause_13_we;
Tests: T1 T2 T3
17795 1/1 reg_we_check[215] = alert_cause_14_we;
Tests: T1 T2 T3
17796 1/1 reg_we_check[216] = alert_cause_15_we;
Tests: T1 T2 T3
17797 1/1 reg_we_check[217] = alert_cause_16_we;
Tests: T1 T2 T3
17798 1/1 reg_we_check[218] = alert_cause_17_we;
Tests: T1 T2 T3
17799 1/1 reg_we_check[219] = alert_cause_18_we;
Tests: T1 T2 T3
17800 1/1 reg_we_check[220] = alert_cause_19_we;
Tests: T1 T2 T3
17801 1/1 reg_we_check[221] = alert_cause_20_we;
Tests: T1 T2 T3
17802 1/1 reg_we_check[222] = alert_cause_21_we;
Tests: T1 T2 T3
17803 1/1 reg_we_check[223] = alert_cause_22_we;
Tests: T1 T2 T3
17804 1/1 reg_we_check[224] = alert_cause_23_we;
Tests: T1 T2 T3
17805 1/1 reg_we_check[225] = alert_cause_24_we;
Tests: T1 T2 T3
17806 1/1 reg_we_check[226] = alert_cause_25_we;
Tests: T1 T2 T3
17807 1/1 reg_we_check[227] = alert_cause_26_we;
Tests: T1 T2 T3
17808 1/1 reg_we_check[228] = alert_cause_27_we;
Tests: T1 T2 T3
17809 1/1 reg_we_check[229] = alert_cause_28_we;
Tests: T1 T2 T3
17810 1/1 reg_we_check[230] = alert_cause_29_we;
Tests: T1 T2 T3
17811 1/1 reg_we_check[231] = alert_cause_30_we;
Tests: T1 T2 T3
17812 1/1 reg_we_check[232] = alert_cause_31_we;
Tests: T1 T2 T3
17813 1/1 reg_we_check[233] = alert_cause_32_we;
Tests: T1 T2 T3
17814 1/1 reg_we_check[234] = alert_cause_33_we;
Tests: T1 T2 T3
17815 1/1 reg_we_check[235] = alert_cause_34_we;
Tests: T1 T2 T3
17816 1/1 reg_we_check[236] = alert_cause_35_we;
Tests: T1 T2 T3
17817 1/1 reg_we_check[237] = alert_cause_36_we;
Tests: T1 T2 T3
17818 1/1 reg_we_check[238] = alert_cause_37_we;
Tests: T1 T2 T3
17819 1/1 reg_we_check[239] = alert_cause_38_we;
Tests: T1 T2 T3
17820 1/1 reg_we_check[240] = alert_cause_39_we;
Tests: T1 T2 T3
17821 1/1 reg_we_check[241] = alert_cause_40_we;
Tests: T1 T2 T3
17822 1/1 reg_we_check[242] = alert_cause_41_we;
Tests: T1 T2 T3
17823 1/1 reg_we_check[243] = alert_cause_42_we;
Tests: T1 T2 T3
17824 1/1 reg_we_check[244] = alert_cause_43_we;
Tests: T1 T2 T3
17825 1/1 reg_we_check[245] = alert_cause_44_we;
Tests: T1 T2 T3
17826 1/1 reg_we_check[246] = alert_cause_45_we;
Tests: T1 T2 T3
17827 1/1 reg_we_check[247] = alert_cause_46_we;
Tests: T1 T2 T3
17828 1/1 reg_we_check[248] = alert_cause_47_we;
Tests: T1 T2 T3
17829 1/1 reg_we_check[249] = alert_cause_48_we;
Tests: T1 T2 T3
17830 1/1 reg_we_check[250] = alert_cause_49_we;
Tests: T1 T2 T3
17831 1/1 reg_we_check[251] = alert_cause_50_we;
Tests: T1 T2 T3
17832 1/1 reg_we_check[252] = alert_cause_51_we;
Tests: T1 T2 T3
17833 1/1 reg_we_check[253] = alert_cause_52_we;
Tests: T1 T2 T3
17834 1/1 reg_we_check[254] = alert_cause_53_we;
Tests: T1 T2 T3
17835 1/1 reg_we_check[255] = alert_cause_54_we;
Tests: T1 T2 T3
17836 1/1 reg_we_check[256] = alert_cause_55_we;
Tests: T1 T2 T3
17837 1/1 reg_we_check[257] = alert_cause_56_we;
Tests: T1 T2 T3
17838 1/1 reg_we_check[258] = alert_cause_57_we;
Tests: T1 T2 T3
17839 1/1 reg_we_check[259] = alert_cause_58_we;
Tests: T1 T2 T3
17840 1/1 reg_we_check[260] = alert_cause_59_we;
Tests: T1 T2 T3
17841 1/1 reg_we_check[261] = alert_cause_60_we;
Tests: T1 T2 T3
17842 1/1 reg_we_check[262] = alert_cause_61_we;
Tests: T1 T2 T3
17843 1/1 reg_we_check[263] = alert_cause_62_we;
Tests: T1 T2 T3
17844 1/1 reg_we_check[264] = alert_cause_63_we;
Tests: T1 T2 T3
17845 1/1 reg_we_check[265] = alert_cause_64_we;
Tests: T1 T2 T3
17846 1/1 reg_we_check[266] = loc_alert_regwen_0_we;
Tests: T1 T2 T3
17847 1/1 reg_we_check[267] = loc_alert_regwen_1_we;
Tests: T1 T2 T3
17848 1/1 reg_we_check[268] = loc_alert_regwen_2_we;
Tests: T1 T2 T3
17849 1/1 reg_we_check[269] = loc_alert_regwen_3_we;
Tests: T1 T2 T3
17850 1/1 reg_we_check[270] = loc_alert_regwen_4_we;
Tests: T1 T2 T3
17851 1/1 reg_we_check[271] = loc_alert_regwen_5_we;
Tests: T1 T2 T3
17852 1/1 reg_we_check[272] = loc_alert_regwen_6_we;
Tests: T1 T2 T3
17853 1/1 reg_we_check[273] = loc_alert_en_shadowed_0_gated_we;
Tests: T1 T2 T3
17854 1/1 reg_we_check[274] = loc_alert_en_shadowed_1_gated_we;
Tests: T1 T2 T3
17855 1/1 reg_we_check[275] = loc_alert_en_shadowed_2_gated_we;
Tests: T1 T2 T3
17856 1/1 reg_we_check[276] = loc_alert_en_shadowed_3_gated_we;
Tests: T1 T2 T3
17857 1/1 reg_we_check[277] = loc_alert_en_shadowed_4_gated_we;
Tests: T1 T2 T3
17858 1/1 reg_we_check[278] = loc_alert_en_shadowed_5_gated_we;
Tests: T1 T2 T3
17859 1/1 reg_we_check[279] = loc_alert_en_shadowed_6_gated_we;
Tests: T1 T2 T3
17860 1/1 reg_we_check[280] = loc_alert_class_shadowed_0_gated_we;
Tests: T1 T2 T3
17861 1/1 reg_we_check[281] = loc_alert_class_shadowed_1_gated_we;
Tests: T1 T2 T3
17862 1/1 reg_we_check[282] = loc_alert_class_shadowed_2_gated_we;
Tests: T1 T2 T3
17863 1/1 reg_we_check[283] = loc_alert_class_shadowed_3_gated_we;
Tests: T1 T2 T3
17864 1/1 reg_we_check[284] = loc_alert_class_shadowed_4_gated_we;
Tests: T1 T2 T3
17865 1/1 reg_we_check[285] = loc_alert_class_shadowed_5_gated_we;
Tests: T1 T2 T3
17866 1/1 reg_we_check[286] = loc_alert_class_shadowed_6_gated_we;
Tests: T1 T2 T3
17867 1/1 reg_we_check[287] = loc_alert_cause_0_we;
Tests: T1 T2 T3
17868 1/1 reg_we_check[288] = loc_alert_cause_1_we;
Tests: T1 T2 T3
17869 1/1 reg_we_check[289] = loc_alert_cause_2_we;
Tests: T1 T2 T3
17870 1/1 reg_we_check[290] = loc_alert_cause_3_we;
Tests: T1 T2 T3
17871 1/1 reg_we_check[291] = loc_alert_cause_4_we;
Tests: T1 T2 T3
17872 1/1 reg_we_check[292] = loc_alert_cause_5_we;
Tests: T1 T2 T3
17873 1/1 reg_we_check[293] = loc_alert_cause_6_we;
Tests: T1 T2 T3
17874 1/1 reg_we_check[294] = classa_regwen_we;
Tests: T1 T2 T3
17875 1/1 reg_we_check[295] = classa_ctrl_shadowed_gated_we;
Tests: T1 T2 T3
17876 1/1 reg_we_check[296] = classa_clr_regwen_we;
Tests: T1 T2 T3
17877 1/1 reg_we_check[297] = classa_clr_shadowed_gated_we;
Tests: T1 T2 T3
17878 1/1 reg_we_check[298] = 1'b0;
Tests: T1 T2 T3
17879 1/1 reg_we_check[299] = classa_accum_thresh_shadowed_gated_we;
Tests: T1 T2 T3
17880 1/1 reg_we_check[300] = classa_timeout_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17881 1/1 reg_we_check[301] = classa_crashdump_trigger_shadowed_gated_we;
Tests: T1 T2 T3
17882 1/1 reg_we_check[302] = classa_phase0_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17883 1/1 reg_we_check[303] = classa_phase1_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17884 1/1 reg_we_check[304] = classa_phase2_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17885 1/1 reg_we_check[305] = classa_phase3_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17886 1/1 reg_we_check[306] = 1'b0;
Tests: T1 T2 T3
17887 1/1 reg_we_check[307] = 1'b0;
Tests: T1 T2 T3
17888 1/1 reg_we_check[308] = classb_regwen_we;
Tests: T1 T2 T3
17889 1/1 reg_we_check[309] = classb_ctrl_shadowed_gated_we;
Tests: T1 T2 T3
17890 1/1 reg_we_check[310] = classb_clr_regwen_we;
Tests: T1 T2 T3
17891 1/1 reg_we_check[311] = classb_clr_shadowed_gated_we;
Tests: T1 T2 T3
17892 1/1 reg_we_check[312] = 1'b0;
Tests: T1 T2 T3
17893 1/1 reg_we_check[313] = classb_accum_thresh_shadowed_gated_we;
Tests: T1 T2 T3
17894 1/1 reg_we_check[314] = classb_timeout_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17895 1/1 reg_we_check[315] = classb_crashdump_trigger_shadowed_gated_we;
Tests: T1 T2 T3
17896 1/1 reg_we_check[316] = classb_phase0_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17897 1/1 reg_we_check[317] = classb_phase1_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17898 1/1 reg_we_check[318] = classb_phase2_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17899 1/1 reg_we_check[319] = classb_phase3_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17900 1/1 reg_we_check[320] = 1'b0;
Tests: T1 T2 T3
17901 1/1 reg_we_check[321] = 1'b0;
Tests: T1 T2 T3
17902 1/1 reg_we_check[322] = classc_regwen_we;
Tests: T1 T2 T3
17903 1/1 reg_we_check[323] = classc_ctrl_shadowed_gated_we;
Tests: T1 T2 T3
17904 1/1 reg_we_check[324] = classc_clr_regwen_we;
Tests: T1 T2 T3
17905 1/1 reg_we_check[325] = classc_clr_shadowed_gated_we;
Tests: T1 T2 T3
17906 1/1 reg_we_check[326] = 1'b0;
Tests: T1 T2 T3
17907 1/1 reg_we_check[327] = classc_accum_thresh_shadowed_gated_we;
Tests: T1 T2 T3
17908 1/1 reg_we_check[328] = classc_timeout_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17909 1/1 reg_we_check[329] = classc_crashdump_trigger_shadowed_gated_we;
Tests: T1 T2 T3
17910 1/1 reg_we_check[330] = classc_phase0_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17911 1/1 reg_we_check[331] = classc_phase1_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17912 1/1 reg_we_check[332] = classc_phase2_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17913 1/1 reg_we_check[333] = classc_phase3_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17914 1/1 reg_we_check[334] = 1'b0;
Tests: T1 T2 T3
17915 1/1 reg_we_check[335] = 1'b0;
Tests: T1 T2 T3
17916 1/1 reg_we_check[336] = classd_regwen_we;
Tests: T1 T2 T3
17917 1/1 reg_we_check[337] = classd_ctrl_shadowed_gated_we;
Tests: T1 T2 T3
17918 1/1 reg_we_check[338] = classd_clr_regwen_we;
Tests: T1 T2 T3
17919 1/1 reg_we_check[339] = classd_clr_shadowed_gated_we;
Tests: T1 T2 T3
17920 1/1 reg_we_check[340] = 1'b0;
Tests: T1 T2 T3
17921 1/1 reg_we_check[341] = classd_accum_thresh_shadowed_gated_we;
Tests: T1 T2 T3
17922 1/1 reg_we_check[342] = classd_timeout_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17923 1/1 reg_we_check[343] = classd_crashdump_trigger_shadowed_gated_we;
Tests: T1 T2 T3
17924 1/1 reg_we_check[344] = classd_phase0_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17925 1/1 reg_we_check[345] = classd_phase1_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17926 1/1 reg_we_check[346] = classd_phase2_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17927 1/1 reg_we_check[347] = classd_phase3_cyc_shadowed_gated_we;
Tests: T1 T2 T3
17928 1/1 reg_we_check[348] = 1'b0;
Tests: T1 T2 T3
17929 1/1 reg_we_check[349] = 1'b0;
Tests: T1 T2 T3
17930 end
17931
17932 // Read data return
17933 always_comb begin
17934 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
17935 1/1 unique case (1'b1)
Tests: T1 T2 T3
17936 addr_hit[0]: begin
17937 1/1 reg_rdata_next[0] = intr_state_classa_qs;
Tests: T1 T2 T3
17938 1/1 reg_rdata_next[1] = intr_state_classb_qs;
Tests: T1 T2 T3
17939 1/1 reg_rdata_next[2] = intr_state_classc_qs;
Tests: T1 T2 T3
17940 1/1 reg_rdata_next[3] = intr_state_classd_qs;
Tests: T1 T2 T3
17941 end
17942
17943 addr_hit[1]: begin
17944 1/1 reg_rdata_next[0] = intr_enable_classa_qs;
Tests: T1 T2 T3
17945 1/1 reg_rdata_next[1] = intr_enable_classb_qs;
Tests: T1 T2 T3
17946 1/1 reg_rdata_next[2] = intr_enable_classc_qs;
Tests: T1 T2 T3
17947 1/1 reg_rdata_next[3] = intr_enable_classd_qs;
Tests: T1 T2 T3
17948 end
17949
17950 addr_hit[2]: begin
17951 1/1 reg_rdata_next[0] = '0;
Tests: T1 T2 T10
17952 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T10
17953 1/1 reg_rdata_next[2] = '0;
Tests: T1 T2 T10
17954 1/1 reg_rdata_next[3] = '0;
Tests: T1 T2 T10
17955 end
17956
17957 addr_hit[3]: begin
17958 1/1 reg_rdata_next[0] = ping_timer_regwen_qs;
Tests: T1 T2 T10
17959 end
17960
17961 addr_hit[4]: begin
17962 1/1 reg_rdata_next[15:0] = ping_timeout_cyc_shadowed_qs;
Tests: T1 T2 T3
17963 end
17964
17965 addr_hit[5]: begin
17966 1/1 reg_rdata_next[0] = ping_timer_en_shadowed_qs;
Tests: T1 T2 T3
17967 end
17968
17969 addr_hit[6]: begin
17970 1/1 reg_rdata_next[0] = alert_regwen_0_qs;
Tests: T1 T2 T10
17971 end
17972
17973 addr_hit[7]: begin
17974 1/1 reg_rdata_next[0] = alert_regwen_1_qs;
Tests: T1 T2 T3
17975 end
17976
17977 addr_hit[8]: begin
17978 1/1 reg_rdata_next[0] = alert_regwen_2_qs;
Tests: T1 T2 T10
17979 end
17980
17981 addr_hit[9]: begin
17982 1/1 reg_rdata_next[0] = alert_regwen_3_qs;
Tests: T1 T2 T10
17983 end
17984
17985 addr_hit[10]: begin
17986 1/1 reg_rdata_next[0] = alert_regwen_4_qs;
Tests: T1 T2 T3
17987 end
17988
17989 addr_hit[11]: begin
17990 1/1 reg_rdata_next[0] = alert_regwen_5_qs;
Tests: T1 T2 T3
17991 end
17992
17993 addr_hit[12]: begin
17994 1/1 reg_rdata_next[0] = alert_regwen_6_qs;
Tests: T1 T2 T3
17995 end
17996
17997 addr_hit[13]: begin
17998 1/1 reg_rdata_next[0] = alert_regwen_7_qs;
Tests: T1 T2 T10
17999 end
18000
18001 addr_hit[14]: begin
18002 1/1 reg_rdata_next[0] = alert_regwen_8_qs;
Tests: T1 T2 T3
18003 end
18004
18005 addr_hit[15]: begin
18006 1/1 reg_rdata_next[0] = alert_regwen_9_qs;
Tests: T1 T2 T10
18007 end
18008
18009 addr_hit[16]: begin
18010 1/1 reg_rdata_next[0] = alert_regwen_10_qs;
Tests: T1 T2 T3
18011 end
18012
18013 addr_hit[17]: begin
18014 1/1 reg_rdata_next[0] = alert_regwen_11_qs;
Tests: T1 T2 T3
18015 end
18016
18017 addr_hit[18]: begin
18018 1/1 reg_rdata_next[0] = alert_regwen_12_qs;
Tests: T1 T2 T3
18019 end
18020
18021 addr_hit[19]: begin
18022 1/1 reg_rdata_next[0] = alert_regwen_13_qs;
Tests: T1 T2 T10
18023 end
18024
18025 addr_hit[20]: begin
18026 1/1 reg_rdata_next[0] = alert_regwen_14_qs;
Tests: T1 T2 T3
18027 end
18028
18029 addr_hit[21]: begin
18030 1/1 reg_rdata_next[0] = alert_regwen_15_qs;
Tests: T1 T2 T10
18031 end
18032
18033 addr_hit[22]: begin
18034 1/1 reg_rdata_next[0] = alert_regwen_16_qs;
Tests: T1 T2 T10
18035 end
18036
18037 addr_hit[23]: begin
18038 1/1 reg_rdata_next[0] = alert_regwen_17_qs;
Tests: T1 T2 T3
18039 end
18040
18041 addr_hit[24]: begin
18042 1/1 reg_rdata_next[0] = alert_regwen_18_qs;
Tests: T1 T2 T3
18043 end
18044
18045 addr_hit[25]: begin
18046 1/1 reg_rdata_next[0] = alert_regwen_19_qs;
Tests: T1 T2 T3
18047 end
18048
18049 addr_hit[26]: begin
18050 1/1 reg_rdata_next[0] = alert_regwen_20_qs;
Tests: T1 T2 T3
18051 end
18052
18053 addr_hit[27]: begin
18054 1/1 reg_rdata_next[0] = alert_regwen_21_qs;
Tests: T1 T2 T3
18055 end
18056
18057 addr_hit[28]: begin
18058 1/1 reg_rdata_next[0] = alert_regwen_22_qs;
Tests: T1 T2 T10
18059 end
18060
18061 addr_hit[29]: begin
18062 1/1 reg_rdata_next[0] = alert_regwen_23_qs;
Tests: T1 T2 T10
18063 end
18064
18065 addr_hit[30]: begin
18066 1/1 reg_rdata_next[0] = alert_regwen_24_qs;
Tests: T1 T2 T3
18067 end
18068
18069 addr_hit[31]: begin
18070 1/1 reg_rdata_next[0] = alert_regwen_25_qs;
Tests: T1 T2 T3
18071 end
18072
18073 addr_hit[32]: begin
18074 1/1 reg_rdata_next[0] = alert_regwen_26_qs;
Tests: T1 T2 T10
18075 end
18076
18077 addr_hit[33]: begin
18078 1/1 reg_rdata_next[0] = alert_regwen_27_qs;
Tests: T1 T2 T3
18079 end
18080
18081 addr_hit[34]: begin
18082 1/1 reg_rdata_next[0] = alert_regwen_28_qs;
Tests: T1 T2 T10
18083 end
18084
18085 addr_hit[35]: begin
18086 1/1 reg_rdata_next[0] = alert_regwen_29_qs;
Tests: T1 T2 T3
18087 end
18088
18089 addr_hit[36]: begin
18090 1/1 reg_rdata_next[0] = alert_regwen_30_qs;
Tests: T1 T2 T10
18091 end
18092
18093 addr_hit[37]: begin
18094 1/1 reg_rdata_next[0] = alert_regwen_31_qs;
Tests: T1 T2 T3
18095 end
18096
18097 addr_hit[38]: begin
18098 1/1 reg_rdata_next[0] = alert_regwen_32_qs;
Tests: T1 T2 T10
18099 end
18100
18101 addr_hit[39]: begin
18102 1/1 reg_rdata_next[0] = alert_regwen_33_qs;
Tests: T1 T2 T10
18103 end
18104
18105 addr_hit[40]: begin
18106 1/1 reg_rdata_next[0] = alert_regwen_34_qs;
Tests: T1 T2 T10
18107 end
18108
18109 addr_hit[41]: begin
18110 1/1 reg_rdata_next[0] = alert_regwen_35_qs;
Tests: T1 T2 T10
18111 end
18112
18113 addr_hit[42]: begin
18114 1/1 reg_rdata_next[0] = alert_regwen_36_qs;
Tests: T1 T2 T3
18115 end
18116
18117 addr_hit[43]: begin
18118 1/1 reg_rdata_next[0] = alert_regwen_37_qs;
Tests: T1 T2 T10
18119 end
18120
18121 addr_hit[44]: begin
18122 1/1 reg_rdata_next[0] = alert_regwen_38_qs;
Tests: T1 T2 T10
18123 end
18124
18125 addr_hit[45]: begin
18126 1/1 reg_rdata_next[0] = alert_regwen_39_qs;
Tests: T1 T2 T3
18127 end
18128
18129 addr_hit[46]: begin
18130 1/1 reg_rdata_next[0] = alert_regwen_40_qs;
Tests: T1 T2 T10
18131 end
18132
18133 addr_hit[47]: begin
18134 1/1 reg_rdata_next[0] = alert_regwen_41_qs;
Tests: T1 T2 T10
18135 end
18136
18137 addr_hit[48]: begin
18138 1/1 reg_rdata_next[0] = alert_regwen_42_qs;
Tests: T1 T2 T10
18139 end
18140
18141 addr_hit[49]: begin
18142 1/1 reg_rdata_next[0] = alert_regwen_43_qs;
Tests: T1 T2 T10
18143 end
18144
18145 addr_hit[50]: begin
18146 1/1 reg_rdata_next[0] = alert_regwen_44_qs;
Tests: T1 T2 T10
18147 end
18148
18149 addr_hit[51]: begin
18150 1/1 reg_rdata_next[0] = alert_regwen_45_qs;
Tests: T1 T2 T3
18151 end
18152
18153 addr_hit[52]: begin
18154 1/1 reg_rdata_next[0] = alert_regwen_46_qs;
Tests: T1 T2 T10
18155 end
18156
18157 addr_hit[53]: begin
18158 1/1 reg_rdata_next[0] = alert_regwen_47_qs;
Tests: T1 T2 T3
18159 end
18160
18161 addr_hit[54]: begin
18162 1/1 reg_rdata_next[0] = alert_regwen_48_qs;
Tests: T1 T2 T3
18163 end
18164
18165 addr_hit[55]: begin
18166 1/1 reg_rdata_next[0] = alert_regwen_49_qs;
Tests: T1 T2 T3
18167 end
18168
18169 addr_hit[56]: begin
18170 1/1 reg_rdata_next[0] = alert_regwen_50_qs;
Tests: T1 T2 T3
18171 end
18172
18173 addr_hit[57]: begin
18174 1/1 reg_rdata_next[0] = alert_regwen_51_qs;
Tests: T1 T2 T10
18175 end
18176
18177 addr_hit[58]: begin
18178 1/1 reg_rdata_next[0] = alert_regwen_52_qs;
Tests: T1 T2 T10
18179 end
18180
18181 addr_hit[59]: begin
18182 1/1 reg_rdata_next[0] = alert_regwen_53_qs;
Tests: T1 T2 T3
18183 end
18184
18185 addr_hit[60]: begin
18186 1/1 reg_rdata_next[0] = alert_regwen_54_qs;
Tests: T1 T2 T3
18187 end
18188
18189 addr_hit[61]: begin
18190 1/1 reg_rdata_next[0] = alert_regwen_55_qs;
Tests: T1 T2 T10
18191 end
18192
18193 addr_hit[62]: begin
18194 1/1 reg_rdata_next[0] = alert_regwen_56_qs;
Tests: T1 T2 T10
18195 end
18196
18197 addr_hit[63]: begin
18198 1/1 reg_rdata_next[0] = alert_regwen_57_qs;
Tests: T1 T2 T3
18199 end
18200
18201 addr_hit[64]: begin
18202 1/1 reg_rdata_next[0] = alert_regwen_58_qs;
Tests: T1 T2 T3
18203 end
18204
18205 addr_hit[65]: begin
18206 1/1 reg_rdata_next[0] = alert_regwen_59_qs;
Tests: T1 T2 T10
18207 end
18208
18209 addr_hit[66]: begin
18210 1/1 reg_rdata_next[0] = alert_regwen_60_qs;
Tests: T1 T2 T10
18211 end
18212
18213 addr_hit[67]: begin
18214 1/1 reg_rdata_next[0] = alert_regwen_61_qs;
Tests: T1 T2 T10
18215 end
18216
18217 addr_hit[68]: begin
18218 1/1 reg_rdata_next[0] = alert_regwen_62_qs;
Tests: T1 T2 T10
18219 end
18220
18221 addr_hit[69]: begin
18222 1/1 reg_rdata_next[0] = alert_regwen_63_qs;
Tests: T1 T2 T10
18223 end
18224
18225 addr_hit[70]: begin
18226 1/1 reg_rdata_next[0] = alert_regwen_64_qs;
Tests: T1 T2 T3
18227 end
18228
18229 addr_hit[71]: begin
18230 1/1 reg_rdata_next[0] = alert_en_shadowed_0_qs;
Tests: T1 T2 T3
18231 end
18232
18233 addr_hit[72]: begin
18234 1/1 reg_rdata_next[0] = alert_en_shadowed_1_qs;
Tests: T1 T2 T3
18235 end
18236
18237 addr_hit[73]: begin
18238 1/1 reg_rdata_next[0] = alert_en_shadowed_2_qs;
Tests: T1 T2 T3
18239 end
18240
18241 addr_hit[74]: begin
18242 1/1 reg_rdata_next[0] = alert_en_shadowed_3_qs;
Tests: T1 T2 T3
18243 end
18244
18245 addr_hit[75]: begin
18246 1/1 reg_rdata_next[0] = alert_en_shadowed_4_qs;
Tests: T1 T2 T3
18247 end
18248
18249 addr_hit[76]: begin
18250 1/1 reg_rdata_next[0] = alert_en_shadowed_5_qs;
Tests: T1 T2 T3
18251 end
18252
18253 addr_hit[77]: begin
18254 1/1 reg_rdata_next[0] = alert_en_shadowed_6_qs;
Tests: T1 T2 T3
18255 end
18256
18257 addr_hit[78]: begin
18258 1/1 reg_rdata_next[0] = alert_en_shadowed_7_qs;
Tests: T1 T2 T3
18259 end
18260
18261 addr_hit[79]: begin
18262 1/1 reg_rdata_next[0] = alert_en_shadowed_8_qs;
Tests: T1 T2 T3
18263 end
18264
18265 addr_hit[80]: begin
18266 1/1 reg_rdata_next[0] = alert_en_shadowed_9_qs;
Tests: T1 T2 T3
18267 end
18268
18269 addr_hit[81]: begin
18270 1/1 reg_rdata_next[0] = alert_en_shadowed_10_qs;
Tests: T1 T2 T3
18271 end
18272
18273 addr_hit[82]: begin
18274 1/1 reg_rdata_next[0] = alert_en_shadowed_11_qs;
Tests: T1 T2 T3
18275 end
18276
18277 addr_hit[83]: begin
18278 1/1 reg_rdata_next[0] = alert_en_shadowed_12_qs;
Tests: T1 T2 T3
18279 end
18280
18281 addr_hit[84]: begin
18282 1/1 reg_rdata_next[0] = alert_en_shadowed_13_qs;
Tests: T1 T2 T3
18283 end
18284
18285 addr_hit[85]: begin
18286 1/1 reg_rdata_next[0] = alert_en_shadowed_14_qs;
Tests: T1 T2 T3
18287 end
18288
18289 addr_hit[86]: begin
18290 1/1 reg_rdata_next[0] = alert_en_shadowed_15_qs;
Tests: T1 T2 T3
18291 end
18292
18293 addr_hit[87]: begin
18294 1/1 reg_rdata_next[0] = alert_en_shadowed_16_qs;
Tests: T1 T2 T3
18295 end
18296
18297 addr_hit[88]: begin
18298 1/1 reg_rdata_next[0] = alert_en_shadowed_17_qs;
Tests: T1 T2 T3
18299 end
18300
18301 addr_hit[89]: begin
18302 1/1 reg_rdata_next[0] = alert_en_shadowed_18_qs;
Tests: T1 T2 T3
18303 end
18304
18305 addr_hit[90]: begin
18306 1/1 reg_rdata_next[0] = alert_en_shadowed_19_qs;
Tests: T1 T2 T3
18307 end
18308
18309 addr_hit[91]: begin
18310 1/1 reg_rdata_next[0] = alert_en_shadowed_20_qs;
Tests: T1 T2 T3
18311 end
18312
18313 addr_hit[92]: begin
18314 1/1 reg_rdata_next[0] = alert_en_shadowed_21_qs;
Tests: T1 T2 T3
18315 end
18316
18317 addr_hit[93]: begin
18318 1/1 reg_rdata_next[0] = alert_en_shadowed_22_qs;
Tests: T1 T2 T3
18319 end
18320
18321 addr_hit[94]: begin
18322 1/1 reg_rdata_next[0] = alert_en_shadowed_23_qs;
Tests: T1 T2 T3
18323 end
18324
18325 addr_hit[95]: begin
18326 1/1 reg_rdata_next[0] = alert_en_shadowed_24_qs;
Tests: T1 T2 T3
18327 end
18328
18329 addr_hit[96]: begin
18330 1/1 reg_rdata_next[0] = alert_en_shadowed_25_qs;
Tests: T1 T2 T3
18331 end
18332
18333 addr_hit[97]: begin
18334 1/1 reg_rdata_next[0] = alert_en_shadowed_26_qs;
Tests: T1 T2 T3
18335 end
18336
18337 addr_hit[98]: begin
18338 1/1 reg_rdata_next[0] = alert_en_shadowed_27_qs;
Tests: T1 T2 T3
18339 end
18340
18341 addr_hit[99]: begin
18342 1/1 reg_rdata_next[0] = alert_en_shadowed_28_qs;
Tests: T1 T2 T3
18343 end
18344
18345 addr_hit[100]: begin
18346 1/1 reg_rdata_next[0] = alert_en_shadowed_29_qs;
Tests: T1 T2 T3
18347 end
18348
18349 addr_hit[101]: begin
18350 1/1 reg_rdata_next[0] = alert_en_shadowed_30_qs;
Tests: T1 T2 T3
18351 end
18352
18353 addr_hit[102]: begin
18354 1/1 reg_rdata_next[0] = alert_en_shadowed_31_qs;
Tests: T1 T2 T3
18355 end
18356
18357 addr_hit[103]: begin
18358 1/1 reg_rdata_next[0] = alert_en_shadowed_32_qs;
Tests: T1 T2 T3
18359 end
18360
18361 addr_hit[104]: begin
18362 1/1 reg_rdata_next[0] = alert_en_shadowed_33_qs;
Tests: T1 T2 T3
18363 end
18364
18365 addr_hit[105]: begin
18366 1/1 reg_rdata_next[0] = alert_en_shadowed_34_qs;
Tests: T1 T2 T3
18367 end
18368
18369 addr_hit[106]: begin
18370 1/1 reg_rdata_next[0] = alert_en_shadowed_35_qs;
Tests: T1 T2 T3
18371 end
18372
18373 addr_hit[107]: begin
18374 1/1 reg_rdata_next[0] = alert_en_shadowed_36_qs;
Tests: T1 T2 T3
18375 end
18376
18377 addr_hit[108]: begin
18378 1/1 reg_rdata_next[0] = alert_en_shadowed_37_qs;
Tests: T1 T2 T3
18379 end
18380
18381 addr_hit[109]: begin
18382 1/1 reg_rdata_next[0] = alert_en_shadowed_38_qs;
Tests: T1 T2 T3
18383 end
18384
18385 addr_hit[110]: begin
18386 1/1 reg_rdata_next[0] = alert_en_shadowed_39_qs;
Tests: T1 T2 T3
18387 end
18388
18389 addr_hit[111]: begin
18390 1/1 reg_rdata_next[0] = alert_en_shadowed_40_qs;
Tests: T1 T2 T3
18391 end
18392
18393 addr_hit[112]: begin
18394 1/1 reg_rdata_next[0] = alert_en_shadowed_41_qs;
Tests: T1 T2 T3
18395 end
18396
18397 addr_hit[113]: begin
18398 1/1 reg_rdata_next[0] = alert_en_shadowed_42_qs;
Tests: T1 T2 T3
18399 end
18400
18401 addr_hit[114]: begin
18402 1/1 reg_rdata_next[0] = alert_en_shadowed_43_qs;
Tests: T1 T2 T3
18403 end
18404
18405 addr_hit[115]: begin
18406 1/1 reg_rdata_next[0] = alert_en_shadowed_44_qs;
Tests: T1 T2 T3
18407 end
18408
18409 addr_hit[116]: begin
18410 1/1 reg_rdata_next[0] = alert_en_shadowed_45_qs;
Tests: T1 T2 T3
18411 end
18412
18413 addr_hit[117]: begin
18414 1/1 reg_rdata_next[0] = alert_en_shadowed_46_qs;
Tests: T1 T2 T3
18415 end
18416
18417 addr_hit[118]: begin
18418 1/1 reg_rdata_next[0] = alert_en_shadowed_47_qs;
Tests: T1 T2 T3
18419 end
18420
18421 addr_hit[119]: begin
18422 1/1 reg_rdata_next[0] = alert_en_shadowed_48_qs;
Tests: T1 T2 T3
18423 end
18424
18425 addr_hit[120]: begin
18426 1/1 reg_rdata_next[0] = alert_en_shadowed_49_qs;
Tests: T1 T2 T3
18427 end
18428
18429 addr_hit[121]: begin
18430 1/1 reg_rdata_next[0] = alert_en_shadowed_50_qs;
Tests: T1 T2 T3
18431 end
18432
18433 addr_hit[122]: begin
18434 1/1 reg_rdata_next[0] = alert_en_shadowed_51_qs;
Tests: T1 T2 T3
18435 end
18436
18437 addr_hit[123]: begin
18438 1/1 reg_rdata_next[0] = alert_en_shadowed_52_qs;
Tests: T1 T2 T3
18439 end
18440
18441 addr_hit[124]: begin
18442 1/1 reg_rdata_next[0] = alert_en_shadowed_53_qs;
Tests: T1 T2 T3
18443 end
18444
18445 addr_hit[125]: begin
18446 1/1 reg_rdata_next[0] = alert_en_shadowed_54_qs;
Tests: T1 T2 T3
18447 end
18448
18449 addr_hit[126]: begin
18450 1/1 reg_rdata_next[0] = alert_en_shadowed_55_qs;
Tests: T1 T2 T3
18451 end
18452
18453 addr_hit[127]: begin
18454 1/1 reg_rdata_next[0] = alert_en_shadowed_56_qs;
Tests: T1 T2 T3
18455 end
18456
18457 addr_hit[128]: begin
18458 1/1 reg_rdata_next[0] = alert_en_shadowed_57_qs;
Tests: T1 T2 T3
18459 end
18460
18461 addr_hit[129]: begin
18462 1/1 reg_rdata_next[0] = alert_en_shadowed_58_qs;
Tests: T1 T2 T3
18463 end
18464
18465 addr_hit[130]: begin
18466 1/1 reg_rdata_next[0] = alert_en_shadowed_59_qs;
Tests: T1 T2 T3
18467 end
18468
18469 addr_hit[131]: begin
18470 1/1 reg_rdata_next[0] = alert_en_shadowed_60_qs;
Tests: T1 T2 T3
18471 end
18472
18473 addr_hit[132]: begin
18474 1/1 reg_rdata_next[0] = alert_en_shadowed_61_qs;
Tests: T1 T2 T3
18475 end
18476
18477 addr_hit[133]: begin
18478 1/1 reg_rdata_next[0] = alert_en_shadowed_62_qs;
Tests: T1 T2 T3
18479 end
18480
18481 addr_hit[134]: begin
18482 1/1 reg_rdata_next[0] = alert_en_shadowed_63_qs;
Tests: T1 T2 T3
18483 end
18484
18485 addr_hit[135]: begin
18486 1/1 reg_rdata_next[0] = alert_en_shadowed_64_qs;
Tests: T1 T2 T3
18487 end
18488
18489 addr_hit[136]: begin
18490 1/1 reg_rdata_next[1:0] = alert_class_shadowed_0_qs;
Tests: T1 T2 T3
18491 end
18492
18493 addr_hit[137]: begin
18494 1/1 reg_rdata_next[1:0] = alert_class_shadowed_1_qs;
Tests: T1 T2 T3
18495 end
18496
18497 addr_hit[138]: begin
18498 1/1 reg_rdata_next[1:0] = alert_class_shadowed_2_qs;
Tests: T1 T2 T3
18499 end
18500
18501 addr_hit[139]: begin
18502 1/1 reg_rdata_next[1:0] = alert_class_shadowed_3_qs;
Tests: T1 T2 T3
18503 end
18504
18505 addr_hit[140]: begin
18506 1/1 reg_rdata_next[1:0] = alert_class_shadowed_4_qs;
Tests: T1 T2 T3
18507 end
18508
18509 addr_hit[141]: begin
18510 1/1 reg_rdata_next[1:0] = alert_class_shadowed_5_qs;
Tests: T1 T2 T3
18511 end
18512
18513 addr_hit[142]: begin
18514 1/1 reg_rdata_next[1:0] = alert_class_shadowed_6_qs;
Tests: T1 T2 T3
18515 end
18516
18517 addr_hit[143]: begin
18518 1/1 reg_rdata_next[1:0] = alert_class_shadowed_7_qs;
Tests: T1 T2 T3
18519 end
18520
18521 addr_hit[144]: begin
18522 1/1 reg_rdata_next[1:0] = alert_class_shadowed_8_qs;
Tests: T1 T2 T3
18523 end
18524
18525 addr_hit[145]: begin
18526 1/1 reg_rdata_next[1:0] = alert_class_shadowed_9_qs;
Tests: T1 T2 T3
18527 end
18528
18529 addr_hit[146]: begin
18530 1/1 reg_rdata_next[1:0] = alert_class_shadowed_10_qs;
Tests: T1 T2 T3
18531 end
18532
18533 addr_hit[147]: begin
18534 1/1 reg_rdata_next[1:0] = alert_class_shadowed_11_qs;
Tests: T1 T2 T3
18535 end
18536
18537 addr_hit[148]: begin
18538 1/1 reg_rdata_next[1:0] = alert_class_shadowed_12_qs;
Tests: T1 T2 T3
18539 end
18540
18541 addr_hit[149]: begin
18542 1/1 reg_rdata_next[1:0] = alert_class_shadowed_13_qs;
Tests: T1 T2 T3
18543 end
18544
18545 addr_hit[150]: begin
18546 1/1 reg_rdata_next[1:0] = alert_class_shadowed_14_qs;
Tests: T1 T2 T3
18547 end
18548
18549 addr_hit[151]: begin
18550 1/1 reg_rdata_next[1:0] = alert_class_shadowed_15_qs;
Tests: T1 T2 T3
18551 end
18552
18553 addr_hit[152]: begin
18554 1/1 reg_rdata_next[1:0] = alert_class_shadowed_16_qs;
Tests: T1 T2 T3
18555 end
18556
18557 addr_hit[153]: begin
18558 1/1 reg_rdata_next[1:0] = alert_class_shadowed_17_qs;
Tests: T1 T2 T3
18559 end
18560
18561 addr_hit[154]: begin
18562 1/1 reg_rdata_next[1:0] = alert_class_shadowed_18_qs;
Tests: T1 T2 T3
18563 end
18564
18565 addr_hit[155]: begin
18566 1/1 reg_rdata_next[1:0] = alert_class_shadowed_19_qs;
Tests: T1 T2 T3
18567 end
18568
18569 addr_hit[156]: begin
18570 1/1 reg_rdata_next[1:0] = alert_class_shadowed_20_qs;
Tests: T1 T2 T3
18571 end
18572
18573 addr_hit[157]: begin
18574 1/1 reg_rdata_next[1:0] = alert_class_shadowed_21_qs;
Tests: T1 T2 T3
18575 end
18576
18577 addr_hit[158]: begin
18578 1/1 reg_rdata_next[1:0] = alert_class_shadowed_22_qs;
Tests: T1 T2 T3
18579 end
18580
18581 addr_hit[159]: begin
18582 1/1 reg_rdata_next[1:0] = alert_class_shadowed_23_qs;
Tests: T1 T2 T3
18583 end
18584
18585 addr_hit[160]: begin
18586 1/1 reg_rdata_next[1:0] = alert_class_shadowed_24_qs;
Tests: T1 T2 T3
18587 end
18588
18589 addr_hit[161]: begin
18590 1/1 reg_rdata_next[1:0] = alert_class_shadowed_25_qs;
Tests: T1 T2 T3
18591 end
18592
18593 addr_hit[162]: begin
18594 1/1 reg_rdata_next[1:0] = alert_class_shadowed_26_qs;
Tests: T1 T2 T3
18595 end
18596
18597 addr_hit[163]: begin
18598 1/1 reg_rdata_next[1:0] = alert_class_shadowed_27_qs;
Tests: T1 T2 T3
18599 end
18600
18601 addr_hit[164]: begin
18602 1/1 reg_rdata_next[1:0] = alert_class_shadowed_28_qs;
Tests: T1 T2 T3
18603 end
18604
18605 addr_hit[165]: begin
18606 1/1 reg_rdata_next[1:0] = alert_class_shadowed_29_qs;
Tests: T1 T2 T3
18607 end
18608
18609 addr_hit[166]: begin
18610 1/1 reg_rdata_next[1:0] = alert_class_shadowed_30_qs;
Tests: T1 T2 T3
18611 end
18612
18613 addr_hit[167]: begin
18614 1/1 reg_rdata_next[1:0] = alert_class_shadowed_31_qs;
Tests: T1 T2 T3
18615 end
18616
18617 addr_hit[168]: begin
18618 1/1 reg_rdata_next[1:0] = alert_class_shadowed_32_qs;
Tests: T1 T2 T3
18619 end
18620
18621 addr_hit[169]: begin
18622 1/1 reg_rdata_next[1:0] = alert_class_shadowed_33_qs;
Tests: T1 T2 T3
18623 end
18624
18625 addr_hit[170]: begin
18626 1/1 reg_rdata_next[1:0] = alert_class_shadowed_34_qs;
Tests: T1 T2 T3
18627 end
18628
18629 addr_hit[171]: begin
18630 1/1 reg_rdata_next[1:0] = alert_class_shadowed_35_qs;
Tests: T1 T2 T3
18631 end
18632
18633 addr_hit[172]: begin
18634 1/1 reg_rdata_next[1:0] = alert_class_shadowed_36_qs;
Tests: T1 T2 T3
18635 end
18636
18637 addr_hit[173]: begin
18638 1/1 reg_rdata_next[1:0] = alert_class_shadowed_37_qs;
Tests: T1 T2 T3
18639 end
18640
18641 addr_hit[174]: begin
18642 1/1 reg_rdata_next[1:0] = alert_class_shadowed_38_qs;
Tests: T1 T2 T3
18643 end
18644
18645 addr_hit[175]: begin
18646 1/1 reg_rdata_next[1:0] = alert_class_shadowed_39_qs;
Tests: T1 T2 T3
18647 end
18648
18649 addr_hit[176]: begin
18650 1/1 reg_rdata_next[1:0] = alert_class_shadowed_40_qs;
Tests: T1 T2 T3
18651 end
18652
18653 addr_hit[177]: begin
18654 1/1 reg_rdata_next[1:0] = alert_class_shadowed_41_qs;
Tests: T1 T2 T3
18655 end
18656
18657 addr_hit[178]: begin
18658 1/1 reg_rdata_next[1:0] = alert_class_shadowed_42_qs;
Tests: T1 T2 T3
18659 end
18660
18661 addr_hit[179]: begin
18662 1/1 reg_rdata_next[1:0] = alert_class_shadowed_43_qs;
Tests: T1 T2 T3
18663 end
18664
18665 addr_hit[180]: begin
18666 1/1 reg_rdata_next[1:0] = alert_class_shadowed_44_qs;
Tests: T1 T2 T3
18667 end
18668
18669 addr_hit[181]: begin
18670 1/1 reg_rdata_next[1:0] = alert_class_shadowed_45_qs;
Tests: T1 T2 T3
18671 end
18672
18673 addr_hit[182]: begin
18674 1/1 reg_rdata_next[1:0] = alert_class_shadowed_46_qs;
Tests: T1 T2 T3
18675 end
18676
18677 addr_hit[183]: begin
18678 1/1 reg_rdata_next[1:0] = alert_class_shadowed_47_qs;
Tests: T1 T2 T3
18679 end
18680
18681 addr_hit[184]: begin
18682 1/1 reg_rdata_next[1:0] = alert_class_shadowed_48_qs;
Tests: T1 T2 T3
18683 end
18684
18685 addr_hit[185]: begin
18686 1/1 reg_rdata_next[1:0] = alert_class_shadowed_49_qs;
Tests: T1 T2 T3
18687 end
18688
18689 addr_hit[186]: begin
18690 1/1 reg_rdata_next[1:0] = alert_class_shadowed_50_qs;
Tests: T1 T2 T3
18691 end
18692
18693 addr_hit[187]: begin
18694 1/1 reg_rdata_next[1:0] = alert_class_shadowed_51_qs;
Tests: T1 T2 T3
18695 end
18696
18697 addr_hit[188]: begin
18698 1/1 reg_rdata_next[1:0] = alert_class_shadowed_52_qs;
Tests: T1 T2 T3
18699 end
18700
18701 addr_hit[189]: begin
18702 1/1 reg_rdata_next[1:0] = alert_class_shadowed_53_qs;
Tests: T1 T2 T3
18703 end
18704
18705 addr_hit[190]: begin
18706 1/1 reg_rdata_next[1:0] = alert_class_shadowed_54_qs;
Tests: T1 T2 T3
18707 end
18708
18709 addr_hit[191]: begin
18710 1/1 reg_rdata_next[1:0] = alert_class_shadowed_55_qs;
Tests: T1 T2 T3
18711 end
18712
18713 addr_hit[192]: begin
18714 1/1 reg_rdata_next[1:0] = alert_class_shadowed_56_qs;
Tests: T1 T2 T3
18715 end
18716
18717 addr_hit[193]: begin
18718 1/1 reg_rdata_next[1:0] = alert_class_shadowed_57_qs;
Tests: T1 T2 T3
18719 end
18720
18721 addr_hit[194]: begin
18722 1/1 reg_rdata_next[1:0] = alert_class_shadowed_58_qs;
Tests: T1 T2 T3
18723 end
18724
18725 addr_hit[195]: begin
18726 1/1 reg_rdata_next[1:0] = alert_class_shadowed_59_qs;
Tests: T1 T2 T3
18727 end
18728
18729 addr_hit[196]: begin
18730 1/1 reg_rdata_next[1:0] = alert_class_shadowed_60_qs;
Tests: T1 T2 T3
18731 end
18732
18733 addr_hit[197]: begin
18734 1/1 reg_rdata_next[1:0] = alert_class_shadowed_61_qs;
Tests: T1 T2 T3
18735 end
18736
18737 addr_hit[198]: begin
18738 1/1 reg_rdata_next[1:0] = alert_class_shadowed_62_qs;
Tests: T1 T2 T3
18739 end
18740
18741 addr_hit[199]: begin
18742 1/1 reg_rdata_next[1:0] = alert_class_shadowed_63_qs;
Tests: T1 T2 T3
18743 end
18744
18745 addr_hit[200]: begin
18746 1/1 reg_rdata_next[1:0] = alert_class_shadowed_64_qs;
Tests: T1 T2 T3
18747 end
18748
18749 addr_hit[201]: begin
18750 1/1 reg_rdata_next[0] = alert_cause_0_qs;
Tests: T1 T2 T3
18751 end
18752
18753 addr_hit[202]: begin
18754 1/1 reg_rdata_next[0] = alert_cause_1_qs;
Tests: T1 T2 T10
18755 end
18756
18757 addr_hit[203]: begin
18758 1/1 reg_rdata_next[0] = alert_cause_2_qs;
Tests: T1 T2 T3
18759 end
18760
18761 addr_hit[204]: begin
18762 1/1 reg_rdata_next[0] = alert_cause_3_qs;
Tests: T1 T2 T3
18763 end
18764
18765 addr_hit[205]: begin
18766 1/1 reg_rdata_next[0] = alert_cause_4_qs;
Tests: T1 T2 T10
18767 end
18768
18769 addr_hit[206]: begin
18770 1/1 reg_rdata_next[0] = alert_cause_5_qs;
Tests: T1 T2 T3
18771 end
18772
18773 addr_hit[207]: begin
18774 1/1 reg_rdata_next[0] = alert_cause_6_qs;
Tests: T1 T2 T10
18775 end
18776
18777 addr_hit[208]: begin
18778 1/1 reg_rdata_next[0] = alert_cause_7_qs;
Tests: T1 T2 T10
18779 end
18780
18781 addr_hit[209]: begin
18782 1/1 reg_rdata_next[0] = alert_cause_8_qs;
Tests: T1 T2 T3
18783 end
18784
18785 addr_hit[210]: begin
18786 1/1 reg_rdata_next[0] = alert_cause_9_qs;
Tests: T1 T2 T3
18787 end
18788
18789 addr_hit[211]: begin
18790 1/1 reg_rdata_next[0] = alert_cause_10_qs;
Tests: T1 T2 T3
18791 end
18792
18793 addr_hit[212]: begin
18794 1/1 reg_rdata_next[0] = alert_cause_11_qs;
Tests: T1 T2 T3
18795 end
18796
18797 addr_hit[213]: begin
18798 1/1 reg_rdata_next[0] = alert_cause_12_qs;
Tests: T1 T2 T3
18799 end
18800
18801 addr_hit[214]: begin
18802 1/1 reg_rdata_next[0] = alert_cause_13_qs;
Tests: T1 T2 T10
18803 end
18804
18805 addr_hit[215]: begin
18806 1/1 reg_rdata_next[0] = alert_cause_14_qs;
Tests: T1 T2 T3
18807 end
18808
18809 addr_hit[216]: begin
18810 1/1 reg_rdata_next[0] = alert_cause_15_qs;
Tests: T1 T2 T10
18811 end
18812
18813 addr_hit[217]: begin
18814 1/1 reg_rdata_next[0] = alert_cause_16_qs;
Tests: T1 T2 T3
18815 end
18816
18817 addr_hit[218]: begin
18818 1/1 reg_rdata_next[0] = alert_cause_17_qs;
Tests: T1 T2 T10
18819 end
18820
18821 addr_hit[219]: begin
18822 1/1 reg_rdata_next[0] = alert_cause_18_qs;
Tests: T1 T2 T10
18823 end
18824
18825 addr_hit[220]: begin
18826 1/1 reg_rdata_next[0] = alert_cause_19_qs;
Tests: T1 T2 T3
18827 end
18828
18829 addr_hit[221]: begin
18830 1/1 reg_rdata_next[0] = alert_cause_20_qs;
Tests: T1 T2 T3
18831 end
18832
18833 addr_hit[222]: begin
18834 1/1 reg_rdata_next[0] = alert_cause_21_qs;
Tests: T1 T2 T3
18835 end
18836
18837 addr_hit[223]: begin
18838 1/1 reg_rdata_next[0] = alert_cause_22_qs;
Tests: T1 T2 T10
18839 end
18840
18841 addr_hit[224]: begin
18842 1/1 reg_rdata_next[0] = alert_cause_23_qs;
Tests: T1 T2 T10
18843 end
18844
18845 addr_hit[225]: begin
18846 1/1 reg_rdata_next[0] = alert_cause_24_qs;
Tests: T1 T2 T10
18847 end
18848
18849 addr_hit[226]: begin
18850 1/1 reg_rdata_next[0] = alert_cause_25_qs;
Tests: T1 T2 T3
18851 end
18852
18853 addr_hit[227]: begin
18854 1/1 reg_rdata_next[0] = alert_cause_26_qs;
Tests: T1 T2 T10
18855 end
18856
18857 addr_hit[228]: begin
18858 1/1 reg_rdata_next[0] = alert_cause_27_qs;
Tests: T1 T2 T10
18859 end
18860
18861 addr_hit[229]: begin
18862 1/1 reg_rdata_next[0] = alert_cause_28_qs;
Tests: T1 T2 T10
18863 end
18864
18865 addr_hit[230]: begin
18866 1/1 reg_rdata_next[0] = alert_cause_29_qs;
Tests: T1 T2 T10
18867 end
18868
18869 addr_hit[231]: begin
18870 1/1 reg_rdata_next[0] = alert_cause_30_qs;
Tests: T1 T2 T10
18871 end
18872
18873 addr_hit[232]: begin
18874 1/1 reg_rdata_next[0] = alert_cause_31_qs;
Tests: T1 T2 T3
18875 end
18876
18877 addr_hit[233]: begin
18878 1/1 reg_rdata_next[0] = alert_cause_32_qs;
Tests: T1 T2 T3
18879 end
18880
18881 addr_hit[234]: begin
18882 1/1 reg_rdata_next[0] = alert_cause_33_qs;
Tests: T1 T2 T3
18883 end
18884
18885 addr_hit[235]: begin
18886 1/1 reg_rdata_next[0] = alert_cause_34_qs;
Tests: T1 T2 T10
18887 end
18888
18889 addr_hit[236]: begin
18890 1/1 reg_rdata_next[0] = alert_cause_35_qs;
Tests: T1 T2 T3
18891 end
18892
18893 addr_hit[237]: begin
18894 1/1 reg_rdata_next[0] = alert_cause_36_qs;
Tests: T1 T2 T3
18895 end
18896
18897 addr_hit[238]: begin
18898 1/1 reg_rdata_next[0] = alert_cause_37_qs;
Tests: T1 T2 T10
18899 end
18900
18901 addr_hit[239]: begin
18902 1/1 reg_rdata_next[0] = alert_cause_38_qs;
Tests: T1 T2 T3
18903 end
18904
18905 addr_hit[240]: begin
18906 1/1 reg_rdata_next[0] = alert_cause_39_qs;
Tests: T1 T2 T3
18907 end
18908
18909 addr_hit[241]: begin
18910 1/1 reg_rdata_next[0] = alert_cause_40_qs;
Tests: T1 T2 T10
18911 end
18912
18913 addr_hit[242]: begin
18914 1/1 reg_rdata_next[0] = alert_cause_41_qs;
Tests: T1 T2 T10
18915 end
18916
18917 addr_hit[243]: begin
18918 1/1 reg_rdata_next[0] = alert_cause_42_qs;
Tests: T1 T2 T3
18919 end
18920
18921 addr_hit[244]: begin
18922 1/1 reg_rdata_next[0] = alert_cause_43_qs;
Tests: T1 T2 T10
18923 end
18924
18925 addr_hit[245]: begin
18926 1/1 reg_rdata_next[0] = alert_cause_44_qs;
Tests: T1 T2 T3
18927 end
18928
18929 addr_hit[246]: begin
18930 1/1 reg_rdata_next[0] = alert_cause_45_qs;
Tests: T1 T2 T10
18931 end
18932
18933 addr_hit[247]: begin
18934 1/1 reg_rdata_next[0] = alert_cause_46_qs;
Tests: T1 T2 T3
18935 end
18936
18937 addr_hit[248]: begin
18938 1/1 reg_rdata_next[0] = alert_cause_47_qs;
Tests: T1 T2 T3
18939 end
18940
18941 addr_hit[249]: begin
18942 1/1 reg_rdata_next[0] = alert_cause_48_qs;
Tests: T1 T2 T10
18943 end
18944
18945 addr_hit[250]: begin
18946 1/1 reg_rdata_next[0] = alert_cause_49_qs;
Tests: T1 T2 T10
18947 end
18948
18949 addr_hit[251]: begin
18950 1/1 reg_rdata_next[0] = alert_cause_50_qs;
Tests: T1 T2 T3
18951 end
18952
18953 addr_hit[252]: begin
18954 1/1 reg_rdata_next[0] = alert_cause_51_qs;
Tests: T1 T2 T3
18955 end
18956
18957 addr_hit[253]: begin
18958 1/1 reg_rdata_next[0] = alert_cause_52_qs;
Tests: T1 T2 T10
18959 end
18960
18961 addr_hit[254]: begin
18962 1/1 reg_rdata_next[0] = alert_cause_53_qs;
Tests: T1 T2 T10
18963 end
18964
18965 addr_hit[255]: begin
18966 1/1 reg_rdata_next[0] = alert_cause_54_qs;
Tests: T1 T2 T3
18967 end
18968
18969 addr_hit[256]: begin
18970 1/1 reg_rdata_next[0] = alert_cause_55_qs;
Tests: T1 T2 T3
18971 end
18972
18973 addr_hit[257]: begin
18974 1/1 reg_rdata_next[0] = alert_cause_56_qs;
Tests: T1 T2 T3
18975 end
18976
18977 addr_hit[258]: begin
18978 1/1 reg_rdata_next[0] = alert_cause_57_qs;
Tests: T1 T2 T10
18979 end
18980
18981 addr_hit[259]: begin
18982 1/1 reg_rdata_next[0] = alert_cause_58_qs;
Tests: T1 T2 T10
18983 end
18984
18985 addr_hit[260]: begin
18986 1/1 reg_rdata_next[0] = alert_cause_59_qs;
Tests: T1 T2 T3
18987 end
18988
18989 addr_hit[261]: begin
18990 1/1 reg_rdata_next[0] = alert_cause_60_qs;
Tests: T1 T2 T10
18991 end
18992
18993 addr_hit[262]: begin
18994 1/1 reg_rdata_next[0] = alert_cause_61_qs;
Tests: T1 T2 T3
18995 end
18996
18997 addr_hit[263]: begin
18998 1/1 reg_rdata_next[0] = alert_cause_62_qs;
Tests: T1 T2 T10
18999 end
19000
19001 addr_hit[264]: begin
19002 1/1 reg_rdata_next[0] = alert_cause_63_qs;
Tests: T1 T2 T10
19003 end
19004
19005 addr_hit[265]: begin
19006 1/1 reg_rdata_next[0] = alert_cause_64_qs;
Tests: T1 T2 T3
19007 end
19008
19009 addr_hit[266]: begin
19010 1/1 reg_rdata_next[0] = loc_alert_regwen_0_qs;
Tests: T1 T2 T3
19011 end
19012
19013 addr_hit[267]: begin
19014 1/1 reg_rdata_next[0] = loc_alert_regwen_1_qs;
Tests: T1 T2 T10
19015 end
19016
19017 addr_hit[268]: begin
19018 1/1 reg_rdata_next[0] = loc_alert_regwen_2_qs;
Tests: T1 T2 T10
19019 end
19020
19021 addr_hit[269]: begin
19022 1/1 reg_rdata_next[0] = loc_alert_regwen_3_qs;
Tests: T1 T2 T10
19023 end
19024
19025 addr_hit[270]: begin
19026 1/1 reg_rdata_next[0] = loc_alert_regwen_4_qs;
Tests: T1 T2 T10
19027 end
19028
19029 addr_hit[271]: begin
19030 1/1 reg_rdata_next[0] = loc_alert_regwen_5_qs;
Tests: T1 T2 T3
19031 end
19032
19033 addr_hit[272]: begin
19034 1/1 reg_rdata_next[0] = loc_alert_regwen_6_qs;
Tests: T1 T2 T10
19035 end
19036
19037 addr_hit[273]: begin
19038 1/1 reg_rdata_next[0] = loc_alert_en_shadowed_0_qs;
Tests: T1 T2 T3
19039 end
19040
19041 addr_hit[274]: begin
19042 1/1 reg_rdata_next[0] = loc_alert_en_shadowed_1_qs;
Tests: T1 T2 T3
19043 end
19044
19045 addr_hit[275]: begin
19046 1/1 reg_rdata_next[0] = loc_alert_en_shadowed_2_qs;
Tests: T1 T2 T3
19047 end
19048
19049 addr_hit[276]: begin
19050 1/1 reg_rdata_next[0] = loc_alert_en_shadowed_3_qs;
Tests: T1 T2 T3
19051 end
19052
19053 addr_hit[277]: begin
19054 1/1 reg_rdata_next[0] = loc_alert_en_shadowed_4_qs;
Tests: T1 T2 T3
19055 end
19056
19057 addr_hit[278]: begin
19058 1/1 reg_rdata_next[0] = loc_alert_en_shadowed_5_qs;
Tests: T1 T2 T3
19059 end
19060
19061 addr_hit[279]: begin
19062 1/1 reg_rdata_next[0] = loc_alert_en_shadowed_6_qs;
Tests: T1 T2 T3
19063 end
19064
19065 addr_hit[280]: begin
19066 1/1 reg_rdata_next[1:0] = loc_alert_class_shadowed_0_qs;
Tests: T1 T2 T3
19067 end
19068
19069 addr_hit[281]: begin
19070 1/1 reg_rdata_next[1:0] = loc_alert_class_shadowed_1_qs;
Tests: T1 T2 T3
19071 end
19072
19073 addr_hit[282]: begin
19074 1/1 reg_rdata_next[1:0] = loc_alert_class_shadowed_2_qs;
Tests: T1 T2 T3
19075 end
19076
19077 addr_hit[283]: begin
19078 1/1 reg_rdata_next[1:0] = loc_alert_class_shadowed_3_qs;
Tests: T1 T2 T3
19079 end
19080
19081 addr_hit[284]: begin
19082 1/1 reg_rdata_next[1:0] = loc_alert_class_shadowed_4_qs;
Tests: T1 T2 T3
19083 end
19084
19085 addr_hit[285]: begin
19086 1/1 reg_rdata_next[1:0] = loc_alert_class_shadowed_5_qs;
Tests: T1 T2 T3
19087 end
19088
19089 addr_hit[286]: begin
19090 1/1 reg_rdata_next[1:0] = loc_alert_class_shadowed_6_qs;
Tests: T1 T2 T3
19091 end
19092
19093 addr_hit[287]: begin
19094 1/1 reg_rdata_next[0] = loc_alert_cause_0_qs;
Tests: T1 T2 T10
19095 end
19096
19097 addr_hit[288]: begin
19098 1/1 reg_rdata_next[0] = loc_alert_cause_1_qs;
Tests: T1 T2 T10
19099 end
19100
19101 addr_hit[289]: begin
19102 1/1 reg_rdata_next[0] = loc_alert_cause_2_qs;
Tests: T1 T2 T10
19103 end
19104
19105 addr_hit[290]: begin
19106 1/1 reg_rdata_next[0] = loc_alert_cause_3_qs;
Tests: T1 T2 T3
19107 end
19108
19109 addr_hit[291]: begin
19110 1/1 reg_rdata_next[0] = loc_alert_cause_4_qs;
Tests: T1 T2 T3
19111 end
19112
19113 addr_hit[292]: begin
19114 1/1 reg_rdata_next[0] = loc_alert_cause_5_qs;
Tests: T1 T2 T3
19115 end
19116
19117 addr_hit[293]: begin
19118 1/1 reg_rdata_next[0] = loc_alert_cause_6_qs;
Tests: T1 T2 T3
19119 end
19120
19121 addr_hit[294]: begin
19122 1/1 reg_rdata_next[0] = classa_regwen_qs;
Tests: T1 T2 T3
19123 end
19124
19125 addr_hit[295]: begin
19126 1/1 reg_rdata_next[0] = classa_ctrl_shadowed_en_qs;
Tests: T1 T2 T3
19127 1/1 reg_rdata_next[1] = classa_ctrl_shadowed_lock_qs;
Tests: T1 T2 T3
19128 1/1 reg_rdata_next[2] = classa_ctrl_shadowed_en_e0_qs;
Tests: T1 T2 T3
19129 1/1 reg_rdata_next[3] = classa_ctrl_shadowed_en_e1_qs;
Tests: T1 T2 T3
19130 1/1 reg_rdata_next[4] = classa_ctrl_shadowed_en_e2_qs;
Tests: T1 T2 T3
19131 1/1 reg_rdata_next[5] = classa_ctrl_shadowed_en_e3_qs;
Tests: T1 T2 T3
19132 1/1 reg_rdata_next[7:6] = classa_ctrl_shadowed_map_e0_qs;
Tests: T1 T2 T3
19133 1/1 reg_rdata_next[9:8] = classa_ctrl_shadowed_map_e1_qs;
Tests: T1 T2 T3
19134 1/1 reg_rdata_next[11:10] = classa_ctrl_shadowed_map_e2_qs;
Tests: T1 T2 T3
19135 1/1 reg_rdata_next[13:12] = classa_ctrl_shadowed_map_e3_qs;
Tests: T1 T2 T3
19136 end
19137
19138 addr_hit[296]: begin
19139 1/1 reg_rdata_next[0] = classa_clr_regwen_qs;
Tests: T1 T2 T10
19140 end
19141
19142 addr_hit[297]: begin
19143 1/1 reg_rdata_next[0] = classa_clr_shadowed_qs;
Tests: T1 T2 T3
19144 end
19145
19146 addr_hit[298]: begin
19147 1/1 reg_rdata_next[15:0] = classa_accum_cnt_qs;
Tests: T1 T2 T3
19148 end
19149
19150 addr_hit[299]: begin
19151 1/1 reg_rdata_next[15:0] = classa_accum_thresh_shadowed_qs;
Tests: T1 T2 T3
19152 end
19153
19154 addr_hit[300]: begin
19155 1/1 reg_rdata_next[31:0] = classa_timeout_cyc_shadowed_qs;
Tests: T1 T2 T10
19156 end
19157
19158 addr_hit[301]: begin
19159 1/1 reg_rdata_next[1:0] = classa_crashdump_trigger_shadowed_qs;
Tests: T1 T2 T10
19160 end
19161
19162 addr_hit[302]: begin
19163 1/1 reg_rdata_next[31:0] = classa_phase0_cyc_shadowed_qs;
Tests: T1 T2 T3
19164 end
19165
19166 addr_hit[303]: begin
19167 1/1 reg_rdata_next[31:0] = classa_phase1_cyc_shadowed_qs;
Tests: T1 T2 T3
19168 end
19169
19170 addr_hit[304]: begin
19171 1/1 reg_rdata_next[31:0] = classa_phase2_cyc_shadowed_qs;
Tests: T1 T2 T10
19172 end
19173
19174 addr_hit[305]: begin
19175 1/1 reg_rdata_next[31:0] = classa_phase3_cyc_shadowed_qs;
Tests: T1 T2 T10
19176 end
19177
19178 addr_hit[306]: begin
19179 1/1 reg_rdata_next[31:0] = classa_esc_cnt_qs;
Tests: T1 T2 T10
19180 end
19181
19182 addr_hit[307]: begin
19183 1/1 reg_rdata_next[2:0] = classa_state_qs;
Tests: T1 T2 T10
19184 end
19185
19186 addr_hit[308]: begin
19187 1/1 reg_rdata_next[0] = classb_regwen_qs;
Tests: T1 T2 T3
19188 end
19189
19190 addr_hit[309]: begin
19191 1/1 reg_rdata_next[0] = classb_ctrl_shadowed_en_qs;
Tests: T1 T2 T3
19192 1/1 reg_rdata_next[1] = classb_ctrl_shadowed_lock_qs;
Tests: T1 T2 T3
19193 1/1 reg_rdata_next[2] = classb_ctrl_shadowed_en_e0_qs;
Tests: T1 T2 T3
19194 1/1 reg_rdata_next[3] = classb_ctrl_shadowed_en_e1_qs;
Tests: T1 T2 T3
19195 1/1 reg_rdata_next[4] = classb_ctrl_shadowed_en_e2_qs;
Tests: T1 T2 T3
19196 1/1 reg_rdata_next[5] = classb_ctrl_shadowed_en_e3_qs;
Tests: T1 T2 T3
19197 1/1 reg_rdata_next[7:6] = classb_ctrl_shadowed_map_e0_qs;
Tests: T1 T2 T3
19198 1/1 reg_rdata_next[9:8] = classb_ctrl_shadowed_map_e1_qs;
Tests: T1 T2 T3
19199 1/1 reg_rdata_next[11:10] = classb_ctrl_shadowed_map_e2_qs;
Tests: T1 T2 T3
19200 1/1 reg_rdata_next[13:12] = classb_ctrl_shadowed_map_e3_qs;
Tests: T1 T2 T3
19201 end
19202
19203 addr_hit[310]: begin
19204 1/1 reg_rdata_next[0] = classb_clr_regwen_qs;
Tests: T1 T2 T10
19205 end
19206
19207 addr_hit[311]: begin
19208 1/1 reg_rdata_next[0] = classb_clr_shadowed_qs;
Tests: T1 T2 T10
19209 end
19210
19211 addr_hit[312]: begin
19212 1/1 reg_rdata_next[15:0] = classb_accum_cnt_qs;
Tests: T1 T2 T3
19213 end
19214
19215 addr_hit[313]: begin
19216 1/1 reg_rdata_next[15:0] = classb_accum_thresh_shadowed_qs;
Tests: T1 T2 T3
19217 end
19218
19219 addr_hit[314]: begin
19220 1/1 reg_rdata_next[31:0] = classb_timeout_cyc_shadowed_qs;
Tests: T1 T2 T3
19221 end
19222
19223 addr_hit[315]: begin
19224 1/1 reg_rdata_next[1:0] = classb_crashdump_trigger_shadowed_qs;
Tests: T1 T2 T10
19225 end
19226
19227 addr_hit[316]: begin
19228 1/1 reg_rdata_next[31:0] = classb_phase0_cyc_shadowed_qs;
Tests: T1 T2 T10
19229 end
19230
19231 addr_hit[317]: begin
19232 1/1 reg_rdata_next[31:0] = classb_phase1_cyc_shadowed_qs;
Tests: T1 T2 T3
19233 end
19234
19235 addr_hit[318]: begin
19236 1/1 reg_rdata_next[31:0] = classb_phase2_cyc_shadowed_qs;
Tests: T1 T2 T3
19237 end
19238
19239 addr_hit[319]: begin
19240 1/1 reg_rdata_next[31:0] = classb_phase3_cyc_shadowed_qs;
Tests: T1 T2 T3
19241 end
19242
19243 addr_hit[320]: begin
19244 1/1 reg_rdata_next[31:0] = classb_esc_cnt_qs;
Tests: T1 T2 T3
19245 end
19246
19247 addr_hit[321]: begin
19248 1/1 reg_rdata_next[2:0] = classb_state_qs;
Tests: T1 T2 T10
19249 end
19250
19251 addr_hit[322]: begin
19252 1/1 reg_rdata_next[0] = classc_regwen_qs;
Tests: T1 T2 T3
19253 end
19254
19255 addr_hit[323]: begin
19256 1/1 reg_rdata_next[0] = classc_ctrl_shadowed_en_qs;
Tests: T1 T2 T3
19257 1/1 reg_rdata_next[1] = classc_ctrl_shadowed_lock_qs;
Tests: T1 T2 T3
19258 1/1 reg_rdata_next[2] = classc_ctrl_shadowed_en_e0_qs;
Tests: T1 T2 T3
19259 1/1 reg_rdata_next[3] = classc_ctrl_shadowed_en_e1_qs;
Tests: T1 T2 T3
19260 1/1 reg_rdata_next[4] = classc_ctrl_shadowed_en_e2_qs;
Tests: T1 T2 T3
19261 1/1 reg_rdata_next[5] = classc_ctrl_shadowed_en_e3_qs;
Tests: T1 T2 T3
19262 1/1 reg_rdata_next[7:6] = classc_ctrl_shadowed_map_e0_qs;
Tests: T1 T2 T3
19263 1/1 reg_rdata_next[9:8] = classc_ctrl_shadowed_map_e1_qs;
Tests: T1 T2 T3
19264 1/1 reg_rdata_next[11:10] = classc_ctrl_shadowed_map_e2_qs;
Tests: T1 T2 T3
19265 1/1 reg_rdata_next[13:12] = classc_ctrl_shadowed_map_e3_qs;
Tests: T1 T2 T3
19266 end
19267
19268 addr_hit[324]: begin
19269 1/1 reg_rdata_next[0] = classc_clr_regwen_qs;
Tests: T1 T2 T3
19270 end
19271
19272 addr_hit[325]: begin
19273 1/1 reg_rdata_next[0] = classc_clr_shadowed_qs;
Tests: T1 T2 T10
19274 end
19275
19276 addr_hit[326]: begin
19277 1/1 reg_rdata_next[15:0] = classc_accum_cnt_qs;
Tests: T1 T2 T3
19278 end
19279
19280 addr_hit[327]: begin
19281 1/1 reg_rdata_next[15:0] = classc_accum_thresh_shadowed_qs;
Tests: T1 T2 T3
19282 end
19283
19284 addr_hit[328]: begin
19285 1/1 reg_rdata_next[31:0] = classc_timeout_cyc_shadowed_qs;
Tests: T1 T2 T3
19286 end
19287
19288 addr_hit[329]: begin
19289 1/1 reg_rdata_next[1:0] = classc_crashdump_trigger_shadowed_qs;
Tests: T1 T2 T10
19290 end
19291
19292 addr_hit[330]: begin
19293 1/1 reg_rdata_next[31:0] = classc_phase0_cyc_shadowed_qs;
Tests: T1 T2 T3
19294 end
19295
19296 addr_hit[331]: begin
19297 1/1 reg_rdata_next[31:0] = classc_phase1_cyc_shadowed_qs;
Tests: T1 T2 T10
19298 end
19299
19300 addr_hit[332]: begin
19301 1/1 reg_rdata_next[31:0] = classc_phase2_cyc_shadowed_qs;
Tests: T1 T2 T3
19302 end
19303
19304 addr_hit[333]: begin
19305 1/1 reg_rdata_next[31:0] = classc_phase3_cyc_shadowed_qs;
Tests: T1 T2 T3
19306 end
19307
19308 addr_hit[334]: begin
19309 1/1 reg_rdata_next[31:0] = classc_esc_cnt_qs;
Tests: T1 T2 T3
19310 end
19311
19312 addr_hit[335]: begin
19313 1/1 reg_rdata_next[2:0] = classc_state_qs;
Tests: T1 T2 T3
19314 end
19315
19316 addr_hit[336]: begin
19317 1/1 reg_rdata_next[0] = classd_regwen_qs;
Tests: T1 T2 T10
19318 end
19319
19320 addr_hit[337]: begin
19321 1/1 reg_rdata_next[0] = classd_ctrl_shadowed_en_qs;
Tests: T1 T2 T3
19322 1/1 reg_rdata_next[1] = classd_ctrl_shadowed_lock_qs;
Tests: T1 T2 T3
19323 1/1 reg_rdata_next[2] = classd_ctrl_shadowed_en_e0_qs;
Tests: T1 T2 T3
19324 1/1 reg_rdata_next[3] = classd_ctrl_shadowed_en_e1_qs;
Tests: T1 T2 T3
19325 1/1 reg_rdata_next[4] = classd_ctrl_shadowed_en_e2_qs;
Tests: T1 T2 T3
19326 1/1 reg_rdata_next[5] = classd_ctrl_shadowed_en_e3_qs;
Tests: T1 T2 T3
19327 1/1 reg_rdata_next[7:6] = classd_ctrl_shadowed_map_e0_qs;
Tests: T1 T2 T3
19328 1/1 reg_rdata_next[9:8] = classd_ctrl_shadowed_map_e1_qs;
Tests: T1 T2 T3
19329 1/1 reg_rdata_next[11:10] = classd_ctrl_shadowed_map_e2_qs;
Tests: T1 T2 T3
19330 1/1 reg_rdata_next[13:12] = classd_ctrl_shadowed_map_e3_qs;
Tests: T1 T2 T3
19331 end
19332
19333 addr_hit[338]: begin
19334 1/1 reg_rdata_next[0] = classd_clr_regwen_qs;
Tests: T1 T2 T10
19335 end
19336
19337 addr_hit[339]: begin
19338 1/1 reg_rdata_next[0] = classd_clr_shadowed_qs;
Tests: T1 T2 T10
19339 end
19340
19341 addr_hit[340]: begin
19342 1/1 reg_rdata_next[15:0] = classd_accum_cnt_qs;
Tests: T1 T2 T3
19343 end
19344
19345 addr_hit[341]: begin
19346 1/1 reg_rdata_next[15:0] = classd_accum_thresh_shadowed_qs;
Tests: T1 T2 T3
19347 end
19348
19349 addr_hit[342]: begin
19350 1/1 reg_rdata_next[31:0] = classd_timeout_cyc_shadowed_qs;
Tests: T1 T2 T3
19351 end
19352
19353 addr_hit[343]: begin
19354 1/1 reg_rdata_next[1:0] = classd_crashdump_trigger_shadowed_qs;
Tests: T1 T2 T3
19355 end
19356
19357 addr_hit[344]: begin
19358 1/1 reg_rdata_next[31:0] = classd_phase0_cyc_shadowed_qs;
Tests: T1 T2 T10
19359 end
19360
19361 addr_hit[345]: begin
19362 1/1 reg_rdata_next[31:0] = classd_phase1_cyc_shadowed_qs;
Tests: T1 T2 T10
19363 end
19364
19365 addr_hit[346]: begin
19366 1/1 reg_rdata_next[31:0] = classd_phase2_cyc_shadowed_qs;
Tests: T1 T2 T10
19367 end
19368
19369 addr_hit[347]: begin
19370 1/1 reg_rdata_next[31:0] = classd_phase3_cyc_shadowed_qs;
Tests: T1 T2 T10
19371 end
19372
19373 addr_hit[348]: begin
19374 1/1 reg_rdata_next[31:0] = classd_esc_cnt_qs;
Tests: T1 T2 T10
19375 end
19376
19377 addr_hit[349]: begin
19378 1/1 reg_rdata_next[2:0] = classd_state_qs;
Tests: T1 T2 T3
19379 end
19380
19381 default: begin
19382 reg_rdata_next = '1;
19383 end
19384 endcase
19385 end
19386
19387 // shadow busy
19388 logic shadow_busy;
19389 logic rst_done;
19390 logic shadow_rst_done;
19391 always_ff @(posedge clk_i or negedge rst_ni) begin
19392 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
19393 1/1 rst_done <= '0;
Tests: T1 T2 T3
19394 end else begin
19395 1/1 rst_done <= 1'b1;
Tests: T1 T2 T3
19396 end
19397 end
19398
19399 always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
19400 1/1 if (!rst_shadowed_ni) begin
Tests: T1 T2 T3
19401 1/1 shadow_rst_done <= '0;
Tests: T1 T2 T3
19402 end else begin
19403 1/1 shadow_rst_done <= 1'b1;
Tests: T1 T2 T3
19404 end
19405 end
19406
19407 // both shadow and normal resets have been released
19408 1/1 assign shadow_busy = ~(rst_done & shadow_rst_done);
Tests: T1 T2 T3
19409
19410 // Collect up storage and update errors
19411 1/1 assign shadowed_storage_err_o = |{
Tests: T1 T2 T3
19412 ping_timeout_cyc_shadowed_storage_err,
19413 ping_timer_en_shadowed_storage_err,
19414 alert_en_shadowed_0_storage_err,
19415 alert_en_shadowed_1_storage_err,
19416 alert_en_shadowed_2_storage_err,
19417 alert_en_shadowed_3_storage_err,
19418 alert_en_shadowed_4_storage_err,
19419 alert_en_shadowed_5_storage_err,
19420 alert_en_shadowed_6_storage_err,
19421 alert_en_shadowed_7_storage_err,
19422 alert_en_shadowed_8_storage_err,
19423 alert_en_shadowed_9_storage_err,
19424 alert_en_shadowed_10_storage_err,
19425 alert_en_shadowed_11_storage_err,
19426 alert_en_shadowed_12_storage_err,
19427 alert_en_shadowed_13_storage_err,
19428 alert_en_shadowed_14_storage_err,
19429 alert_en_shadowed_15_storage_err,
19430 alert_en_shadowed_16_storage_err,
19431 alert_en_shadowed_17_storage_err,
19432 alert_en_shadowed_18_storage_err,
19433 alert_en_shadowed_19_storage_err,
19434 alert_en_shadowed_20_storage_err,
19435 alert_en_shadowed_21_storage_err,
19436 alert_en_shadowed_22_storage_err,
19437 alert_en_shadowed_23_storage_err,
19438 alert_en_shadowed_24_storage_err,
19439 alert_en_shadowed_25_storage_err,
19440 alert_en_shadowed_26_storage_err,
19441 alert_en_shadowed_27_storage_err,
19442 alert_en_shadowed_28_storage_err,
19443 alert_en_shadowed_29_storage_err,
19444 alert_en_shadowed_30_storage_err,
19445 alert_en_shadowed_31_storage_err,
19446 alert_en_shadowed_32_storage_err,
19447 alert_en_shadowed_33_storage_err,
19448 alert_en_shadowed_34_storage_err,
19449 alert_en_shadowed_35_storage_err,
19450 alert_en_shadowed_36_storage_err,
19451 alert_en_shadowed_37_storage_err,
19452 alert_en_shadowed_38_storage_err,
19453 alert_en_shadowed_39_storage_err,
19454 alert_en_shadowed_40_storage_err,
19455 alert_en_shadowed_41_storage_err,
19456 alert_en_shadowed_42_storage_err,
19457 alert_en_shadowed_43_storage_err,
19458 alert_en_shadowed_44_storage_err,
19459 alert_en_shadowed_45_storage_err,
19460 alert_en_shadowed_46_storage_err,
19461 alert_en_shadowed_47_storage_err,
19462 alert_en_shadowed_48_storage_err,
19463 alert_en_shadowed_49_storage_err,
19464 alert_en_shadowed_50_storage_err,
19465 alert_en_shadowed_51_storage_err,
19466 alert_en_shadowed_52_storage_err,
19467 alert_en_shadowed_53_storage_err,
19468 alert_en_shadowed_54_storage_err,
19469 alert_en_shadowed_55_storage_err,
19470 alert_en_shadowed_56_storage_err,
19471 alert_en_shadowed_57_storage_err,
19472 alert_en_shadowed_58_storage_err,
19473 alert_en_shadowed_59_storage_err,
19474 alert_en_shadowed_60_storage_err,
19475 alert_en_shadowed_61_storage_err,
19476 alert_en_shadowed_62_storage_err,
19477 alert_en_shadowed_63_storage_err,
19478 alert_en_shadowed_64_storage_err,
19479 alert_class_shadowed_0_storage_err,
19480 alert_class_shadowed_1_storage_err,
19481 alert_class_shadowed_2_storage_err,
19482 alert_class_shadowed_3_storage_err,
19483 alert_class_shadowed_4_storage_err,
19484 alert_class_shadowed_5_storage_err,
19485 alert_class_shadowed_6_storage_err,
19486 alert_class_shadowed_7_storage_err,
19487 alert_class_shadowed_8_storage_err,
19488 alert_class_shadowed_9_storage_err,
19489 alert_class_shadowed_10_storage_err,
19490 alert_class_shadowed_11_storage_err,
19491 alert_class_shadowed_12_storage_err,
19492 alert_class_shadowed_13_storage_err,
19493 alert_class_shadowed_14_storage_err,
19494 alert_class_shadowed_15_storage_err,
19495 alert_class_shadowed_16_storage_err,
19496 alert_class_shadowed_17_storage_err,
19497 alert_class_shadowed_18_storage_err,
19498 alert_class_shadowed_19_storage_err,
19499 alert_class_shadowed_20_storage_err,
19500 alert_class_shadowed_21_storage_err,
19501 alert_class_shadowed_22_storage_err,
19502 alert_class_shadowed_23_storage_err,
19503 alert_class_shadowed_24_storage_err,
19504 alert_class_shadowed_25_storage_err,
19505 alert_class_shadowed_26_storage_err,
19506 alert_class_shadowed_27_storage_err,
19507 alert_class_shadowed_28_storage_err,
19508 alert_class_shadowed_29_storage_err,
19509 alert_class_shadowed_30_storage_err,
19510 alert_class_shadowed_31_storage_err,
19511 alert_class_shadowed_32_storage_err,
19512 alert_class_shadowed_33_storage_err,
19513 alert_class_shadowed_34_storage_err,
19514 alert_class_shadowed_35_storage_err,
19515 alert_class_shadowed_36_storage_err,
19516 alert_class_shadowed_37_storage_err,
19517 alert_class_shadowed_38_storage_err,
19518 alert_class_shadowed_39_storage_err,
19519 alert_class_shadowed_40_storage_err,
19520 alert_class_shadowed_41_storage_err,
19521 alert_class_shadowed_42_storage_err,
19522 alert_class_shadowed_43_storage_err,
19523 alert_class_shadowed_44_storage_err,
19524 alert_class_shadowed_45_storage_err,
19525 alert_class_shadowed_46_storage_err,
19526 alert_class_shadowed_47_storage_err,
19527 alert_class_shadowed_48_storage_err,
19528 alert_class_shadowed_49_storage_err,
19529 alert_class_shadowed_50_storage_err,
19530 alert_class_shadowed_51_storage_err,
19531 alert_class_shadowed_52_storage_err,
19532 alert_class_shadowed_53_storage_err,
19533 alert_class_shadowed_54_storage_err,
19534 alert_class_shadowed_55_storage_err,
19535 alert_class_shadowed_56_storage_err,
19536 alert_class_shadowed_57_storage_err,
19537 alert_class_shadowed_58_storage_err,
19538 alert_class_shadowed_59_storage_err,
19539 alert_class_shadowed_60_storage_err,
19540 alert_class_shadowed_61_storage_err,
19541 alert_class_shadowed_62_storage_err,
19542 alert_class_shadowed_63_storage_err,
19543 alert_class_shadowed_64_storage_err,
19544 loc_alert_en_shadowed_0_storage_err,
19545 loc_alert_en_shadowed_1_storage_err,
19546 loc_alert_en_shadowed_2_storage_err,
19547 loc_alert_en_shadowed_3_storage_err,
19548 loc_alert_en_shadowed_4_storage_err,
19549 loc_alert_en_shadowed_5_storage_err,
19550 loc_alert_en_shadowed_6_storage_err,
19551 loc_alert_class_shadowed_0_storage_err,
19552 loc_alert_class_shadowed_1_storage_err,
19553 loc_alert_class_shadowed_2_storage_err,
19554 loc_alert_class_shadowed_3_storage_err,
19555 loc_alert_class_shadowed_4_storage_err,
19556 loc_alert_class_shadowed_5_storage_err,
19557 loc_alert_class_shadowed_6_storage_err,
19558 classa_ctrl_shadowed_en_storage_err,
19559 classa_ctrl_shadowed_lock_storage_err,
19560 classa_ctrl_shadowed_en_e0_storage_err,
19561 classa_ctrl_shadowed_en_e1_storage_err,
19562 classa_ctrl_shadowed_en_e2_storage_err,
19563 classa_ctrl_shadowed_en_e3_storage_err,
19564 classa_ctrl_shadowed_map_e0_storage_err,
19565 classa_ctrl_shadowed_map_e1_storage_err,
19566 classa_ctrl_shadowed_map_e2_storage_err,
19567 classa_ctrl_shadowed_map_e3_storage_err,
19568 classa_clr_shadowed_storage_err,
19569 classa_accum_thresh_shadowed_storage_err,
19570 classa_timeout_cyc_shadowed_storage_err,
19571 classa_crashdump_trigger_shadowed_storage_err,
19572 classa_phase0_cyc_shadowed_storage_err,
19573 classa_phase1_cyc_shadowed_storage_err,
19574 classa_phase2_cyc_shadowed_storage_err,
19575 classa_phase3_cyc_shadowed_storage_err,
19576 classb_ctrl_shadowed_en_storage_err,
19577 classb_ctrl_shadowed_lock_storage_err,
19578 classb_ctrl_shadowed_en_e0_storage_err,
19579 classb_ctrl_shadowed_en_e1_storage_err,
19580 classb_ctrl_shadowed_en_e2_storage_err,
19581 classb_ctrl_shadowed_en_e3_storage_err,
19582 classb_ctrl_shadowed_map_e0_storage_err,
19583 classb_ctrl_shadowed_map_e1_storage_err,
19584 classb_ctrl_shadowed_map_e2_storage_err,
19585 classb_ctrl_shadowed_map_e3_storage_err,
19586 classb_clr_shadowed_storage_err,
19587 classb_accum_thresh_shadowed_storage_err,
19588 classb_timeout_cyc_shadowed_storage_err,
19589 classb_crashdump_trigger_shadowed_storage_err,
19590 classb_phase0_cyc_shadowed_storage_err,
19591 classb_phase1_cyc_shadowed_storage_err,
19592 classb_phase2_cyc_shadowed_storage_err,
19593 classb_phase3_cyc_shadowed_storage_err,
19594 classc_ctrl_shadowed_en_storage_err,
19595 classc_ctrl_shadowed_lock_storage_err,
19596 classc_ctrl_shadowed_en_e0_storage_err,
19597 classc_ctrl_shadowed_en_e1_storage_err,
19598 classc_ctrl_shadowed_en_e2_storage_err,
19599 classc_ctrl_shadowed_en_e3_storage_err,
19600 classc_ctrl_shadowed_map_e0_storage_err,
19601 classc_ctrl_shadowed_map_e1_storage_err,
19602 classc_ctrl_shadowed_map_e2_storage_err,
19603 classc_ctrl_shadowed_map_e3_storage_err,
19604 classc_clr_shadowed_storage_err,
19605 classc_accum_thresh_shadowed_storage_err,
19606 classc_timeout_cyc_shadowed_storage_err,
19607 classc_crashdump_trigger_shadowed_storage_err,
19608 classc_phase0_cyc_shadowed_storage_err,
19609 classc_phase1_cyc_shadowed_storage_err,
19610 classc_phase2_cyc_shadowed_storage_err,
19611 classc_phase3_cyc_shadowed_storage_err,
19612 classd_ctrl_shadowed_en_storage_err,
19613 classd_ctrl_shadowed_lock_storage_err,
19614 classd_ctrl_shadowed_en_e0_storage_err,
19615 classd_ctrl_shadowed_en_e1_storage_err,
19616 classd_ctrl_shadowed_en_e2_storage_err,
19617 classd_ctrl_shadowed_en_e3_storage_err,
19618 classd_ctrl_shadowed_map_e0_storage_err,
19619 classd_ctrl_shadowed_map_e1_storage_err,
19620 classd_ctrl_shadowed_map_e2_storage_err,
19621 classd_ctrl_shadowed_map_e3_storage_err,
19622 classd_clr_shadowed_storage_err,
19623 classd_accum_thresh_shadowed_storage_err,
19624 classd_timeout_cyc_shadowed_storage_err,
19625 classd_crashdump_trigger_shadowed_storage_err,
19626 classd_phase0_cyc_shadowed_storage_err,
19627 classd_phase1_cyc_shadowed_storage_err,
19628 classd_phase2_cyc_shadowed_storage_err,
19629 classd_phase3_cyc_shadowed_storage_err
19630 };
19631 1/1 assign shadowed_update_err_o = |{
Tests: T1 T2 T3
19632 ping_timeout_cyc_shadowed_update_err,
19633 ping_timer_en_shadowed_update_err,
19634 alert_en_shadowed_0_update_err,
19635 alert_en_shadowed_1_update_err,
19636 alert_en_shadowed_2_update_err,
19637 alert_en_shadowed_3_update_err,
19638 alert_en_shadowed_4_update_err,
19639 alert_en_shadowed_5_update_err,
19640 alert_en_shadowed_6_update_err,
19641 alert_en_shadowed_7_update_err,
19642 alert_en_shadowed_8_update_err,
19643 alert_en_shadowed_9_update_err,
19644 alert_en_shadowed_10_update_err,
19645 alert_en_shadowed_11_update_err,
19646 alert_en_shadowed_12_update_err,
19647 alert_en_shadowed_13_update_err,
19648 alert_en_shadowed_14_update_err,
19649 alert_en_shadowed_15_update_err,
19650 alert_en_shadowed_16_update_err,
19651 alert_en_shadowed_17_update_err,
19652 alert_en_shadowed_18_update_err,
19653 alert_en_shadowed_19_update_err,
19654 alert_en_shadowed_20_update_err,
19655 alert_en_shadowed_21_update_err,
19656 alert_en_shadowed_22_update_err,
19657 alert_en_shadowed_23_update_err,
19658 alert_en_shadowed_24_update_err,
19659 alert_en_shadowed_25_update_err,
19660 alert_en_shadowed_26_update_err,
19661 alert_en_shadowed_27_update_err,
19662 alert_en_shadowed_28_update_err,
19663 alert_en_shadowed_29_update_err,
19664 alert_en_shadowed_30_update_err,
19665 alert_en_shadowed_31_update_err,
19666 alert_en_shadowed_32_update_err,
19667 alert_en_shadowed_33_update_err,
19668 alert_en_shadowed_34_update_err,
19669 alert_en_shadowed_35_update_err,
19670 alert_en_shadowed_36_update_err,
19671 alert_en_shadowed_37_update_err,
19672 alert_en_shadowed_38_update_err,
19673 alert_en_shadowed_39_update_err,
19674 alert_en_shadowed_40_update_err,
19675 alert_en_shadowed_41_update_err,
19676 alert_en_shadowed_42_update_err,
19677 alert_en_shadowed_43_update_err,
19678 alert_en_shadowed_44_update_err,
19679 alert_en_shadowed_45_update_err,
19680 alert_en_shadowed_46_update_err,
19681 alert_en_shadowed_47_update_err,
19682 alert_en_shadowed_48_update_err,
19683 alert_en_shadowed_49_update_err,
19684 alert_en_shadowed_50_update_err,
19685 alert_en_shadowed_51_update_err,
19686 alert_en_shadowed_52_update_err,
19687 alert_en_shadowed_53_update_err,
19688 alert_en_shadowed_54_update_err,
19689 alert_en_shadowed_55_update_err,
19690 alert_en_shadowed_56_update_err,
19691 alert_en_shadowed_57_update_err,
19692 alert_en_shadowed_58_update_err,
19693 alert_en_shadowed_59_update_err,
19694 alert_en_shadowed_60_update_err,
19695 alert_en_shadowed_61_update_err,
19696 alert_en_shadowed_62_update_err,
19697 alert_en_shadowed_63_update_err,
19698 alert_en_shadowed_64_update_err,
19699 alert_class_shadowed_0_update_err,
19700 alert_class_shadowed_1_update_err,
19701 alert_class_shadowed_2_update_err,
19702 alert_class_shadowed_3_update_err,
19703 alert_class_shadowed_4_update_err,
19704 alert_class_shadowed_5_update_err,
19705 alert_class_shadowed_6_update_err,
19706 alert_class_shadowed_7_update_err,
19707 alert_class_shadowed_8_update_err,
19708 alert_class_shadowed_9_update_err,
19709 alert_class_shadowed_10_update_err,
19710 alert_class_shadowed_11_update_err,
19711 alert_class_shadowed_12_update_err,
19712 alert_class_shadowed_13_update_err,
19713 alert_class_shadowed_14_update_err,
19714 alert_class_shadowed_15_update_err,
19715 alert_class_shadowed_16_update_err,
19716 alert_class_shadowed_17_update_err,
19717 alert_class_shadowed_18_update_err,
19718 alert_class_shadowed_19_update_err,
19719 alert_class_shadowed_20_update_err,
19720 alert_class_shadowed_21_update_err,
19721 alert_class_shadowed_22_update_err,
19722 alert_class_shadowed_23_update_err,
19723 alert_class_shadowed_24_update_err,
19724 alert_class_shadowed_25_update_err,
19725 alert_class_shadowed_26_update_err,
19726 alert_class_shadowed_27_update_err,
19727 alert_class_shadowed_28_update_err,
19728 alert_class_shadowed_29_update_err,
19729 alert_class_shadowed_30_update_err,
19730 alert_class_shadowed_31_update_err,
19731 alert_class_shadowed_32_update_err,
19732 alert_class_shadowed_33_update_err,
19733 alert_class_shadowed_34_update_err,
19734 alert_class_shadowed_35_update_err,
19735 alert_class_shadowed_36_update_err,
19736 alert_class_shadowed_37_update_err,
19737 alert_class_shadowed_38_update_err,
19738 alert_class_shadowed_39_update_err,
19739 alert_class_shadowed_40_update_err,
19740 alert_class_shadowed_41_update_err,
19741 alert_class_shadowed_42_update_err,
19742 alert_class_shadowed_43_update_err,
19743 alert_class_shadowed_44_update_err,
19744 alert_class_shadowed_45_update_err,
19745 alert_class_shadowed_46_update_err,
19746 alert_class_shadowed_47_update_err,
19747 alert_class_shadowed_48_update_err,
19748 alert_class_shadowed_49_update_err,
19749 alert_class_shadowed_50_update_err,
19750 alert_class_shadowed_51_update_err,
19751 alert_class_shadowed_52_update_err,
19752 alert_class_shadowed_53_update_err,
19753 alert_class_shadowed_54_update_err,
19754 alert_class_shadowed_55_update_err,
19755 alert_class_shadowed_56_update_err,
19756 alert_class_shadowed_57_update_err,
19757 alert_class_shadowed_58_update_err,
19758 alert_class_shadowed_59_update_err,
19759 alert_class_shadowed_60_update_err,
19760 alert_class_shadowed_61_update_err,
19761 alert_class_shadowed_62_update_err,
19762 alert_class_shadowed_63_update_err,
19763 alert_class_shadowed_64_update_err,
19764 loc_alert_en_shadowed_0_update_err,
19765 loc_alert_en_shadowed_1_update_err,
19766 loc_alert_en_shadowed_2_update_err,
19767 loc_alert_en_shadowed_3_update_err,
19768 loc_alert_en_shadowed_4_update_err,
19769 loc_alert_en_shadowed_5_update_err,
19770 loc_alert_en_shadowed_6_update_err,
19771 loc_alert_class_shadowed_0_update_err,
19772 loc_alert_class_shadowed_1_update_err,
19773 loc_alert_class_shadowed_2_update_err,
19774 loc_alert_class_shadowed_3_update_err,
19775 loc_alert_class_shadowed_4_update_err,
19776 loc_alert_class_shadowed_5_update_err,
19777 loc_alert_class_shadowed_6_update_err,
19778 classa_ctrl_shadowed_en_update_err,
19779 classa_ctrl_shadowed_lock_update_err,
19780 classa_ctrl_shadowed_en_e0_update_err,
19781 classa_ctrl_shadowed_en_e1_update_err,
19782 classa_ctrl_shadowed_en_e2_update_err,
19783 classa_ctrl_shadowed_en_e3_update_err,
19784 classa_ctrl_shadowed_map_e0_update_err,
19785 classa_ctrl_shadowed_map_e1_update_err,
19786 classa_ctrl_shadowed_map_e2_update_err,
19787 classa_ctrl_shadowed_map_e3_update_err,
19788 classa_clr_shadowed_update_err,
19789 classa_accum_thresh_shadowed_update_err,
19790 classa_timeout_cyc_shadowed_update_err,
19791 classa_crashdump_trigger_shadowed_update_err,
19792 classa_phase0_cyc_shadowed_update_err,
19793 classa_phase1_cyc_shadowed_update_err,
19794 classa_phase2_cyc_shadowed_update_err,
19795 classa_phase3_cyc_shadowed_update_err,
19796 classb_ctrl_shadowed_en_update_err,
19797 classb_ctrl_shadowed_lock_update_err,
19798 classb_ctrl_shadowed_en_e0_update_err,
19799 classb_ctrl_shadowed_en_e1_update_err,
19800 classb_ctrl_shadowed_en_e2_update_err,
19801 classb_ctrl_shadowed_en_e3_update_err,
19802 classb_ctrl_shadowed_map_e0_update_err,
19803 classb_ctrl_shadowed_map_e1_update_err,
19804 classb_ctrl_shadowed_map_e2_update_err,
19805 classb_ctrl_shadowed_map_e3_update_err,
19806 classb_clr_shadowed_update_err,
19807 classb_accum_thresh_shadowed_update_err,
19808 classb_timeout_cyc_shadowed_update_err,
19809 classb_crashdump_trigger_shadowed_update_err,
19810 classb_phase0_cyc_shadowed_update_err,
19811 classb_phase1_cyc_shadowed_update_err,
19812 classb_phase2_cyc_shadowed_update_err,
19813 classb_phase3_cyc_shadowed_update_err,
19814 classc_ctrl_shadowed_en_update_err,
19815 classc_ctrl_shadowed_lock_update_err,
19816 classc_ctrl_shadowed_en_e0_update_err,
19817 classc_ctrl_shadowed_en_e1_update_err,
19818 classc_ctrl_shadowed_en_e2_update_err,
19819 classc_ctrl_shadowed_en_e3_update_err,
19820 classc_ctrl_shadowed_map_e0_update_err,
19821 classc_ctrl_shadowed_map_e1_update_err,
19822 classc_ctrl_shadowed_map_e2_update_err,
19823 classc_ctrl_shadowed_map_e3_update_err,
19824 classc_clr_shadowed_update_err,
19825 classc_accum_thresh_shadowed_update_err,
19826 classc_timeout_cyc_shadowed_update_err,
19827 classc_crashdump_trigger_shadowed_update_err,
19828 classc_phase0_cyc_shadowed_update_err,
19829 classc_phase1_cyc_shadowed_update_err,
19830 classc_phase2_cyc_shadowed_update_err,
19831 classc_phase3_cyc_shadowed_update_err,
19832 classd_ctrl_shadowed_en_update_err,
19833 classd_ctrl_shadowed_lock_update_err,
19834 classd_ctrl_shadowed_en_e0_update_err,
19835 classd_ctrl_shadowed_en_e1_update_err,
19836 classd_ctrl_shadowed_en_e2_update_err,
19837 classd_ctrl_shadowed_en_e3_update_err,
19838 classd_ctrl_shadowed_map_e0_update_err,
19839 classd_ctrl_shadowed_map_e1_update_err,
19840 classd_ctrl_shadowed_map_e2_update_err,
19841 classd_ctrl_shadowed_map_e3_update_err,
19842 classd_clr_shadowed_update_err,
19843 classd_accum_thresh_shadowed_update_err,
19844 classd_timeout_cyc_shadowed_update_err,
19845 classd_crashdump_trigger_shadowed_update_err,
19846 classd_phase0_cyc_shadowed_update_err,
19847 classd_phase1_cyc_shadowed_update_err,
19848 classd_phase2_cyc_shadowed_update_err,
19849 classd_phase3_cyc_shadowed_update_err
19850 };
19851
19852 // register busy
19853 1/1 assign reg_busy = shadow_busy;
Tests: T1 T2 T3
19854
19855 // Unused signal tieoff
19856
19857 // wdata / byte enable are not always fully used
19858 // add a blanket unused statement to handle lint waivers
19859 logic unused_wdata;
19860 logic unused_be;
19861 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
19862 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3