| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.23 | 99.99 | 98.74 | 97.09 | 100.00 | 100.00 | 99.38 | 99.40 |
| T779 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3746514804 | Oct 09 06:08:54 PM UTC 24 | Oct 09 06:09:05 PM UTC 24 | 1039239377 ps | ||
| T780 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1580828640 | Oct 09 05:59:52 PM UTC 24 | Oct 09 06:09:19 PM UTC 24 | 25185958046 ps | ||
| T781 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.278402279 | Oct 09 06:09:06 PM UTC 24 | Oct 09 06:09:22 PM UTC 24 | 798005752 ps | ||
| T782 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.2720841579 | Oct 09 06:09:23 PM UTC 24 | Oct 09 06:09:26 PM UTC 24 | 9582117 ps | ||
| T783 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.466332752 | Oct 09 06:08:51 PM UTC 24 | Oct 09 06:09:28 PM UTC 24 | 1424870412 ps | ||
| T784 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3749664350 | Oct 09 06:09:28 PM UTC 24 | Oct 09 06:09:36 PM UTC 24 | 116361123 ps | ||
| T785 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.906447634 | Oct 09 06:09:30 PM UTC 24 | Oct 09 06:09:37 PM UTC 24 | 64060938 ps | ||
| T181 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2229880633 | Oct 09 06:04:07 PM UTC 24 | Oct 09 06:09:58 PM UTC 24 | 15492463866 ps | ||
| T225 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1946927308 | Oct 09 06:08:43 PM UTC 24 | Oct 09 06:09:59 PM UTC 24 | 892720832 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1273945478 | Oct 09 06:03:46 PM UTC 24 | Oct 09 06:10:02 PM UTC 24 | 16985115556 ps | ||
| T217 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4200765358 | Oct 09 06:09:20 PM UTC 24 | Oct 09 06:10:03 PM UTC 24 | 516636155 ps | ||
| T221 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.30441418 | Oct 09 06:10:00 PM UTC 24 | Oct 09 06:10:04 PM UTC 24 | 65228997 ps | ||
| T786 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1161286268 | Oct 09 06:10:04 PM UTC 24 | Oct 09 06:10:07 PM UTC 24 | 20996641 ps | ||
| T787 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3549425533 | Oct 09 06:10:04 PM UTC 24 | Oct 09 06:10:10 PM UTC 24 | 25593750 ps | ||
| T788 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.645632762 | Oct 09 06:10:12 PM UTC 24 | Oct 09 06:10:15 PM UTC 24 | 34917791 ps | ||
| T789 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.777272877 | Oct 09 06:10:08 PM UTC 24 | Oct 09 06:10:18 PM UTC 24 | 35604886 ps | ||
| T790 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2485405821 | Oct 09 06:10:16 PM UTC 24 | Oct 09 06:10:20 PM UTC 24 | 8647098 ps | ||
| T791 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1012915042 | Oct 09 06:10:19 PM UTC 24 | Oct 09 06:10:22 PM UTC 24 | 10592601 ps | ||
| T792 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.879473955 | Oct 09 06:10:00 PM UTC 24 | Oct 09 06:10:24 PM UTC 24 | 366345781 ps | ||
| T793 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1898926231 | Oct 09 06:10:21 PM UTC 24 | Oct 09 06:10:25 PM UTC 24 | 23581112 ps | ||
| T794 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3361361041 | Oct 09 06:10:05 PM UTC 24 | Oct 09 06:10:25 PM UTC 24 | 91050801 ps | ||
| T795 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2604183724 | Oct 09 06:10:23 PM UTC 24 | Oct 09 06:10:27 PM UTC 24 | 11370327 ps | ||
| T796 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3469815114 | Oct 09 06:10:25 PM UTC 24 | Oct 09 06:10:28 PM UTC 24 | 9833937 ps | ||
| T797 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1901814114 | Oct 09 06:10:26 PM UTC 24 | Oct 09 06:10:29 PM UTC 24 | 25444156 ps | ||
| T798 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1269492830 | Oct 09 06:10:27 PM UTC 24 | Oct 09 06:10:30 PM UTC 24 | 12940639 ps | ||
| T799 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3409334217 | Oct 09 06:09:29 PM UTC 24 | Oct 09 06:10:30 PM UTC 24 | 537573006 ps | ||
| T800 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.929219363 | Oct 09 06:10:29 PM UTC 24 | Oct 09 06:10:32 PM UTC 24 | 13429717 ps | ||
| T801 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.859513578 | Oct 09 06:10:29 PM UTC 24 | Oct 09 06:10:32 PM UTC 24 | 10377321 ps | ||
| T802 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1551108129 | Oct 09 06:10:30 PM UTC 24 | Oct 09 06:10:33 PM UTC 24 | 12776134 ps | ||
| T803 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.3334369110 | Oct 09 06:10:32 PM UTC 24 | Oct 09 06:10:35 PM UTC 24 | 9839027 ps | ||
| T804 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.3643487778 | Oct 09 06:10:32 PM UTC 24 | Oct 09 06:10:35 PM UTC 24 | 12632408 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3106973793 | Oct 09 06:00:23 PM UTC 24 | Oct 09 06:10:36 PM UTC 24 | 6964481349 ps | ||
| T805 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.2417915796 | Oct 09 06:10:33 PM UTC 24 | Oct 09 06:10:37 PM UTC 24 | 8770349 ps | ||
| T806 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.741738092 | Oct 09 06:10:34 PM UTC 24 | Oct 09 06:10:37 PM UTC 24 | 8760520 ps | ||
| T807 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3366984430 | Oct 09 06:10:35 PM UTC 24 | Oct 09 06:10:38 PM UTC 24 | 9543399 ps | ||
| T808 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.1865024297 | Oct 09 06:10:36 PM UTC 24 | Oct 09 06:10:39 PM UTC 24 | 7128397 ps | ||
| T809 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.4239980345 | Oct 09 06:10:36 PM UTC 24 | Oct 09 06:10:39 PM UTC 24 | 7771906 ps | ||
| T810 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.981264268 | Oct 09 06:10:39 PM UTC 24 | Oct 09 06:10:41 PM UTC 24 | 9021484 ps | ||
| T811 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.381034230 | Oct 09 06:10:39 PM UTC 24 | Oct 09 06:10:42 PM UTC 24 | 9686095 ps | ||
| T812 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1275072558 | Oct 09 06:10:38 PM UTC 24 | Oct 09 06:10:42 PM UTC 24 | 10064923 ps | ||
| T813 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2482074809 | Oct 09 06:10:40 PM UTC 24 | Oct 09 06:10:43 PM UTC 24 | 15682425 ps | ||
| T814 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.4195595707 | Oct 09 06:10:40 PM UTC 24 | Oct 09 06:10:43 PM UTC 24 | 11536525 ps | ||
| T815 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2883634792 | Oct 09 05:56:33 PM UTC 24 | Oct 09 06:10:44 PM UTC 24 | 28476567419 ps | ||
| T816 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.4252017875 | Oct 09 06:10:43 PM UTC 24 | Oct 09 06:10:45 PM UTC 24 | 6874654 ps | ||
| T817 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.557173448 | Oct 09 06:10:39 PM UTC 24 | Oct 09 06:10:46 PM UTC 24 | 73990162 ps | ||
| T818 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.2564662296 | Oct 09 06:10:44 PM UTC 24 | Oct 09 06:10:47 PM UTC 24 | 15660670 ps | ||
| T819 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.637639126 | Oct 09 06:10:44 PM UTC 24 | Oct 09 06:10:47 PM UTC 24 | 6344577 ps | ||
| T820 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.445565286 | Oct 09 06:10:44 PM UTC 24 | Oct 09 06:10:48 PM UTC 24 | 41730763 ps | ||
| T821 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.1845407968 | Oct 09 06:10:44 PM UTC 24 | Oct 09 06:10:48 PM UTC 24 | 10192537 ps | ||
| T822 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2558027815 | Oct 09 06:10:46 PM UTC 24 | Oct 09 06:10:49 PM UTC 24 | 9097797 ps | ||
| T193 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.919013953 | Oct 09 06:07:51 PM UTC 24 | Oct 09 06:11:14 PM UTC 24 | 9714203551 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3812822732 | Oct 09 06:01:07 PM UTC 24 | Oct 09 06:11:23 PM UTC 24 | 41477844886 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.407340268 | Oct 09 06:06:45 PM UTC 24 | Oct 09 06:11:25 PM UTC 24 | 6092153354 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1558101104 | Oct 09 06:05:22 PM UTC 24 | Oct 09 06:11:48 PM UTC 24 | 4212033222 ps | ||
| T197 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.941340963 | Oct 09 06:06:18 PM UTC 24 | Oct 09 06:13:01 PM UTC 24 | 8689617858 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2839808033 | Oct 09 06:02:50 PM UTC 24 | Oct 09 06:13:13 PM UTC 24 | 22181305894 ps | ||
| T194 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1294786471 | Oct 09 06:02:45 PM UTC 24 | Oct 09 06:13:40 PM UTC 24 | 6334234768 ps | ||
| T195 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.448868385 | Oct 09 06:08:12 PM UTC 24 | Oct 09 06:13:48 PM UTC 24 | 62633231948 ps | ||
| T408 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3593378701 | Oct 09 06:07:49 PM UTC 24 | Oct 09 06:14:37 PM UTC 24 | 9897084390 ps | ||
| T201 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1864863567 | Oct 09 06:06:11 PM UTC 24 | Oct 09 06:14:38 PM UTC 24 | 12837474984 ps | ||
| T202 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3187039401 | Oct 09 06:05:17 PM UTC 24 | Oct 09 06:15:10 PM UTC 24 | 15175854715 ps | ||
| T198 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3491617111 | Oct 09 06:09:06 PM UTC 24 | Oct 09 06:15:43 PM UTC 24 | 5277277277 ps | ||
| T199 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2084055119 | Oct 09 06:09:37 PM UTC 24 | Oct 09 06:16:02 PM UTC 24 | 4102142204 ps | ||
| T409 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.584500818 | Oct 09 06:06:42 PM UTC 24 | Oct 09 06:16:44 PM UTC 24 | 12587274886 ps | ||
| T204 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1744695 | Oct 09 05:55:49 PM UTC 24 | Oct 09 06:19:18 PM UTC 24 | 47208817371 ps | ||
| T203 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3290812624 | Oct 09 06:09:37 PM UTC 24 | Oct 09 06:19:46 PM UTC 24 | 33696469172 ps | ||
| T207 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2957458981 | Oct 09 06:01:44 PM UTC 24 | Oct 09 06:20:02 PM UTC 24 | 76615099417 ps | ||
| T410 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3612573355 | Oct 09 06:08:10 PM UTC 24 | Oct 09 06:23:43 PM UTC 24 | 5851245302 ps | ||
| T200 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2161920286 | Oct 09 06:05:46 PM UTC 24 | Oct 09 06:24:07 PM UTC 24 | 52707160177 ps | ||
| T411 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.574739373 | Oct 09 06:04:37 PM UTC 24 | Oct 09 06:24:14 PM UTC 24 | 15291216328 ps | ||
| T206 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3513045726 | Oct 09 06:07:20 PM UTC 24 | Oct 09 06:25:00 PM UTC 24 | 12199768484 ps | ||
| T205 | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.325835089 | Oct 09 06:08:59 PM UTC 24 | Oct 09 06:27:32 PM UTC 24 | 70713617423 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_classes.2429044673 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1024658881 ps |
| CPU time | 31.33 seconds |
| Started | Oct 09 04:15:48 PM UTC 24 |
| Finished | Oct 09 04:16:20 PM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429044673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2429044673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all_with_rand_reset.4052477769 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1663667511 ps |
| CPU time | 199.11 seconds |
| Started | Oct 09 04:17:03 PM UTC 24 |
| Finished | Oct 09 04:20:25 PM UTC 24 |
| Peak memory | 277044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4052477769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.al ert_handler_stress_all_with_rand_reset.4052477769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_sec_cm.2451363428 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 830388503 ps |
| CPU time | 34.13 seconds |
| Started | Oct 09 04:17:05 PM UTC 24 |
| Finished | Oct 09 04:17:40 PM UTC 24 |
| Peak memory | 292660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451363428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2451363428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy_stress.942308695 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 191877432 ps |
| CPU time | 9.74 seconds |
| Started | Oct 09 04:16:29 PM UTC 24 |
| Finished | Oct 09 04:16:41 PM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942308695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.942308695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_classes.2693212672 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 105154877 ps |
| CPU time | 7.98 seconds |
| Started | Oct 09 04:17:12 PM UTC 24 |
| Finished | Oct 09 04:17:21 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693212672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2693212672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_rw.150054412 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 436052174 ps |
| CPU time | 10.45 seconds |
| Started | Oct 09 05:55:32 PM UTC 24 |
| Finished | Oct 09 05:55:44 PM UTC 24 |
| Peak memory | 250560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150054412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.150054412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all_with_rand_reset.446120755 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 6979962889 ps |
| CPU time | 428.75 seconds |
| Started | Oct 09 04:16:09 PM UTC 24 |
| Finished | Oct 09 04:23:23 PM UTC 24 |
| Peak memory | 279088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=446120755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.ale rt_handler_stress_all_with_rand_reset.446120755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy.2100497694 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 77794510009 ps |
| CPU time | 2688.76 seconds |
| Started | Oct 09 04:15:57 PM UTC 24 |
| Finished | Oct 09 05:01:16 PM UTC 24 |
| Peak memory | 299524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100497694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2100497694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4077216605 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8081190370 ps |
| CPU time | 263.74 seconds |
| Started | Oct 09 05:55:54 PM UTC 24 |
| Finished | Oct 09 06:00:22 PM UTC 24 |
| Peak memory | 277716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077216605 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.4077216605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg.2202425224 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 40500056425 ps |
| CPU time | 970.46 seconds |
| Started | Oct 09 04:38:39 PM UTC 24 |
| Finished | Oct 09 04:55:02 PM UTC 24 |
| Peak memory | 283068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202425224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2202425224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1594852109 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 334846341 ps |
| CPU time | 65.84 seconds |
| Started | Oct 09 05:59:37 PM UTC 24 |
| Finished | Oct 09 06:00:45 PM UTC 24 |
| Peak memory | 248784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594852109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1594852109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all_with_rand_reset.141252075 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4859528693 ps |
| CPU time | 217.56 seconds |
| Started | Oct 09 04:56:31 PM UTC 24 |
| Finished | Oct 09 05:00:12 PM UTC 24 |
| Peak memory | 277112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=141252075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.al ert_handler_stress_all_with_rand_reset.141252075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_entropy.836702040 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 13518015375 ps |
| CPU time | 1790.15 seconds |
| Started | Oct 09 04:55:42 PM UTC 24 |
| Finished | Oct 09 05:25:55 PM UTC 24 |
| Peak memory | 299444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836702040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.836702040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4052633520 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4649011811 ps |
| CPU time | 747.44 seconds |
| Started | Oct 09 05:55:10 PM UTC 24 |
| Finished | Oct 09 06:07:48 PM UTC 24 |
| Peak memory | 283792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052633520 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shado w_reg_errors_with_csr_rw.4052633520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_classes.1399418406 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 408850155 ps |
| CPU time | 35.66 seconds |
| Started | Oct 09 04:17:41 PM UTC 24 |
| Finished | Oct 09 04:18:18 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399418406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1399418406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_ping_timeout.2520090331 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 42171255735 ps |
| CPU time | 463.2 seconds |
| Started | Oct 09 04:22:13 PM UTC 24 |
| Finished | Oct 09 04:30:01 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520090331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2520090331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2166971110 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 6592703783 ps |
| CPU time | 340.69 seconds |
| Started | Oct 09 06:01:12 PM UTC 24 |
| Finished | Oct 09 06:06:58 PM UTC 24 |
| Peak memory | 277652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166971110 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.2166971110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all_with_rand_reset.1289394128 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 7899411026 ps |
| CPU time | 139.48 seconds |
| Started | Oct 09 04:21:27 PM UTC 24 |
| Finished | Oct 09 04:23:50 PM UTC 24 |
| Peak memory | 281132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1289394128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.al ert_handler_stress_all_with_rand_reset.1289394128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg_stub_clk.1032842414 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 22144184618 ps |
| CPU time | 1313.8 seconds |
| Started | Oct 09 04:18:54 PM UTC 24 |
| Finished | Oct 09 04:41:05 PM UTC 24 |
| Peak memory | 299444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032842414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1032842414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_stress_all.2133526522 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 31755983815 ps |
| CPU time | 2099.78 seconds |
| Started | Oct 09 04:18:59 PM UTC 24 |
| Finished | Oct 09 04:54:23 PM UTC 24 |
| Peak memory | 299436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133526522 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all.2133526522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_classes.82417580 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 384579982 ps |
| CPU time | 26.54 seconds |
| Started | Oct 09 04:16:16 PM UTC 24 |
| Finished | Oct 09 04:16:44 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82417580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.82417580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1472209911 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 7391682710 ps |
| CPU time | 314.64 seconds |
| Started | Oct 09 06:00:24 PM UTC 24 |
| Finished | Oct 09 06:05:44 PM UTC 24 |
| Peak memory | 277516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472209911 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.1472209911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_intr_test.2903444951 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 21325713 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 06:00:46 PM UTC 24 |
| Finished | Oct 09 06:00:49 PM UTC 24 |
| Peak memory | 248660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903444951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2903444951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg.2856052080 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 119189242562 ps |
| CPU time | 2305.99 seconds |
| Started | Oct 09 04:25:10 PM UTC 24 |
| Finished | Oct 09 05:04:05 PM UTC 24 |
| Peak memory | 283136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856052080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2856052080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3290812624 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 33696469172 ps |
| CPU time | 600.95 seconds |
| Started | Oct 09 06:09:37 PM UTC 24 |
| Finished | Oct 09 06:19:46 PM UTC 24 |
| Peak memory | 277508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290812624 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shad ow_reg_errors_with_csr_rw.3290812624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy.3331635876 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 29187305994 ps |
| CPU time | 789.48 seconds |
| Started | Oct 09 04:29:26 PM UTC 24 |
| Finished | Oct 09 04:42:46 PM UTC 24 |
| Peak memory | 276988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331635876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3331635876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_sig_int_fail.1705570026 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3375507690 ps |
| CPU time | 38.67 seconds |
| Started | Oct 09 04:16:47 PM UTC 24 |
| Finished | Oct 09 04:17:27 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705570026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1705570026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_ping_timeout.3744189117 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 12249232934 ps |
| CPU time | 450.91 seconds |
| Started | Oct 09 04:41:08 PM UTC 24 |
| Finished | Oct 09 04:48:45 PM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744189117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3744189117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg.2858744591 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 55544772441 ps |
| CPU time | 3307.64 seconds |
| Started | Oct 09 04:21:17 PM UTC 24 |
| Finished | Oct 09 05:17:01 PM UTC 24 |
| Peak memory | 299644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858744591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2858744591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.533736751 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 88104935143 ps |
| CPU time | 777.12 seconds |
| Started | Oct 09 05:52:44 PM UTC 24 |
| Finished | Oct 09 06:05:52 PM UTC 24 |
| Peak memory | 283656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533736751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow _reg_errors_with_csr_rw.533736751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all_with_rand_reset.1319379096 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4813336827 ps |
| CPU time | 291.83 seconds |
| Started | Oct 09 04:22:51 PM UTC 24 |
| Finished | Oct 09 04:27:47 PM UTC 24 |
| Peak memory | 279084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1319379096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.al ert_handler_stress_all_with_rand_reset.1319379096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_ping_timeout.3490768143 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 55571413491 ps |
| CPU time | 654.46 seconds |
| Started | Oct 09 04:23:30 PM UTC 24 |
| Finished | Oct 09 04:34:33 PM UTC 24 |
| Peak memory | 260608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490768143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3490768143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.444186887 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 4463353463 ps |
| CPU time | 368.61 seconds |
| Started | Oct 09 05:55:14 PM UTC 24 |
| Finished | Oct 09 06:01:28 PM UTC 24 |
| Peak memory | 281604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444186887 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.444186887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg.3646949196 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 273507417132 ps |
| CPU time | 1523.56 seconds |
| Started | Oct 09 04:17:23 PM UTC 24 |
| Finished | Oct 09 04:43:05 PM UTC 24 |
| Peak memory | 281208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646949196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3646949196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_sig_int_fail.3697658715 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 2186557258 ps |
| CPU time | 48.35 seconds |
| Started | Oct 09 04:17:22 PM UTC 24 |
| Finished | Oct 09 04:18:12 PM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697658715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3697658715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.574739373 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 15291216328 ps |
| CPU time | 1161.79 seconds |
| Started | Oct 09 06:04:37 PM UTC 24 |
| Finished | Oct 09 06:24:14 PM UTC 24 |
| Peak memory | 277516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574739373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shado w_reg_errors_with_csr_rw.574739373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_ping_timeout.1863600574 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 12394412995 ps |
| CPU time | 567.32 seconds |
| Started | Oct 09 04:45:40 PM UTC 24 |
| Finished | Oct 09 04:55:15 PM UTC 24 |
| Peak memory | 260612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863600574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1863600574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1660225083 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2209729631 ps |
| CPU time | 179.67 seconds |
| Started | Oct 09 05:56:34 PM UTC 24 |
| Finished | Oct 09 05:59:37 PM UTC 24 |
| Peak memory | 250892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660225083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1660225083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_ping_timeout.1159246611 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 47121734190 ps |
| CPU time | 516.57 seconds |
| Started | Oct 09 05:09:31 PM UTC 24 |
| Finished | Oct 09 05:18:15 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159246611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1159246611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all_with_rand_reset.2922221186 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 56524352574 ps |
| CPU time | 542.41 seconds |
| Started | Oct 09 05:19:17 PM UTC 24 |
| Finished | Oct 09 05:28:27 PM UTC 24 |
| Peak memory | 295540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2922221186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.a lert_handler_stress_all_with_rand_reset.2922221186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg.251263295 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 34732284908 ps |
| CPU time | 1997.65 seconds |
| Started | Oct 09 05:31:33 PM UTC 24 |
| Finished | Oct 09 06:05:14 PM UTC 24 |
| Peak memory | 283264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251263295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.251263295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_ping_timeout.1173956130 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 11630262054 ps |
| CPU time | 371.62 seconds |
| Started | Oct 09 05:25:41 PM UTC 24 |
| Finished | Oct 09 05:31:57 PM UTC 24 |
| Peak memory | 266756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173956130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1173956130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all_with_rand_reset.2686802185 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2278035775 ps |
| CPU time | 136.36 seconds |
| Started | Oct 09 04:30:26 PM UTC 24 |
| Finished | Oct 09 04:32:45 PM UTC 24 |
| Peak memory | 281132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2686802185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.a lert_handler_stress_all_with_rand_reset.2686802185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2084055119 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4102142204 ps |
| CPU time | 379.02 seconds |
| Started | Oct 09 06:09:37 PM UTC 24 |
| Finished | Oct 09 06:16:02 PM UTC 24 |
| Peak memory | 277508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084055119 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.2084055119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_random_alerts.417066827 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 926460604 ps |
| CPU time | 67.08 seconds |
| Started | Oct 09 04:15:45 PM UTC 24 |
| Finished | Oct 09 04:16:54 PM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417066827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.417066827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg.2508491988 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 152675490034 ps |
| CPU time | 1322.25 seconds |
| Started | Oct 09 04:41:16 PM UTC 24 |
| Finished | Oct 09 05:03:35 PM UTC 24 |
| Peak memory | 283064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508491988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2508491988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all.1551604386 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 92114649872 ps |
| CPU time | 2483.74 seconds |
| Started | Oct 09 04:18:12 PM UTC 24 |
| Finished | Oct 09 05:00:05 PM UTC 24 |
| Peak memory | 309676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551604386 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all.1551604386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3513045726 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 12199768484 ps |
| CPU time | 1046.55 seconds |
| Started | Oct 09 06:07:20 PM UTC 24 |
| Finished | Oct 09 06:25:00 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513045726 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shad ow_reg_errors_with_csr_rw.3513045726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.448868385 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 62633231948 ps |
| CPU time | 330.99 seconds |
| Started | Oct 09 06:08:12 PM UTC 24 |
| Finished | Oct 09 06:13:48 PM UTC 24 |
| Peak memory | 283800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448868385 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.448868385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_sig_int_fail.3990997886 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3328895234 ps |
| CPU time | 73.54 seconds |
| Started | Oct 09 04:18:43 PM UTC 24 |
| Finished | Oct 09 04:19:59 PM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990997886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3990997886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_intr_test.956373764 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 9309078 ps |
| CPU time | 2.62 seconds |
| Started | Oct 09 06:05:29 PM UTC 24 |
| Finished | Oct 09 06:05:33 PM UTC 24 |
| Peak memory | 248452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956373764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.956373764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg.1972174148 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 127852975982 ps |
| CPU time | 2373.88 seconds |
| Started | Oct 09 04:59:10 PM UTC 24 |
| Finished | Oct 09 05:39:13 PM UTC 24 |
| Peak memory | 285696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972174148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1972174148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all.1056866975 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 139640769782 ps |
| CPU time | 4472.45 seconds |
| Started | Oct 09 05:47:14 PM UTC 24 |
| Finished | Oct 09 07:02:43 PM UTC 24 |
| Peak memory | 316328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056866975 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_stress_all.1056866975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all.2371162250 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 1276452762 ps |
| CPU time | 43.71 seconds |
| Started | Oct 09 04:28:01 PM UTC 24 |
| Finished | Oct 09 04:28:47 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371162250 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_stress_all.2371162250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_stress_all.1558311442 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 16512930138 ps |
| CPU time | 1613.05 seconds |
| Started | Oct 09 04:33:06 PM UTC 24 |
| Finished | Oct 09 05:00:19 PM UTC 24 |
| Peak memory | 299508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558311442 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_stress_all.1558311442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_stress_all.3698899455 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 151832090986 ps |
| CPU time | 2079.53 seconds |
| Started | Oct 09 04:35:43 PM UTC 24 |
| Finished | Oct 09 05:10:45 PM UTC 24 |
| Peak memory | 299436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698899455 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_stress_all.3698899455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_ping_timeout.3169068740 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 29961553984 ps |
| CPU time | 860.88 seconds |
| Started | Oct 09 04:54:02 PM UTC 24 |
| Finished | Oct 09 05:08:34 PM UTC 24 |
| Peak memory | 260740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169068740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3169068740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_sig_int_fail.1433579753 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 1142083792 ps |
| CPU time | 51.72 seconds |
| Started | Oct 09 04:58:37 PM UTC 24 |
| Finished | Oct 09 04:59:30 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433579753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1433579753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg.2900873392 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 42200754717 ps |
| CPU time | 2582.27 seconds |
| Started | Oct 09 05:11:32 PM UTC 24 |
| Finished | Oct 09 05:55:04 PM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900873392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2900873392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all_with_rand_reset.463033308 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4031263576 ps |
| CPU time | 343.64 seconds |
| Started | Oct 09 05:04:09 PM UTC 24 |
| Finished | Oct 09 05:09:58 PM UTC 24 |
| Peak memory | 277112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=463033308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.al ert_handler_stress_all_with_rand_reset.463033308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_intg_err.232967906 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 103053488 ps |
| CPU time | 5.51 seconds |
| Started | Oct 09 06:07:54 PM UTC 24 |
| Finished | Oct 09 06:08:01 PM UTC 24 |
| Peak memory | 248776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232967906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.232967906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.941340963 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 8689617858 ps |
| CPU time | 396.65 seconds |
| Started | Oct 09 06:06:18 PM UTC 24 |
| Finished | Oct 09 06:13:01 PM UTC 24 |
| Peak memory | 277848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941340963 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.941340963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_alert_accum_saturation.1531036937 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 169694066 ps |
| CPU time | 5.76 seconds |
| Started | Oct 09 04:16:09 PM UTC 24 |
| Finished | Oct 09 04:16:16 PM UTC 24 |
| Peak memory | 260736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531036937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1531036937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_alert_accum_saturation.3530944382 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 91313754 ps |
| CPU time | 6.37 seconds |
| Started | Oct 09 04:16:34 PM UTC 24 |
| Finished | Oct 09 04:16:41 PM UTC 24 |
| Peak memory | 260804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530944382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3530944382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_alert_accum_saturation.1782876184 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 17790501 ps |
| CPU time | 2.77 seconds |
| Started | Oct 09 04:25:23 PM UTC 24 |
| Finished | Oct 09 04:25:27 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782876184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1782876184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_alert_accum_saturation.2768531962 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 45010746 ps |
| CPU time | 6.1 seconds |
| Started | Oct 09 04:28:25 PM UTC 24 |
| Finished | Oct 09 04:28:33 PM UTC 24 |
| Peak memory | 260732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768531962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2768531962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg.4089802259 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 267542312967 ps |
| CPU time | 2323.25 seconds |
| Started | Oct 09 04:16:52 PM UTC 24 |
| Finished | Oct 09 04:56:04 PM UTC 24 |
| Peak memory | 293368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089802259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4089802259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_ping_timeout.3460388567 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 92722392282 ps |
| CPU time | 630.7 seconds |
| Started | Oct 09 04:17:22 PM UTC 24 |
| Finished | Oct 09 04:28:01 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460388567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3460388567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_intr_timeout.3170333953 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 971544584 ps |
| CPU time | 69.16 seconds |
| Started | Oct 09 04:17:46 PM UTC 24 |
| Finished | Oct 09 04:18:57 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170333953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3170333953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_stress_all.963917183 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 36823937397 ps |
| CPU time | 2381.12 seconds |
| Started | Oct 09 04:22:42 PM UTC 24 |
| Finished | Oct 09 05:02:52 PM UTC 24 |
| Peak memory | 295548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963917183 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all.963917183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_ping_timeout.1394005919 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 21884771067 ps |
| CPU time | 692.32 seconds |
| Started | Oct 09 05:13:30 PM UTC 24 |
| Finished | Oct 09 05:25:11 PM UTC 24 |
| Peak memory | 260612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394005919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1394005919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_sec_cm.498114222 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 1109443221 ps |
| CPU time | 74.73 seconds |
| Started | Oct 09 04:16:13 PM UTC 24 |
| Finished | Oct 09 04:17:30 PM UTC 24 |
| Peak memory | 294756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498114222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.498114222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3491617111 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 5277277277 ps |
| CPU time | 391.89 seconds |
| Started | Oct 09 06:09:06 PM UTC 24 |
| Finished | Oct 09 06:15:43 PM UTC 24 |
| Peak memory | 277584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491617111 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.3491617111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2477640645 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 302062832 ps |
| CPU time | 30.45 seconds |
| Started | Oct 09 06:04:56 PM UTC 24 |
| Finished | Oct 09 06:05:28 PM UTC 24 |
| Peak memory | 250556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477640645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2477640645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1864863567 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 12837474984 ps |
| CPU time | 499.58 seconds |
| Started | Oct 09 06:06:11 PM UTC 24 |
| Finished | Oct 09 06:14:38 PM UTC 24 |
| Peak memory | 281680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864863567 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shad ow_reg_errors_with_csr_rw.1864863567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_sig_int_fail.2757126574 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 670747310 ps |
| CPU time | 44.23 seconds |
| Started | Oct 09 04:19:52 PM UTC 24 |
| Finished | Oct 09 04:20:38 PM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757126574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2757126574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_intr_test.2560112368 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7610233 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 05:55:26 PM UTC 24 |
| Finished | Oct 09 05:55:29 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560112368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2560112368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_alerts.3667462946 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 816850270 ps |
| CPU time | 70.75 seconds |
| Started | Oct 09 04:26:01 PM UTC 24 |
| Finished | Oct 09 04:27:14 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667462946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3667462946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_classes.1649177531 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 403850139 ps |
| CPU time | 54.67 seconds |
| Started | Oct 09 04:34:22 PM UTC 24 |
| Finished | Oct 09 04:35:18 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649177531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1649177531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_classes.1033634113 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 1531959857 ps |
| CPU time | 51.06 seconds |
| Started | Oct 09 04:37:46 PM UTC 24 |
| Finished | Oct 09 04:38:38 PM UTC 24 |
| Peak memory | 260604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033634113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1033634113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_smoke.3452364246 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 609527817 ps |
| CPU time | 47.54 seconds |
| Started | Oct 09 04:40:26 PM UTC 24 |
| Finished | Oct 09 04:41:15 PM UTC 24 |
| Peak memory | 266600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452364246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3452364246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg.1528386977 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 105066206816 ps |
| CPU time | 1574.8 seconds |
| Started | Oct 09 04:48:46 PM UTC 24 |
| Finished | Oct 09 05:15:19 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528386977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1528386977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_stress_all.803121846 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 129840788378 ps |
| CPU time | 3632.28 seconds |
| Started | Oct 09 04:49:06 PM UTC 24 |
| Finished | Oct 09 05:50:19 PM UTC 24 |
| Peak memory | 318380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803121846 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_stress_all.803121846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_sig_int_fail.3549654347 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 170095109 ps |
| CPU time | 7.14 seconds |
| Started | Oct 09 04:50:58 PM UTC 24 |
| Finished | Oct 09 04:51:06 PM UTC 24 |
| Peak memory | 250488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549654347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3549654347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_alerts.3382461964 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 489052540 ps |
| CPU time | 36.18 seconds |
| Started | Oct 09 05:06:52 PM UTC 24 |
| Finished | Oct 09 05:07:30 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382461964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3382461964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_sig_int_fail.2589818053 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 1284690844 ps |
| CPU time | 74.19 seconds |
| Started | Oct 09 05:10:50 PM UTC 24 |
| Finished | Oct 09 05:12:07 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589818053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.2589818053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_lpg.996890293 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 9986560920 ps |
| CPU time | 1223.67 seconds |
| Started | Oct 09 05:22:42 PM UTC 24 |
| Finished | Oct 09 05:43:22 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996890293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.996890293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_sig_int_fail.3083531606 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 769898661 ps |
| CPU time | 10.34 seconds |
| Started | Oct 09 05:22:29 PM UTC 24 |
| Finished | Oct 09 05:22:41 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083531606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3083531606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3349186569 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 2591463317 ps |
| CPU time | 122.99 seconds |
| Started | Oct 09 06:05:27 PM UTC 24 |
| Finished | Oct 09 06:07:33 PM UTC 24 |
| Peak memory | 250620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349186569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3349186569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3369212718 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 61644260 ps |
| CPU time | 5.28 seconds |
| Started | Oct 09 06:06:32 PM UTC 24 |
| Finished | Oct 09 06:06:38 PM UTC 24 |
| Peak memory | 248772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369212718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3369212718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3935198601 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 196967461 ps |
| CPU time | 5.81 seconds |
| Started | Oct 09 06:06:57 PM UTC 24 |
| Finished | Oct 09 06:07:04 PM UTC 24 |
| Peak memory | 248504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935198601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3935198601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4200765358 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 516636155 ps |
| CPU time | 40.62 seconds |
| Started | Oct 09 06:09:20 PM UTC 24 |
| Finished | Oct 09 06:10:03 PM UTC 24 |
| Peak memory | 250556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200765358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4200765358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3950976370 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 1158862742 ps |
| CPU time | 107.8 seconds |
| Started | Oct 09 06:02:29 PM UTC 24 |
| Finished | Oct 09 06:04:19 PM UTC 24 |
| Peak memory | 250832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950976370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3950976370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3736455497 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 92041081 ps |
| CPU time | 3.82 seconds |
| Started | Oct 09 05:53:50 PM UTC 24 |
| Finished | Oct 09 05:53:55 PM UTC 24 |
| Peak memory | 248656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736455497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3736455497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_intg_err.152096349 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 62405493 ps |
| CPU time | 7.28 seconds |
| Started | Oct 09 05:55:24 PM UTC 24 |
| Finished | Oct 09 05:55:33 PM UTC 24 |
| Peak memory | 248772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152096349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.152096349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.627593652 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 823784837 ps |
| CPU time | 178.99 seconds |
| Started | Oct 09 06:04:47 PM UTC 24 |
| Finished | Oct 09 06:07:49 PM UTC 24 |
| Peak memory | 277520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627593652 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.627593652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_intg_err.3886722296 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 62277231 ps |
| CPU time | 6.49 seconds |
| Started | Oct 09 05:57:22 PM UTC 24 |
| Finished | Oct 09 05:57:30 PM UTC 24 |
| Peak memory | 248784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886722296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.3886722296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_smoke.3356732053 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 427909335 ps |
| CPU time | 27.33 seconds |
| Started | Oct 09 04:15:45 PM UTC 24 |
| Finished | Oct 09 04:16:14 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356732053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3356732053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1401759960 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 17805072960 ps |
| CPU time | 332.82 seconds |
| Started | Oct 09 05:54:23 PM UTC 24 |
| Finished | Oct 09 06:00:01 PM UTC 24 |
| Peak memory | 248576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401759960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1401759960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3568505112 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 44460491 ps |
| CPU time | 5.7 seconds |
| Started | Oct 09 06:05:55 PM UTC 24 |
| Finished | Oct 09 06:06:02 PM UTC 24 |
| Peak memory | 250556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568505112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3568505112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1946927308 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 892720832 ps |
| CPU time | 73.37 seconds |
| Started | Oct 09 06:08:43 PM UTC 24 |
| Finished | Oct 09 06:09:59 PM UTC 24 |
| Peak memory | 258744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946927308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1946927308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_intg_err.30441418 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 65228997 ps |
| CPU time | 2.75 seconds |
| Started | Oct 09 06:10:00 PM UTC 24 |
| Finished | Oct 09 06:10:04 PM UTC 24 |
| Peak memory | 250636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30441418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.30441418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2469936024 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 22767350 ps |
| CPU time | 4.4 seconds |
| Started | Oct 09 05:56:04 PM UTC 24 |
| Finished | Oct 09 05:56:10 PM UTC 24 |
| Peak memory | 248592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469936024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2469936024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_intg_err.102965722 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1086721985 ps |
| CPU time | 52.01 seconds |
| Started | Oct 09 06:00:43 PM UTC 24 |
| Finished | Oct 09 06:01:37 PM UTC 24 |
| Peak memory | 250552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102965722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.102965722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2937685564 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 1237735959 ps |
| CPU time | 66.2 seconds |
| Started | Oct 09 06:01:20 PM UTC 24 |
| Finished | Oct 09 06:02:28 PM UTC 24 |
| Peak memory | 250640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937685564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2937685564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4272722176 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 445364658 ps |
| CPU time | 58.26 seconds |
| Started | Oct 09 06:03:10 PM UTC 24 |
| Finished | Oct 09 06:04:10 PM UTC 24 |
| Peak memory | 250832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272722176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4272722176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all_with_rand_reset.1824885727 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 1323056537 ps |
| CPU time | 101.75 seconds |
| Started | Oct 09 04:16:36 PM UTC 24 |
| Finished | Oct 09 04:18:20 PM UTC 24 |
| Peak memory | 276972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1824885727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.al ert_handler_stress_all_with_rand_reset.1824885727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_classes.2408376824 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 2345461725 ps |
| CPU time | 90.41 seconds |
| Started | Oct 09 04:52:52 PM UTC 24 |
| Finished | Oct 09 04:54:25 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408376824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2408376824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_intr_timeout.3826668044 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 388748060 ps |
| CPU time | 28.45 seconds |
| Started | Oct 09 04:18:29 PM UTC 24 |
| Finished | Oct 09 04:18:59 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826668044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3826668044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1225526911 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 15216902308 ps |
| CPU time | 284.39 seconds |
| Started | Oct 09 05:54:25 PM UTC 24 |
| Finished | Oct 09 05:59:14 PM UTC 24 |
| Peak memory | 250884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225526911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1225526911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3636802307 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 110712077 ps |
| CPU time | 14.98 seconds |
| Started | Oct 09 05:54:01 PM UTC 24 |
| Finished | Oct 09 05:54:17 PM UTC 24 |
| Peak memory | 260800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636802307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3636802307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3599776489 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 243428759 ps |
| CPU time | 14.9 seconds |
| Started | Oct 09 05:55:08 PM UTC 24 |
| Finished | Oct 09 05:55:24 PM UTC 24 |
| Peak memory | 267080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599776489 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_ rw_with_rand_reset.3599776489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_csr_rw.387747029 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 59993112 ps |
| CPU time | 5.01 seconds |
| Started | Oct 09 05:54:18 PM UTC 24 |
| Finished | Oct 09 05:54:24 PM UTC 24 |
| Peak memory | 248712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387747029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.387747029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_intr_test.3920296628 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 25833214 ps |
| CPU time | 2.39 seconds |
| Started | Oct 09 05:53:56 PM UTC 24 |
| Finished | Oct 09 05:54:00 PM UTC 24 |
| Peak memory | 248460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920296628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3920296628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3093854398 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 274263418 ps |
| CPU time | 40.19 seconds |
| Started | Oct 09 05:55:07 PM UTC 24 |
| Finished | Oct 09 05:55:49 PM UTC 24 |
| Peak memory | 260872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093854398 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.3093854398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3458467450 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 1489146519 ps |
| CPU time | 105.93 seconds |
| Started | Oct 09 05:53:25 PM UTC 24 |
| Finished | Oct 09 05:55:14 PM UTC 24 |
| Peak memory | 267476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458467450 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.3458467450 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/0.alert_handler_tl_errors.1720202151 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 175874282 ps |
| CPU time | 19.67 seconds |
| Started | Oct 09 05:53:28 PM UTC 24 |
| Finished | Oct 09 05:53:49 PM UTC 24 |
| Peak memory | 260928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720202151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1720202151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1619020357 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 12776928345 ps |
| CPU time | 407.55 seconds |
| Started | Oct 09 05:55:38 PM UTC 24 |
| Finished | Oct 09 06:02:32 PM UTC 24 |
| Peak memory | 250892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619020357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1619020357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1132094880 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 14854412024 ps |
| CPU time | 504.88 seconds |
| Started | Oct 09 05:55:34 PM UTC 24 |
| Finished | Oct 09 06:04:06 PM UTC 24 |
| Peak memory | 248580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132094880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1132094880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1757614723 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 61219906 ps |
| CPU time | 6.11 seconds |
| Started | Oct 09 05:55:30 PM UTC 24 |
| Finished | Oct 09 05:55:37 PM UTC 24 |
| Peak memory | 260876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757614723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1757614723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3515414022 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 35018325 ps |
| CPU time | 8.3 seconds |
| Started | Oct 09 05:55:44 PM UTC 24 |
| Finished | Oct 09 05:55:54 PM UTC 24 |
| Peak memory | 250624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515414022 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_ rw_with_rand_reset.3515414022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.49331960 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 530846937 ps |
| CPU time | 48.9 seconds |
| Started | Oct 09 05:55:41 PM UTC 24 |
| Finished | Oct 09 05:56:32 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49331960 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.49331960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/1.alert_handler_tl_errors.4423124 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 51178729 ps |
| CPU time | 8.08 seconds |
| Started | Oct 09 05:55:21 PM UTC 24 |
| Finished | Oct 09 05:55:30 PM UTC 24 |
| Peak memory | 265256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4423124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_S EQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4423124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.4077973108 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 62813277 ps |
| CPU time | 10.64 seconds |
| Started | Oct 09 06:05:13 PM UTC 24 |
| Finished | Oct 09 06:05:25 PM UTC 24 |
| Peak memory | 262908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077973108 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_mem _rw_with_rand_reset.4077973108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_csr_rw.2358044742 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 372581187 ps |
| CPU time | 7.09 seconds |
| Started | Oct 09 06:05:04 PM UTC 24 |
| Finished | Oct 09 06:05:12 PM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358044742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2358044742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_intr_test.4268137822 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 15351728 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 06:05:00 PM UTC 24 |
| Finished | Oct 09 06:05:03 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268137822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4268137822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1238686780 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 281782812 ps |
| CPU time | 37.48 seconds |
| Started | Oct 09 06:05:06 PM UTC 24 |
| Finished | Oct 09 06:05:45 PM UTC 24 |
| Peak memory | 258824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238686780 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_outstanding.1238686780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/10.alert_handler_tl_errors.2293861398 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 134002179 ps |
| CPU time | 15.09 seconds |
| Started | Oct 09 06:04:49 PM UTC 24 |
| Finished | Oct 09 06:05:05 PM UTC 24 |
| Peak memory | 260872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293861398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2293861398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.753369396 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 67598339 ps |
| CPU time | 13.3 seconds |
| Started | Oct 09 06:05:45 PM UTC 24 |
| Finished | Oct 09 06:06:00 PM UTC 24 |
| Peak memory | 264952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753369396 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_mem_ rw_with_rand_reset.753369396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_csr_rw.2513176272 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 283249998 ps |
| CPU time | 5.14 seconds |
| Started | Oct 09 06:05:34 PM UTC 24 |
| Finished | Oct 09 06:05:40 PM UTC 24 |
| Peak memory | 248836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513176272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2513176272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.4241465981 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 595876384 ps |
| CPU time | 34.23 seconds |
| Started | Oct 09 06:05:41 PM UTC 24 |
| Finished | Oct 09 06:06:17 PM UTC 24 |
| Peak memory | 258748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241465981 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outstanding.4241465981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1558101104 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4212033222 ps |
| CPU time | 380.1 seconds |
| Started | Oct 09 06:05:22 PM UTC 24 |
| Finished | Oct 09 06:11:48 PM UTC 24 |
| Peak memory | 277508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558101104 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.1558101104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3187039401 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 15175854715 ps |
| CPU time | 585.77 seconds |
| Started | Oct 09 06:05:17 PM UTC 24 |
| Finished | Oct 09 06:15:10 PM UTC 24 |
| Peak memory | 279560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187039401 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shad ow_reg_errors_with_csr_rw.3187039401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/11.alert_handler_tl_errors.1364897419 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 580830660 ps |
| CPU time | 24.39 seconds |
| Started | Oct 09 06:05:25 PM UTC 24 |
| Finished | Oct 09 06:05:51 PM UTC 24 |
| Peak memory | 267348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364897419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1364897419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2973794530 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 33943929 ps |
| CPU time | 9 seconds |
| Started | Oct 09 06:06:11 PM UTC 24 |
| Finished | Oct 09 06:06:21 PM UTC 24 |
| Peak memory | 250692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973794530 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_mem _rw_with_rand_reset.2973794530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_csr_rw.338608231 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 63082367 ps |
| CPU time | 4.96 seconds |
| Started | Oct 09 06:06:03 PM UTC 24 |
| Finished | Oct 09 06:06:10 PM UTC 24 |
| Peak memory | 248508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338608231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.338608231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_intr_test.272967443 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 21884633 ps |
| CPU time | 2.16 seconds |
| Started | Oct 09 06:06:01 PM UTC 24 |
| Finished | Oct 09 06:06:04 PM UTC 24 |
| Peak memory | 248448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272967443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.272967443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3631349242 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1268383885 ps |
| CPU time | 31.33 seconds |
| Started | Oct 09 06:06:06 PM UTC 24 |
| Finished | Oct 09 06:06:38 PM UTC 24 |
| Peak memory | 258824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631349242 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_outstanding.3631349242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3732757176 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4081862126 ps |
| CPU time | 169.11 seconds |
| Started | Oct 09 06:05:54 PM UTC 24 |
| Finished | Oct 09 06:08:46 PM UTC 24 |
| Peak memory | 277840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732757176 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.3732757176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2161920286 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 52707160177 ps |
| CPU time | 1085.95 seconds |
| Started | Oct 09 06:05:46 PM UTC 24 |
| Finished | Oct 09 06:24:07 PM UTC 24 |
| Peak memory | 277516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161920286 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shad ow_reg_errors_with_csr_rw.2161920286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/12.alert_handler_tl_errors.3825243612 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 973001669 ps |
| CPU time | 14.87 seconds |
| Started | Oct 09 06:05:54 PM UTC 24 |
| Finished | Oct 09 06:06:10 PM UTC 24 |
| Peak memory | 261140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825243612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3825243612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3329573284 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 61268608 ps |
| CPU time | 13.73 seconds |
| Started | Oct 09 06:06:41 PM UTC 24 |
| Finished | Oct 09 06:06:56 PM UTC 24 |
| Peak memory | 264956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329573284 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_mem _rw_with_rand_reset.3329573284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_csr_rw.4167971856 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 34593328 ps |
| CPU time | 9.05 seconds |
| Started | Oct 09 06:06:39 PM UTC 24 |
| Finished | Oct 09 06:06:50 PM UTC 24 |
| Peak memory | 248836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167971856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.4167971856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_intr_test.1909371267 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 13369728 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 06:06:37 PM UTC 24 |
| Finished | Oct 09 06:06:41 PM UTC 24 |
| Peak memory | 248532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909371267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.1909371267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1165996804 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1994175584 ps |
| CPU time | 49.32 seconds |
| Started | Oct 09 06:06:40 PM UTC 24 |
| Finished | Oct 09 06:07:31 PM UTC 24 |
| Peak memory | 258824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165996804 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_outstanding.1165996804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/13.alert_handler_tl_errors.2592322137 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 33140984 ps |
| CPU time | 6.62 seconds |
| Started | Oct 09 06:06:22 PM UTC 24 |
| Finished | Oct 09 06:06:30 PM UTC 24 |
| Peak memory | 263252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592322137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2592322137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.921391783 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 81766998 ps |
| CPU time | 6.96 seconds |
| Started | Oct 09 06:07:10 PM UTC 24 |
| Finished | Oct 09 06:07:19 PM UTC 24 |
| Peak memory | 262980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921391783 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_mem_ rw_with_rand_reset.921391783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_csr_rw.2144051757 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 961864907 ps |
| CPU time | 13.52 seconds |
| Started | Oct 09 06:07:05 PM UTC 24 |
| Finished | Oct 09 06:07:20 PM UTC 24 |
| Peak memory | 248508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144051757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2144051757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_intr_test.686159514 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 10144182 ps |
| CPU time | 2.12 seconds |
| Started | Oct 09 06:07:00 PM UTC 24 |
| Finished | Oct 09 06:07:04 PM UTC 24 |
| Peak memory | 248452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686159514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.686159514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1043114134 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 250276883 ps |
| CPU time | 29.15 seconds |
| Started | Oct 09 06:07:05 PM UTC 24 |
| Finished | Oct 09 06:07:36 PM UTC 24 |
| Peak memory | 258752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043114134 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_outstanding.1043114134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.407340268 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 6092153354 ps |
| CPU time | 274.94 seconds |
| Started | Oct 09 06:06:45 PM UTC 24 |
| Finished | Oct 09 06:11:25 PM UTC 24 |
| Peak memory | 277784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407340268 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.407340268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.584500818 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 12587274886 ps |
| CPU time | 593.83 seconds |
| Started | Oct 09 06:06:42 PM UTC 24 |
| Finished | Oct 09 06:16:44 PM UTC 24 |
| Peak memory | 277780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584500818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shado w_reg_errors_with_csr_rw.584500818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/14.alert_handler_tl_errors.1129980916 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 298258212 ps |
| CPU time | 17.86 seconds |
| Started | Oct 09 06:06:51 PM UTC 24 |
| Finished | Oct 09 06:07:10 PM UTC 24 |
| Peak memory | 267016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129980916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1129980916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4117550546 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 73068835 ps |
| CPU time | 8.58 seconds |
| Started | Oct 09 06:07:44 PM UTC 24 |
| Finished | Oct 09 06:07:53 PM UTC 24 |
| Peak memory | 260932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117550546 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_mem _rw_with_rand_reset.4117550546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_csr_rw.1946343167 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 67066885 ps |
| CPU time | 6.69 seconds |
| Started | Oct 09 06:07:40 PM UTC 24 |
| Finished | Oct 09 06:07:48 PM UTC 24 |
| Peak memory | 250628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946343167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1946343167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_intr_test.2011068416 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 8187551 ps |
| CPU time | 2.52 seconds |
| Started | Oct 09 06:07:37 PM UTC 24 |
| Finished | Oct 09 06:07:41 PM UTC 24 |
| Peak memory | 248660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011068416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2011068416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.834617045 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1137552686 ps |
| CPU time | 21.44 seconds |
| Started | Oct 09 06:07:41 PM UTC 24 |
| Finished | Oct 09 06:08:04 PM UTC 24 |
| Peak memory | 258752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834617045 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_outstanding.834617045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.4160710010 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 858598513 ps |
| CPU time | 79.46 seconds |
| Started | Oct 09 06:07:21 PM UTC 24 |
| Finished | Oct 09 06:08:43 PM UTC 24 |
| Peak memory | 267280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160710010 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.4160710010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_errors.1296060689 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 160908986 ps |
| CPU time | 10.05 seconds |
| Started | Oct 09 06:07:31 PM UTC 24 |
| Finished | Oct 09 06:07:43 PM UTC 24 |
| Peak memory | 261076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296060689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1296060689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/15.alert_handler_tl_intg_err.773026053 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 68597878 ps |
| CPU time | 4.29 seconds |
| Started | Oct 09 06:07:34 PM UTC 24 |
| Finished | Oct 09 06:07:39 PM UTC 24 |
| Peak memory | 248776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773026053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_te st +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.773026053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3846091051 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 270605613 ps |
| CPU time | 19.53 seconds |
| Started | Oct 09 06:08:10 PM UTC 24 |
| Finished | Oct 09 06:08:30 PM UTC 24 |
| Peak memory | 263172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846091051 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_mem _rw_with_rand_reset.3846091051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_csr_rw.1756997524 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 91639750 ps |
| CPU time | 5.22 seconds |
| Started | Oct 09 06:08:05 PM UTC 24 |
| Finished | Oct 09 06:08:11 PM UTC 24 |
| Peak memory | 248580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756997524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1756997524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_intr_test.3530252570 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 16981652 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 06:08:03 PM UTC 24 |
| Finished | Oct 09 06:08:06 PM UTC 24 |
| Peak memory | 248596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530252570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3530252570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2830750931 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 695306718 ps |
| CPU time | 39.85 seconds |
| Started | Oct 09 06:08:07 PM UTC 24 |
| Finished | Oct 09 06:08:49 PM UTC 24 |
| Peak memory | 261064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830750931 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outstanding.2830750931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.919013953 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 9714203551 ps |
| CPU time | 199.84 seconds |
| Started | Oct 09 06:07:51 PM UTC 24 |
| Finished | Oct 09 06:11:14 PM UTC 24 |
| Peak memory | 279568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919013953 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.919013953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3593378701 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 9897084390 ps |
| CPU time | 402.03 seconds |
| Started | Oct 09 06:07:49 PM UTC 24 |
| Finished | Oct 09 06:14:37 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593378701 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shad ow_reg_errors_with_csr_rw.3593378701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/16.alert_handler_tl_errors.3109062682 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 69290331 ps |
| CPU time | 15.8 seconds |
| Started | Oct 09 06:07:51 PM UTC 24 |
| Finished | Oct 09 06:08:08 PM UTC 24 |
| Peak memory | 261140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109062682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3109062682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3746514804 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 1039239377 ps |
| CPU time | 9.73 seconds |
| Started | Oct 09 06:08:54 PM UTC 24 |
| Finished | Oct 09 06:09:05 PM UTC 24 |
| Peak memory | 250884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746514804 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_mem _rw_with_rand_reset.3746514804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_csr_rw.133574152 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 357151329 ps |
| CPU time | 13.1 seconds |
| Started | Oct 09 06:08:50 PM UTC 24 |
| Finished | Oct 09 06:09:04 PM UTC 24 |
| Peak memory | 248580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133574152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.133574152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_intr_test.1821067300 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 19985096 ps |
| CPU time | 2.22 seconds |
| Started | Oct 09 06:08:47 PM UTC 24 |
| Finished | Oct 09 06:08:50 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821067300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1821067300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.466332752 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1424870412 ps |
| CPU time | 35.71 seconds |
| Started | Oct 09 06:08:51 PM UTC 24 |
| Finished | Oct 09 06:09:28 PM UTC 24 |
| Peak memory | 260800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466332752 -assert nopostproc +UVM_TESTNAME=alert_handle r_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_outstanding.466332752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3612573355 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 5851245302 ps |
| CPU time | 920.65 seconds |
| Started | Oct 09 06:08:10 PM UTC 24 |
| Finished | Oct 09 06:23:43 PM UTC 24 |
| Peak memory | 277616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612573355 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shad ow_reg_errors_with_csr_rw.3612573355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/17.alert_handler_tl_errors.825831927 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 652349941 ps |
| CPU time | 19.65 seconds |
| Started | Oct 09 06:08:31 PM UTC 24 |
| Finished | Oct 09 06:08:52 PM UTC 24 |
| Peak memory | 260864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825831927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.825831927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.906447634 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 64060938 ps |
| CPU time | 5.37 seconds |
| Started | Oct 09 06:09:30 PM UTC 24 |
| Finished | Oct 09 06:09:37 PM UTC 24 |
| Peak memory | 250692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906447634 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_mem_ rw_with_rand_reset.906447634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_csr_rw.3749664350 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 116361123 ps |
| CPU time | 7.61 seconds |
| Started | Oct 09 06:09:28 PM UTC 24 |
| Finished | Oct 09 06:09:36 PM UTC 24 |
| Peak memory | 250756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749664350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3749664350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_intr_test.2720841579 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 9582117 ps |
| CPU time | 2.11 seconds |
| Started | Oct 09 06:09:23 PM UTC 24 |
| Finished | Oct 09 06:09:26 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720841579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2720841579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3409334217 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 537573006 ps |
| CPU time | 59.43 seconds |
| Started | Oct 09 06:09:29 PM UTC 24 |
| Finished | Oct 09 06:10:30 PM UTC 24 |
| Peak memory | 261064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409334217 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_outstanding.3409334217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.325835089 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 70713617423 ps |
| CPU time | 1098.3 seconds |
| Started | Oct 09 06:08:59 PM UTC 24 |
| Finished | Oct 09 06:27:32 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325835089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shado w_reg_errors_with_csr_rw.325835089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/18.alert_handler_tl_errors.278402279 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 798005752 ps |
| CPU time | 14.59 seconds |
| Started | Oct 09 06:09:06 PM UTC 24 |
| Finished | Oct 09 06:09:22 PM UTC 24 |
| Peak memory | 260868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278402279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.278402279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.777272877 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 35604886 ps |
| CPU time | 8.28 seconds |
| Started | Oct 09 06:10:08 PM UTC 24 |
| Finished | Oct 09 06:10:18 PM UTC 24 |
| Peak memory | 267000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777272877 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_mem_ rw_with_rand_reset.777272877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_csr_rw.3549425533 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 25593750 ps |
| CPU time | 5.16 seconds |
| Started | Oct 09 06:10:04 PM UTC 24 |
| Finished | Oct 09 06:10:10 PM UTC 24 |
| Peak memory | 248772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549425533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3549425533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_intr_test.1161286268 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 20996641 ps |
| CPU time | 2.29 seconds |
| Started | Oct 09 06:10:04 PM UTC 24 |
| Finished | Oct 09 06:10:07 PM UTC 24 |
| Peak memory | 248460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161286268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1161286268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3361361041 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 91050801 ps |
| CPU time | 18.75 seconds |
| Started | Oct 09 06:10:05 PM UTC 24 |
| Finished | Oct 09 06:10:25 PM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361361041 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outstanding.3361361041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/19.alert_handler_tl_errors.879473955 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 366345781 ps |
| CPU time | 22.26 seconds |
| Started | Oct 09 06:10:00 PM UTC 24 |
| Finished | Oct 09 06:10:24 PM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879473955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.879473955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2883634792 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 28476567419 ps |
| CPU time | 839 seconds |
| Started | Oct 09 05:56:33 PM UTC 24 |
| Finished | Oct 09 06:10:44 PM UTC 24 |
| Peak memory | 250628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883634792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2883634792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2146005561 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 223674588 ps |
| CPU time | 14.55 seconds |
| Started | Oct 09 05:56:14 PM UTC 24 |
| Finished | Oct 09 05:56:30 PM UTC 24 |
| Peak memory | 261068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146005561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2146005561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.467388081 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 97136102 ps |
| CPU time | 11.8 seconds |
| Started | Oct 09 05:56:59 PM UTC 24 |
| Finished | Oct 09 05:57:12 PM UTC 24 |
| Peak memory | 250896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467388081 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_r w_with_rand_reset.467388081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_csr_rw.664329928 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 33641921 ps |
| CPU time | 5.7 seconds |
| Started | Oct 09 05:56:32 PM UTC 24 |
| Finished | Oct 09 05:56:39 PM UTC 24 |
| Peak memory | 250824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664329928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.664329928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_intr_test.61595709 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 10808035 ps |
| CPU time | 2.03 seconds |
| Started | Oct 09 05:56:10 PM UTC 24 |
| Finished | Oct 09 05:56:13 PM UTC 24 |
| Peak memory | 246472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61595709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_ SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handle r-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.61595709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.49887396 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1873996343 ps |
| CPU time | 60.73 seconds |
| Started | Oct 09 05:56:40 PM UTC 24 |
| Finished | Oct 09 05:57:43 PM UTC 24 |
| Peak memory | 258828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49887396 -assert nopostproc +UVM_TESTNAME=alert_handler _base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.49887396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1744695 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 47208817371 ps |
| CPU time | 1390.85 seconds |
| Started | Oct 09 05:55:49 PM UTC 24 |
| Finished | Oct 09 06:19:18 PM UTC 24 |
| Peak memory | 277776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744695 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_r eg_errors_with_csr_rw.1744695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/2.alert_handler_tl_errors.1834925092 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 300052060 ps |
| CPU time | 35.24 seconds |
| Started | Oct 09 05:55:56 PM UTC 24 |
| Finished | Oct 09 05:56:33 PM UTC 24 |
| Peak memory | 261132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834925092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1834925092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/20.alert_handler_intr_test.645632762 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 34917791 ps |
| CPU time | 2.47 seconds |
| Started | Oct 09 06:10:12 PM UTC 24 |
| Finished | Oct 09 06:10:15 PM UTC 24 |
| Peak memory | 248452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645632762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.645632762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/21.alert_handler_intr_test.2485405821 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 8647098 ps |
| CPU time | 2.16 seconds |
| Started | Oct 09 06:10:16 PM UTC 24 |
| Finished | Oct 09 06:10:20 PM UTC 24 |
| Peak memory | 248456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485405821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.2485405821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/22.alert_handler_intr_test.1012915042 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 10592601 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 06:10:19 PM UTC 24 |
| Finished | Oct 09 06:10:22 PM UTC 24 |
| Peak memory | 248460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012915042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1012915042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/23.alert_handler_intr_test.1898926231 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 23581112 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 06:10:21 PM UTC 24 |
| Finished | Oct 09 06:10:25 PM UTC 24 |
| Peak memory | 248460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898926231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1898926231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/24.alert_handler_intr_test.2604183724 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 11370327 ps |
| CPU time | 2.27 seconds |
| Started | Oct 09 06:10:23 PM UTC 24 |
| Finished | Oct 09 06:10:27 PM UTC 24 |
| Peak memory | 248596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604183724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2604183724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/25.alert_handler_intr_test.3469815114 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 9833937 ps |
| CPU time | 2 seconds |
| Started | Oct 09 06:10:25 PM UTC 24 |
| Finished | Oct 09 06:10:28 PM UTC 24 |
| Peak memory | 246964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469815114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3469815114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/26.alert_handler_intr_test.1901814114 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 25444156 ps |
| CPU time | 2.13 seconds |
| Started | Oct 09 06:10:26 PM UTC 24 |
| Finished | Oct 09 06:10:29 PM UTC 24 |
| Peak memory | 246412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901814114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1901814114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/27.alert_handler_intr_test.1269492830 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 12940639 ps |
| CPU time | 1.69 seconds |
| Started | Oct 09 06:10:27 PM UTC 24 |
| Finished | Oct 09 06:10:30 PM UTC 24 |
| Peak memory | 246964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269492830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1269492830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/28.alert_handler_intr_test.859513578 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 10377321 ps |
| CPU time | 2.42 seconds |
| Started | Oct 09 06:10:29 PM UTC 24 |
| Finished | Oct 09 06:10:32 PM UTC 24 |
| Peak memory | 248716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859513578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.859513578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/29.alert_handler_intr_test.929219363 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 13429717 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 06:10:29 PM UTC 24 |
| Finished | Oct 09 06:10:32 PM UTC 24 |
| Peak memory | 248716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929219363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.929219363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1697579313 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2332163989 ps |
| CPU time | 189.82 seconds |
| Started | Oct 09 05:57:53 PM UTC 24 |
| Finished | Oct 09 06:01:06 PM UTC 24 |
| Peak memory | 250700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697579313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1697579313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3502739819 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 22879144880 ps |
| CPU time | 482.65 seconds |
| Started | Oct 09 05:57:44 PM UTC 24 |
| Finished | Oct 09 06:05:54 PM UTC 24 |
| Peak memory | 248580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502739819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3502739819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1388046527 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 39957615 ps |
| CPU time | 6.28 seconds |
| Started | Oct 09 05:57:35 PM UTC 24 |
| Finished | Oct 09 05:57:42 PM UTC 24 |
| Peak memory | 260800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388046527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1388046527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.112509757 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 60897573 ps |
| CPU time | 12.9 seconds |
| Started | Oct 09 05:59:15 PM UTC 24 |
| Finished | Oct 09 05:59:29 PM UTC 24 |
| Peak memory | 252672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112509757 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_r w_with_rand_reset.112509757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_csr_rw.3368079301 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 177891174 ps |
| CPU time | 6.94 seconds |
| Started | Oct 09 05:57:44 PM UTC 24 |
| Finished | Oct 09 05:57:52 PM UTC 24 |
| Peak memory | 248772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368079301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3368079301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_intr_test.3402830771 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 51864889 ps |
| CPU time | 2.21 seconds |
| Started | Oct 09 05:57:31 PM UTC 24 |
| Finished | Oct 09 05:57:34 PM UTC 24 |
| Peak memory | 248660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402830771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3402830771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2848834319 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 336893765 ps |
| CPU time | 32.77 seconds |
| Started | Oct 09 05:59:01 PM UTC 24 |
| Finished | Oct 09 05:59:35 PM UTC 24 |
| Peak memory | 250888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848834319 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.2848834319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1130495092 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3085359602 ps |
| CPU time | 173.55 seconds |
| Started | Oct 09 05:57:06 PM UTC 24 |
| Finished | Oct 09 06:00:03 PM UTC 24 |
| Peak memory | 267344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130495092 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.1130495092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1375730929 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 13136656045 ps |
| CPU time | 448.3 seconds |
| Started | Oct 09 05:57:00 PM UTC 24 |
| Finished | Oct 09 06:04:35 PM UTC 24 |
| Peak memory | 277584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375730929 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shado w_reg_errors_with_csr_rw.1375730929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/3.alert_handler_tl_errors.1921585575 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 109225415 ps |
| CPU time | 6.98 seconds |
| Started | Oct 09 05:57:13 PM UTC 24 |
| Finished | Oct 09 05:57:21 PM UTC 24 |
| Peak memory | 260876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921585575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1921585575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/30.alert_handler_intr_test.1551108129 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 12776134 ps |
| CPU time | 1.72 seconds |
| Started | Oct 09 06:10:30 PM UTC 24 |
| Finished | Oct 09 06:10:33 PM UTC 24 |
| Peak memory | 246896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551108129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1551108129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/31.alert_handler_intr_test.3643487778 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 12632408 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 06:10:32 PM UTC 24 |
| Finished | Oct 09 06:10:35 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643487778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3643487778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/32.alert_handler_intr_test.3334369110 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 9839027 ps |
| CPU time | 1.57 seconds |
| Started | Oct 09 06:10:32 PM UTC 24 |
| Finished | Oct 09 06:10:35 PM UTC 24 |
| Peak memory | 244852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334369110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3334369110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/33.alert_handler_intr_test.2417915796 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 8770349 ps |
| CPU time | 2 seconds |
| Started | Oct 09 06:10:33 PM UTC 24 |
| Finished | Oct 09 06:10:37 PM UTC 24 |
| Peak memory | 246896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417915796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2417915796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/34.alert_handler_intr_test.741738092 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 8760520 ps |
| CPU time | 2.34 seconds |
| Started | Oct 09 06:10:34 PM UTC 24 |
| Finished | Oct 09 06:10:37 PM UTC 24 |
| Peak memory | 248652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741738092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.741738092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/35.alert_handler_intr_test.3366984430 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 9543399 ps |
| CPU time | 2.05 seconds |
| Started | Oct 09 06:10:35 PM UTC 24 |
| Finished | Oct 09 06:10:38 PM UTC 24 |
| Peak memory | 246484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366984430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3366984430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/36.alert_handler_intr_test.4239980345 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 7771906 ps |
| CPU time | 1.79 seconds |
| Started | Oct 09 06:10:36 PM UTC 24 |
| Finished | Oct 09 06:10:39 PM UTC 24 |
| Peak memory | 246964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239980345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4239980345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/37.alert_handler_intr_test.1865024297 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 7128397 ps |
| CPU time | 1.76 seconds |
| Started | Oct 09 06:10:36 PM UTC 24 |
| Finished | Oct 09 06:10:39 PM UTC 24 |
| Peak memory | 244852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865024297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1865024297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/38.alert_handler_intr_test.1275072558 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 10064923 ps |
| CPU time | 2.64 seconds |
| Started | Oct 09 06:10:38 PM UTC 24 |
| Finished | Oct 09 06:10:42 PM UTC 24 |
| Peak memory | 248468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275072558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1275072558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/39.alert_handler_intr_test.557173448 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 73990162 ps |
| CPU time | 6.11 seconds |
| Started | Oct 09 06:10:39 PM UTC 24 |
| Finished | Oct 09 06:10:46 PM UTC 24 |
| Peak memory | 248708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557173448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.557173448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1597987587 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 3378393275 ps |
| CPU time | 385.73 seconds |
| Started | Oct 09 06:00:00 PM UTC 24 |
| Finished | Oct 09 06:06:40 PM UTC 24 |
| Peak memory | 250764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597987587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1597987587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1580828640 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 25185958046 ps |
| CPU time | 559.03 seconds |
| Started | Oct 09 05:59:52 PM UTC 24 |
| Finished | Oct 09 06:09:19 PM UTC 24 |
| Peak memory | 248580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580828640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1580828640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3011456270 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 129869569 ps |
| CPU time | 15.44 seconds |
| Started | Oct 09 05:59:42 PM UTC 24 |
| Finished | Oct 09 05:59:59 PM UTC 24 |
| Peak memory | 260800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM _LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011456270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3011456270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2567121894 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 294759811 ps |
| CPU time | 13.25 seconds |
| Started | Oct 09 06:00:09 PM UTC 24 |
| Finished | Oct 09 06:00:23 PM UTC 24 |
| Peak memory | 250888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567121894 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_ rw_with_rand_reset.2567121894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_csr_rw.779721877 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 20511907 ps |
| CPU time | 5.27 seconds |
| Started | Oct 09 05:59:45 PM UTC 24 |
| Finished | Oct 09 05:59:52 PM UTC 24 |
| Peak memory | 250560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779721877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.779721877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_intr_test.1096033123 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 10459176 ps |
| CPU time | 1.99 seconds |
| Started | Oct 09 05:59:38 PM UTC 24 |
| Finished | Oct 09 05:59:41 PM UTC 24 |
| Peak memory | 246964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096033123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1096033123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3764344417 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 356968531 ps |
| CPU time | 32.49 seconds |
| Started | Oct 09 06:00:02 PM UTC 24 |
| Finished | Oct 09 06:00:42 PM UTC 24 |
| Peak memory | 250824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764344417 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.3764344417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.10052227 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 1589520124 ps |
| CPU time | 103.46 seconds |
| Started | Oct 09 05:59:33 PM UTC 24 |
| Finished | Oct 09 06:01:18 PM UTC 24 |
| Peak memory | 277716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10052227 -assert nopostproc +UVM_TESTNAME=alert_handler_ba se_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.10052227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3821111029 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 81890184782 ps |
| CPU time | 571.14 seconds |
| Started | Oct 09 05:59:18 PM UTC 24 |
| Finished | Oct 09 06:08:58 PM UTC 24 |
| Peak memory | 277508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821111029 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shado w_reg_errors_with_csr_rw.3821111029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/4.alert_handler_tl_errors.3605642802 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 572702331 ps |
| CPU time | 10.14 seconds |
| Started | Oct 09 05:59:33 PM UTC 24 |
| Finished | Oct 09 05:59:44 PM UTC 24 |
| Peak memory | 261140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3605642802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3605642802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/40.alert_handler_intr_test.381034230 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 9686095 ps |
| CPU time | 2.4 seconds |
| Started | Oct 09 06:10:39 PM UTC 24 |
| Finished | Oct 09 06:10:42 PM UTC 24 |
| Peak memory | 247588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381034230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.381034230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/41.alert_handler_intr_test.981264268 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 9021484 ps |
| CPU time | 1.7 seconds |
| Started | Oct 09 06:10:39 PM UTC 24 |
| Finished | Oct 09 06:10:41 PM UTC 24 |
| Peak memory | 247680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981264268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.981264268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/42.alert_handler_intr_test.2482074809 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 15682425 ps |
| CPU time | 2.08 seconds |
| Started | Oct 09 06:10:40 PM UTC 24 |
| Finished | Oct 09 06:10:43 PM UTC 24 |
| Peak memory | 248460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482074809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2482074809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/43.alert_handler_intr_test.4195595707 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 11536525 ps |
| CPU time | 2.17 seconds |
| Started | Oct 09 06:10:40 PM UTC 24 |
| Finished | Oct 09 06:10:43 PM UTC 24 |
| Peak memory | 248456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195595707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4195595707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/44.alert_handler_intr_test.4252017875 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 6874654 ps |
| CPU time | 1.53 seconds |
| Started | Oct 09 06:10:43 PM UTC 24 |
| Finished | Oct 09 06:10:45 PM UTC 24 |
| Peak memory | 246896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252017875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4252017875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/45.alert_handler_intr_test.637639126 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 6344577 ps |
| CPU time | 2.24 seconds |
| Started | Oct 09 06:10:44 PM UTC 24 |
| Finished | Oct 09 06:10:47 PM UTC 24 |
| Peak memory | 248780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637639126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.637639126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/46.alert_handler_intr_test.2564662296 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 15660670 ps |
| CPU time | 1.62 seconds |
| Started | Oct 09 06:10:44 PM UTC 24 |
| Finished | Oct 09 06:10:47 PM UTC 24 |
| Peak memory | 244916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564662296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2564662296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/47.alert_handler_intr_test.1845407968 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 10192537 ps |
| CPU time | 2.44 seconds |
| Started | Oct 09 06:10:44 PM UTC 24 |
| Finished | Oct 09 06:10:48 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845407968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1845407968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/48.alert_handler_intr_test.445565286 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 41730763 ps |
| CPU time | 2.3 seconds |
| Started | Oct 09 06:10:44 PM UTC 24 |
| Finished | Oct 09 06:10:48 PM UTC 24 |
| Peak memory | 248448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445565286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.445565286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/49.alert_handler_intr_test.2558027815 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 9097797 ps |
| CPU time | 2.56 seconds |
| Started | Oct 09 06:10:46 PM UTC 24 |
| Finished | Oct 09 06:10:49 PM UTC 24 |
| Peak memory | 246740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558027815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2558027815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2598070340 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 1025231641 ps |
| CPU time | 15.65 seconds |
| Started | Oct 09 06:01:00 PM UTC 24 |
| Finished | Oct 09 06:01:17 PM UTC 24 |
| Peak memory | 267080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598070340 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_mem_ rw_with_rand_reset.2598070340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_csr_rw.3615959035 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 51776206 ps |
| CPU time | 7.8 seconds |
| Started | Oct 09 06:00:50 PM UTC 24 |
| Finished | Oct 09 06:00:59 PM UTC 24 |
| Peak memory | 248504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615959035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.3615959035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2657452050 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 331204219 ps |
| CPU time | 20.12 seconds |
| Started | Oct 09 06:00:50 PM UTC 24 |
| Finished | Oct 09 06:01:11 PM UTC 24 |
| Peak memory | 258824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657452050 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outstanding.2657452050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3106973793 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 6964481349 ps |
| CPU time | 604.62 seconds |
| Started | Oct 09 06:00:23 PM UTC 24 |
| Finished | Oct 09 06:10:36 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106973793 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shado w_reg_errors_with_csr_rw.3106973793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/5.alert_handler_tl_errors.3478712983 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 564241154 ps |
| CPU time | 12.74 seconds |
| Started | Oct 09 06:00:35 PM UTC 24 |
| Finished | Oct 09 06:00:49 PM UTC 24 |
| Peak memory | 260876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478712983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3478712983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1290567735 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 129669903 ps |
| CPU time | 8.32 seconds |
| Started | Oct 09 06:01:39 PM UTC 24 |
| Finished | Oct 09 06:01:49 PM UTC 24 |
| Peak memory | 250632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290567735 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_mem_ rw_with_rand_reset.1290567735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_csr_rw.4119942243 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 36681198 ps |
| CPU time | 9.23 seconds |
| Started | Oct 09 06:01:33 PM UTC 24 |
| Finished | Oct 09 06:01:43 PM UTC 24 |
| Peak memory | 248772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119942243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4119942243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_intr_test.782795829 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 10122067 ps |
| CPU time | 2.07 seconds |
| Started | Oct 09 06:01:29 PM UTC 24 |
| Finished | Oct 09 06:01:32 PM UTC 24 |
| Peak memory | 248720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782795829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST _SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handl er-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.782795829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2446973310 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 728505412 ps |
| CPU time | 68.36 seconds |
| Started | Oct 09 06:01:38 PM UTC 24 |
| Finished | Oct 09 06:02:49 PM UTC 24 |
| Peak memory | 259016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446973310 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outstanding.2446973310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3812822732 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 41477844886 ps |
| CPU time | 607.79 seconds |
| Started | Oct 09 06:01:07 PM UTC 24 |
| Finished | Oct 09 06:11:23 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812822732 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shado w_reg_errors_with_csr_rw.3812822732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/6.alert_handler_tl_errors.2235595124 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 97288249 ps |
| CPU time | 19.38 seconds |
| Started | Oct 09 06:01:17 PM UTC 24 |
| Finished | Oct 09 06:01:38 PM UTC 24 |
| Peak memory | 260948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235595124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2235595124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2504345654 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 197134146 ps |
| CPU time | 13.03 seconds |
| Started | Oct 09 06:02:37 PM UTC 24 |
| Finished | Oct 09 06:02:52 PM UTC 24 |
| Peak memory | 250696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504345654 -assert n opostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_mem_ rw_with_rand_reset.2504345654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_csr_rw.2906356730 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 34743958 ps |
| CPU time | 10.12 seconds |
| Started | Oct 09 06:02:33 PM UTC 24 |
| Finished | Oct 09 06:02:44 PM UTC 24 |
| Peak memory | 248580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906356730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2906356730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_intr_test.4026910122 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 13705161 ps |
| CPU time | 2.09 seconds |
| Started | Oct 09 06:02:32 PM UTC 24 |
| Finished | Oct 09 06:02:35 PM UTC 24 |
| Peak memory | 246412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026910122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4026910122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1014447653 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 988604415 ps |
| CPU time | 31 seconds |
| Started | Oct 09 06:02:36 PM UTC 24 |
| Finished | Oct 09 06:03:09 PM UTC 24 |
| Peak memory | 258824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014447653 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outstanding.1014447653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.952229426 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 15535763207 ps |
| CPU time | 290.67 seconds |
| Started | Oct 09 06:01:49 PM UTC 24 |
| Finished | Oct 09 06:06:45 PM UTC 24 |
| Peak memory | 283656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952229426 -assert nopostproc +UVM_TESTNAME=alert_handler_b ase_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.952229426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2957458981 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 76615099417 ps |
| CPU time | 1084.32 seconds |
| Started | Oct 09 06:01:44 PM UTC 24 |
| Finished | Oct 09 06:20:02 PM UTC 24 |
| Peak memory | 277776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957458981 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shado w_reg_errors_with_csr_rw.2957458981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/7.alert_handler_tl_errors.2172678508 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 106873094 ps |
| CPU time | 7.7 seconds |
| Started | Oct 09 06:02:28 PM UTC 24 |
| Finished | Oct 09 06:02:37 PM UTC 24 |
| Peak memory | 261076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172678508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2172678508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.166688938 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 564947382 ps |
| CPU time | 11.46 seconds |
| Started | Oct 09 06:03:32 PM UTC 24 |
| Finished | Oct 09 06:03:45 PM UTC 24 |
| Peak memory | 262896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166688938 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_mem_r w_with_rand_reset.166688938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_csr_rw.2368231855 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 192645436 ps |
| CPU time | 9 seconds |
| Started | Oct 09 06:03:19 PM UTC 24 |
| Finished | Oct 09 06:03:29 PM UTC 24 |
| Peak memory | 248508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368231855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_ TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_h andler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2368231855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_intr_test.1093045918 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 6586032 ps |
| CPU time | 2.28 seconds |
| Started | Oct 09 06:03:15 PM UTC 24 |
| Finished | Oct 09 06:03:18 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093045918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1093045918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1087461505 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1307818804 ps |
| CPU time | 72.06 seconds |
| Started | Oct 09 06:03:32 PM UTC 24 |
| Finished | Oct 09 06:04:46 PM UTC 24 |
| Peak memory | 258772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087461505 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outstanding.1087461505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2839808033 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 22181305894 ps |
| CPU time | 614.54 seconds |
| Started | Oct 09 06:02:50 PM UTC 24 |
| Finished | Oct 09 06:13:13 PM UTC 24 |
| Peak memory | 277588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839808033 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.2839808033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1294786471 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 6334234768 ps |
| CPU time | 645.69 seconds |
| Started | Oct 09 06:02:45 PM UTC 24 |
| Finished | Oct 09 06:13:40 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294786471 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shado w_reg_errors_with_csr_rw.1294786471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/8.alert_handler_tl_errors.1297003418 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 158976144 ps |
| CPU time | 20.42 seconds |
| Started | Oct 09 06:02:53 PM UTC 24 |
| Finished | Oct 09 06:03:15 PM UTC 24 |
| Peak memory | 260948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297003418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1297003418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.150589426 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 216445513 ps |
| CPU time | 18.71 seconds |
| Started | Oct 09 06:04:35 PM UTC 24 |
| Finished | Oct 09 06:04:55 PM UTC 24 |
| Peak memory | 263180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000 0 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150589426 -assert no postproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_mem_r w_with_rand_reset.150589426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_csr_rw.616317797 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 33363401 ps |
| CPU time | 5.59 seconds |
| Started | Oct 09 06:04:28 PM UTC 24 |
| Finished | Oct 09 06:04:34 PM UTC 24 |
| Peak memory | 248584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616317797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ha ndler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.616317797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_intr_test.3069199483 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 15428505 ps |
| CPU time | 2.95 seconds |
| Started | Oct 09 06:04:27 PM UTC 24 |
| Finished | Oct 09 06:04:31 PM UTC 24 |
| Peak memory | 248724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069199483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3069199483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.4158548681 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 1504901477 ps |
| CPU time | 46.7 seconds |
| Started | Oct 09 06:04:32 PM UTC 24 |
| Finished | Oct 09 06:05:21 PM UTC 24 |
| Peak memory | 259016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158548681 -assert nopostproc +UVM_TESTNAME=alert_handl er_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outstanding.4158548681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2229880633 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 15492463866 ps |
| CPU time | 346.46 seconds |
| Started | Oct 09 06:04:07 PM UTC 24 |
| Finished | Oct 09 06:09:58 PM UTC 24 |
| Peak memory | 277508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229880633 -assert nopostproc +UVM_TESTNAME=alert_handler_ base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.2229880633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1273945478 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 16985115556 ps |
| CPU time | 369.76 seconds |
| Started | Oct 09 06:03:46 PM UTC 24 |
| Finished | Oct 09 06:10:02 PM UTC 24 |
| Peak memory | 277512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_cs r_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273945478 -asser t nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shado w_reg_errors_with_csr_rw.1273945478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_errors.1433933872 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 1147790897 ps |
| CPU time | 35.96 seconds |
| Started | Oct 09 06:04:11 PM UTC 24 |
| Finished | Oct 09 06:04:48 PM UTC 24 |
| Peak memory | 261140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433933872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_hand ler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1433933872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2089294855 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 110117029 ps |
| CPU time | 4.65 seconds |
| Started | Oct 09 06:04:20 PM UTC 24 |
| Finished | Oct 09 06:04:26 PM UTC 24 |
| Peak memory | 248784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089294855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_t est +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_0 8/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2089294855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_entropy_stress.1010924196 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 3038954132 ps |
| CPU time | 48.3 seconds |
| Started | Oct 09 04:16:07 PM UTC 24 |
| Finished | Oct 09 04:16:56 PM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010924196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1010924196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_alert_accum.1587575774 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 6935877375 ps |
| CPU time | 175.82 seconds |
| Started | Oct 09 04:15:52 PM UTC 24 |
| Finished | Oct 09 04:18:51 PM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587575774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1587575774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_esc_intr_timeout.1763717612 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 261842821 ps |
| CPU time | 22.33 seconds |
| Started | Oct 09 04:15:49 PM UTC 24 |
| Finished | Oct 09 04:16:12 PM UTC 24 |
| Peak memory | 260524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763717612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1763717612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg.3268857123 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 38085703430 ps |
| CPU time | 1450.24 seconds |
| Started | Oct 09 04:15:58 PM UTC 24 |
| Finished | Oct 09 04:40:26 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268857123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.3268857123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_lpg_stub_clk.3373867928 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 186737425067 ps |
| CPU time | 823.26 seconds |
| Started | Oct 09 04:16:01 PM UTC 24 |
| Finished | Oct 09 04:29:55 PM UTC 24 |
| Peak memory | 283268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373867928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3373867928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_ping_timeout.2894668251 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 3452268430 ps |
| CPU time | 72.65 seconds |
| Started | Oct 09 04:15:57 PM UTC 24 |
| Finished | Oct 09 04:17:12 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894668251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2894668251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_sig_int_fail.3926865922 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 105624460 ps |
| CPU time | 22.46 seconds |
| Started | Oct 09 04:15:55 PM UTC 24 |
| Finished | Oct 09 04:16:19 PM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926865922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3926865922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/0.alert_handler_stress_all.622190652 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 78580692250 ps |
| CPU time | 1059.95 seconds |
| Started | Oct 09 04:16:08 PM UTC 24 |
| Finished | Oct 09 04:34:01 PM UTC 24 |
| Peak memory | 293296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622190652 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all.622190652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/0.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_entropy.598334571 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 34785491855 ps |
| CPU time | 843.94 seconds |
| Started | Oct 09 04:16:21 PM UTC 24 |
| Finished | Oct 09 04:30:36 PM UTC 24 |
| Peak memory | 283268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598334571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.598334571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_alert_accum.475427416 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 199829634 ps |
| CPU time | 15.1 seconds |
| Started | Oct 09 04:16:19 PM UTC 24 |
| Finished | Oct 09 04:16:35 PM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475427416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.475427416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_esc_intr_timeout.3170239144 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 8895947331 ps |
| CPU time | 63.61 seconds |
| Started | Oct 09 04:16:17 PM UTC 24 |
| Finished | Oct 09 04:17:23 PM UTC 24 |
| Peak memory | 260724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170239144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3170239144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg.1474859496 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 103882250770 ps |
| CPU time | 1952.62 seconds |
| Started | Oct 09 04:16:26 PM UTC 24 |
| Finished | Oct 09 04:49:21 PM UTC 24 |
| Peak memory | 299512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474859496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1474859496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_lpg_stub_clk.2471266695 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 34264921037 ps |
| CPU time | 1332.4 seconds |
| Started | Oct 09 04:16:26 PM UTC 24 |
| Finished | Oct 09 04:38:55 PM UTC 24 |
| Peak memory | 293300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471266695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2471266695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_ping_timeout.1952322699 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 7182768042 ps |
| CPU time | 280.93 seconds |
| Started | Oct 09 04:16:21 PM UTC 24 |
| Finished | Oct 09 04:21:06 PM UTC 24 |
| Peak memory | 266752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952322699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1952322699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_random_alerts.690456818 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 270527570 ps |
| CPU time | 25.2 seconds |
| Started | Oct 09 04:16:16 PM UTC 24 |
| Finished | Oct 09 04:16:43 PM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690456818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.690456818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_sec_cm.3600652293 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1351895414 ps |
| CPU time | 62.2 seconds |
| Started | Oct 09 04:16:42 PM UTC 24 |
| Finished | Oct 09 04:17:46 PM UTC 24 |
| Peak memory | 292572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600652293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3600652293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_sig_int_fail.3716169844 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 682190648 ps |
| CPU time | 26.14 seconds |
| Started | Oct 09 04:16:20 PM UTC 24 |
| Finished | Oct 09 04:16:47 PM UTC 24 |
| Peak memory | 266716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716169844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3716169844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_smoke.1085691537 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 953234075 ps |
| CPU time | 60.43 seconds |
| Started | Oct 09 04:16:15 PM UTC 24 |
| Finished | Oct 09 04:17:17 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085691537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1085691537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/1.alert_handler_stress_all.1719504797 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 130364791252 ps |
| CPU time | 4053.62 seconds |
| Started | Oct 09 04:16:32 PM UTC 24 |
| Finished | Oct 09 05:24:54 PM UTC 24 |
| Peak memory | 302196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719504797 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all.1719504797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/1.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy.1888454783 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 37151494841 ps |
| CPU time | 1238.42 seconds |
| Started | Oct 09 04:24:58 PM UTC 24 |
| Finished | Oct 09 04:45:52 PM UTC 24 |
| Peak memory | 293500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888454783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1888454783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_entropy_stress.3957675032 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1174528602 ps |
| CPU time | 72.89 seconds |
| Started | Oct 09 04:25:11 PM UTC 24 |
| Finished | Oct 09 04:26:26 PM UTC 24 |
| Peak memory | 260672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957675032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3957675032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_alert_accum.1587845884 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2261043366 ps |
| CPU time | 98.99 seconds |
| Started | Oct 09 04:24:50 PM UTC 24 |
| Finished | Oct 09 04:26:31 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587845884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1587845884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_esc_intr_timeout.1356012839 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3871472535 ps |
| CPU time | 49.89 seconds |
| Started | Oct 09 04:24:18 PM UTC 24 |
| Finished | Oct 09 04:25:10 PM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356012839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1356012839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_lpg_stub_clk.1562779096 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 90203575195 ps |
| CPU time | 2812.22 seconds |
| Started | Oct 09 04:25:11 PM UTC 24 |
| Finished | Oct 09 05:12:36 PM UTC 24 |
| Peak memory | 295352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562779096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1562779096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_ping_timeout.2210336623 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 23778162357 ps |
| CPU time | 288.07 seconds |
| Started | Oct 09 04:24:59 PM UTC 24 |
| Finished | Oct 09 04:29:51 PM UTC 24 |
| Peak memory | 260740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210336623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2210336623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_alerts.3715095608 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 936630300 ps |
| CPU time | 48.36 seconds |
| Started | Oct 09 04:24:04 PM UTC 24 |
| Finished | Oct 09 04:24:54 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715095608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3715095608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_random_classes.3177292874 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 1418546847 ps |
| CPU time | 39.18 seconds |
| Started | Oct 09 04:24:16 PM UTC 24 |
| Finished | Oct 09 04:24:57 PM UTC 24 |
| Peak memory | 266684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177292874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3177292874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_sig_int_fail.2929890360 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 459237536 ps |
| CPU time | 38.54 seconds |
| Started | Oct 09 04:24:54 PM UTC 24 |
| Finished | Oct 09 04:25:35 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929890360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2929890360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_smoke.2892622821 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 745806922 ps |
| CPU time | 51.79 seconds |
| Started | Oct 09 04:24:04 PM UTC 24 |
| Finished | Oct 09 04:24:57 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892622821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2892622821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/10.alert_handler_stress_all.3192072924 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 103943283325 ps |
| CPU time | 1701.19 seconds |
| Started | Oct 09 04:25:19 PM UTC 24 |
| Finished | Oct 09 04:54:00 PM UTC 24 |
| Peak memory | 293292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192072924 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_stress_all.3192072924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/10.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy.2651186169 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 57431119011 ps |
| CPU time | 1749.13 seconds |
| Started | Oct 09 04:26:58 PM UTC 24 |
| Finished | Oct 09 04:56:29 PM UTC 24 |
| Peak memory | 299516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651186169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2651186169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_entropy_stress.3853697146 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 595323025 ps |
| CPU time | 39.76 seconds |
| Started | Oct 09 04:27:48 PM UTC 24 |
| Finished | Oct 09 04:28:30 PM UTC 24 |
| Peak memory | 260472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853697146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3853697146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_alert_accum.3654193616 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 7992328134 ps |
| CPU time | 105.1 seconds |
| Started | Oct 09 04:26:37 PM UTC 24 |
| Finished | Oct 09 04:28:24 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654193616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3654193616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_esc_intr_timeout.1915647269 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1853954100 ps |
| CPU time | 33.8 seconds |
| Started | Oct 09 04:26:33 PM UTC 24 |
| Finished | Oct 09 04:27:08 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915647269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1915647269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg.292879770 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 86891420857 ps |
| CPU time | 1353.86 seconds |
| Started | Oct 09 04:27:15 PM UTC 24 |
| Finished | Oct 09 04:50:05 PM UTC 24 |
| Peak memory | 283056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292879770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.292879770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_lpg_stub_clk.1788768817 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 9086311035 ps |
| CPU time | 1150.36 seconds |
| Started | Oct 09 04:27:22 PM UTC 24 |
| Finished | Oct 09 04:46:47 PM UTC 24 |
| Peak memory | 283064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788768817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1788768817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_ping_timeout.1218664370 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 10859718462 ps |
| CPU time | 465.17 seconds |
| Started | Oct 09 04:27:09 PM UTC 24 |
| Finished | Oct 09 04:35:00 PM UTC 24 |
| Peak memory | 260612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218664370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1218664370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_random_classes.853682115 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 619032064 ps |
| CPU time | 53.17 seconds |
| Started | Oct 09 04:26:26 PM UTC 24 |
| Finished | Oct 09 04:27:21 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853682115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.853682115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_sig_int_fail.2295085143 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 429816886 ps |
| CPU time | 18.43 seconds |
| Started | Oct 09 04:26:38 PM UTC 24 |
| Finished | Oct 09 04:26:58 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295085143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2295085143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_smoke.3380184052 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 263232957 ps |
| CPU time | 22.92 seconds |
| Started | Oct 09 04:25:36 PM UTC 24 |
| Finished | Oct 09 04:26:00 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380184052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3380184052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/11.alert_handler_stress_all_with_rand_reset.3312703715 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4213731611 ps |
| CPU time | 252.62 seconds |
| Started | Oct 09 04:28:32 PM UTC 24 |
| Finished | Oct 09 04:32:48 PM UTC 24 |
| Peak memory | 279284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3312703715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.a lert_handler_stress_all_with_rand_reset.3312703715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/11.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_alert_accum_saturation.1973277106 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 18337832 ps |
| CPU time | 4.66 seconds |
| Started | Oct 09 04:30:24 PM UTC 24 |
| Finished | Oct 09 04:30:30 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973277106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1973277106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_entropy_stress.2847688797 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 1112433414 ps |
| CPU time | 14.51 seconds |
| Started | Oct 09 04:30:03 PM UTC 24 |
| Finished | Oct 09 04:30:18 PM UTC 24 |
| Peak memory | 260544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847688797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2847688797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_alert_accum.114661428 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1504105174 ps |
| CPU time | 90.72 seconds |
| Started | Oct 09 04:29:17 PM UTC 24 |
| Finished | Oct 09 04:30:50 PM UTC 24 |
| Peak memory | 266836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114661428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.114661428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_esc_intr_timeout.3816480266 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 425197416 ps |
| CPU time | 31.02 seconds |
| Started | Oct 09 04:29:14 PM UTC 24 |
| Finished | Oct 09 04:29:47 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816480266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3816480266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg.539715909 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 167164327858 ps |
| CPU time | 2644.39 seconds |
| Started | Oct 09 04:29:52 PM UTC 24 |
| Finished | Oct 09 05:14:27 PM UTC 24 |
| Peak memory | 293296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539715909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.539715909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_lpg_stub_clk.2311865263 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 37449116856 ps |
| CPU time | 2187.65 seconds |
| Started | Oct 09 04:29:56 PM UTC 24 |
| Finished | Oct 09 05:06:49 PM UTC 24 |
| Peak memory | 299528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311865263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2311865263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_ping_timeout.655934687 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 9500534868 ps |
| CPU time | 349.24 seconds |
| Started | Oct 09 04:29:48 PM UTC 24 |
| Finished | Oct 09 04:35:42 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655934687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.655934687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_alerts.1929970953 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4898894153 ps |
| CPU time | 26.02 seconds |
| Started | Oct 09 04:28:48 PM UTC 24 |
| Finished | Oct 09 04:29:15 PM UTC 24 |
| Peak memory | 266664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929970953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1929970953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_random_classes.467827327 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 846532766 ps |
| CPU time | 66.12 seconds |
| Started | Oct 09 04:29:14 PM UTC 24 |
| Finished | Oct 09 04:30:23 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467827327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.467827327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_sig_int_fail.235448872 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 950340564 ps |
| CPU time | 58.48 seconds |
| Started | Oct 09 04:29:25 PM UTC 24 |
| Finished | Oct 09 04:30:25 PM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235448872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.235448872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_smoke.2039884046 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 3416190846 ps |
| CPU time | 49.62 seconds |
| Started | Oct 09 04:28:34 PM UTC 24 |
| Finished | Oct 09 04:29:25 PM UTC 24 |
| Peak memory | 266664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039884046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2039884046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/12.alert_handler_stress_all.293019983 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 36681370960 ps |
| CPU time | 2563.51 seconds |
| Started | Oct 09 04:30:20 PM UTC 24 |
| Finished | Oct 09 05:13:34 PM UTC 24 |
| Peak memory | 299444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293019983 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_stress_all.293019983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/12.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_alert_accum_saturation.3997826276 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 370909582 ps |
| CPU time | 4.5 seconds |
| Started | Oct 09 04:33:52 PM UTC 24 |
| Finished | Oct 09 04:33:58 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997826276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3997826276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy.3893681394 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 36503480300 ps |
| CPU time | 983.74 seconds |
| Started | Oct 09 04:31:40 PM UTC 24 |
| Finished | Oct 09 04:48:16 PM UTC 24 |
| Peak memory | 293372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893681394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3893681394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_entropy_stress.4071361096 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 455300701 ps |
| CPU time | 15.21 seconds |
| Started | Oct 09 04:32:49 PM UTC 24 |
| Finished | Oct 09 04:33:05 PM UTC 24 |
| Peak memory | 260544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071361096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.4071361096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_alert_accum.2264017956 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 1016582030 ps |
| CPU time | 64.6 seconds |
| Started | Oct 09 04:31:14 PM UTC 24 |
| Finished | Oct 09 04:32:20 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264017956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2264017956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_esc_intr_timeout.3670428206 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 1318561273 ps |
| CPU time | 40.36 seconds |
| Started | Oct 09 04:30:58 PM UTC 24 |
| Finished | Oct 09 04:31:40 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670428206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3670428206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg.1568855331 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 61468637372 ps |
| CPU time | 1257.86 seconds |
| Started | Oct 09 04:32:22 PM UTC 24 |
| Finished | Oct 09 04:53:35 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568855331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1568855331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_lpg_stub_clk.3956379132 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 77491399562 ps |
| CPU time | 2564.29 seconds |
| Started | Oct 09 04:32:46 PM UTC 24 |
| Finished | Oct 09 05:15:59 PM UTC 24 |
| Peak memory | 299524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956379132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3956379132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_ping_timeout.142229184 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 12672153165 ps |
| CPU time | 578.62 seconds |
| Started | Oct 09 04:31:54 PM UTC 24 |
| Finished | Oct 09 04:41:41 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142229184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.142229184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_alerts.3502880161 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1212362156 ps |
| CPU time | 34.42 seconds |
| Started | Oct 09 04:30:37 PM UTC 24 |
| Finished | Oct 09 04:31:13 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502880161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3502880161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_random_classes.3365467428 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 29858527 ps |
| CPU time | 5.22 seconds |
| Started | Oct 09 04:30:51 PM UTC 24 |
| Finished | Oct 09 04:30:57 PM UTC 24 |
| Peak memory | 250328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365467428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3365467428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_sig_int_fail.46378272 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 674073930 ps |
| CPU time | 25.99 seconds |
| Started | Oct 09 04:31:26 PM UTC 24 |
| Finished | Oct 09 04:31:53 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46378272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.46378272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/13.alert_handler_smoke.3441757276 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 749527696 ps |
| CPU time | 53.49 seconds |
| Started | Oct 09 04:30:30 PM UTC 24 |
| Finished | Oct 09 04:31:25 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441757276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3441757276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/13.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_alert_accum_saturation.3910626802 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 31142263 ps |
| CPU time | 4.71 seconds |
| Started | Oct 09 04:36:07 PM UTC 24 |
| Finished | Oct 09 04:36:13 PM UTC 24 |
| Peak memory | 260872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910626802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3910626802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy.3172556846 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 195811240585 ps |
| CPU time | 3374.64 seconds |
| Started | Oct 09 04:34:42 PM UTC 24 |
| Finished | Oct 09 05:31:35 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172556846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3172556846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_entropy_stress.626474014 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1472684686 ps |
| CPU time | 27.21 seconds |
| Started | Oct 09 04:35:38 PM UTC 24 |
| Finished | Oct 09 04:36:07 PM UTC 24 |
| Peak memory | 260668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626474014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.626474014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_alert_accum.3480252928 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 13215735471 ps |
| CPU time | 96.22 seconds |
| Started | Oct 09 04:34:34 PM UTC 24 |
| Finished | Oct 09 04:36:12 PM UTC 24 |
| Peak memory | 266748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480252928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3480252928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_esc_intr_timeout.3166044971 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 157021057 ps |
| CPU time | 6.06 seconds |
| Started | Oct 09 04:34:34 PM UTC 24 |
| Finished | Oct 09 04:34:41 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166044971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3166044971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg.1057506406 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 312411702425 ps |
| CPU time | 1317.66 seconds |
| Started | Oct 09 04:35:19 PM UTC 24 |
| Finished | Oct 09 04:57:31 PM UTC 24 |
| Peak memory | 293500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057506406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1057506406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_lpg_stub_clk.1906898271 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 31013799119 ps |
| CPU time | 1983.97 seconds |
| Started | Oct 09 04:35:23 PM UTC 24 |
| Finished | Oct 09 05:08:50 PM UTC 24 |
| Peak memory | 297476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906898271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1906898271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_ping_timeout.370060557 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5865136005 ps |
| CPU time | 160.8 seconds |
| Started | Oct 09 04:35:01 PM UTC 24 |
| Finished | Oct 09 04:37:44 PM UTC 24 |
| Peak memory | 266880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370060557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.370060557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_random_alerts.1600504932 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 740862317 ps |
| CPU time | 18.23 seconds |
| Started | Oct 09 04:34:22 PM UTC 24 |
| Finished | Oct 09 04:34:41 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600504932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1600504932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_sig_int_fail.4021339433 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 2480339482 ps |
| CPU time | 37.96 seconds |
| Started | Oct 09 04:34:42 PM UTC 24 |
| Finished | Oct 09 04:35:22 PM UTC 24 |
| Peak memory | 266808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021339433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4021339433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/14.alert_handler_smoke.2449826490 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 155625026 ps |
| CPU time | 16.94 seconds |
| Started | Oct 09 04:34:02 PM UTC 24 |
| Finished | Oct 09 04:34:21 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449826490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2449826490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/14.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_alert_accum_saturation.2566741749 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 102474761 ps |
| CPU time | 4.85 seconds |
| Started | Oct 09 04:40:17 PM UTC 24 |
| Finished | Oct 09 04:40:23 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566741749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2566741749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy.625331747 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 12291598836 ps |
| CPU time | 1648.5 seconds |
| Started | Oct 09 04:38:32 PM UTC 24 |
| Finished | Oct 09 05:06:21 PM UTC 24 |
| Peak memory | 299520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625331747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.625331747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_entropy_stress.563368955 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 144221936 ps |
| CPU time | 13.53 seconds |
| Started | Oct 09 04:39:15 PM UTC 24 |
| Finished | Oct 09 04:39:30 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563368955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.563368955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_alert_accum.3631264907 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 905882234 ps |
| CPU time | 34.27 seconds |
| Started | Oct 09 04:37:56 PM UTC 24 |
| Finished | Oct 09 04:38:32 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631264907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3631264907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_esc_intr_timeout.3329436968 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 220088925 ps |
| CPU time | 6.98 seconds |
| Started | Oct 09 04:37:47 PM UTC 24 |
| Finished | Oct 09 04:37:55 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329436968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3329436968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_lpg_stub_clk.2070464529 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 126051057618 ps |
| CPU time | 2147.37 seconds |
| Started | Oct 09 04:38:58 PM UTC 24 |
| Finished | Oct 09 05:15:10 PM UTC 24 |
| Peak memory | 295364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070464529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2070464529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_ping_timeout.713934827 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4946715726 ps |
| CPU time | 223.8 seconds |
| Started | Oct 09 04:38:34 PM UTC 24 |
| Finished | Oct 09 04:42:22 PM UTC 24 |
| Peak memory | 260608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713934827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.713934827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_random_alerts.341712895 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 213075448 ps |
| CPU time | 22.33 seconds |
| Started | Oct 09 04:37:21 PM UTC 24 |
| Finished | Oct 09 04:37:45 PM UTC 24 |
| Peak memory | 266620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341712895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.341712895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_sig_int_fail.3689781829 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 217880005 ps |
| CPU time | 8.74 seconds |
| Started | Oct 09 04:38:24 PM UTC 24 |
| Finished | Oct 09 04:38:34 PM UTC 24 |
| Peak memory | 250296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689781829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3689781829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_smoke.1864149324 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 1265272065 ps |
| CPU time | 63.23 seconds |
| Started | Oct 09 04:36:15 PM UTC 24 |
| Finished | Oct 09 04:37:20 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864149324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1864149324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/15.alert_handler_stress_all.1535357877 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 2062691442 ps |
| CPU time | 78.4 seconds |
| Started | Oct 09 04:39:32 PM UTC 24 |
| Finished | Oct 09 04:40:52 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535357877 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_stress_all.1535357877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/15.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_alert_accum_saturation.3592044174 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 33070674 ps |
| CPU time | 5.17 seconds |
| Started | Oct 09 04:41:50 PM UTC 24 |
| Finished | Oct 09 04:41:56 PM UTC 24 |
| Peak memory | 260936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592044174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3592044174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy.4246538090 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 5341769700 ps |
| CPU time | 720.21 seconds |
| Started | Oct 09 04:41:05 PM UTC 24 |
| Finished | Oct 09 04:53:16 PM UTC 24 |
| Peak memory | 277116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246538090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4246538090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_entropy_stress.2302040231 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 149218800 ps |
| CPU time | 13.01 seconds |
| Started | Oct 09 04:41:42 PM UTC 24 |
| Finished | Oct 09 04:41:56 PM UTC 24 |
| Peak memory | 260544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302040231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2302040231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_alert_accum.2028557278 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1554527443 ps |
| CPU time | 119.02 seconds |
| Started | Oct 09 04:40:53 PM UTC 24 |
| Finished | Oct 09 04:42:54 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028557278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2028557278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_esc_intr_timeout.782966554 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 1329913214 ps |
| CPU time | 56.48 seconds |
| Started | Oct 09 04:40:51 PM UTC 24 |
| Finished | Oct 09 04:41:49 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782966554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.782966554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_lpg_stub_clk.3104763785 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 37708777223 ps |
| CPU time | 2799.35 seconds |
| Started | Oct 09 04:41:22 PM UTC 24 |
| Finished | Oct 09 05:28:34 PM UTC 24 |
| Peak memory | 302276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104763785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3104763785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_alerts.884319443 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 492336382 ps |
| CPU time | 26.52 seconds |
| Started | Oct 09 04:40:28 PM UTC 24 |
| Finished | Oct 09 04:40:56 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884319443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.884319443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_random_classes.1139879833 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 93346913 ps |
| CPU time | 16.42 seconds |
| Started | Oct 09 04:40:32 PM UTC 24 |
| Finished | Oct 09 04:40:50 PM UTC 24 |
| Peak memory | 266808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139879833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1139879833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_sig_int_fail.3882097414 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 262009660 ps |
| CPU time | 22.86 seconds |
| Started | Oct 09 04:40:57 PM UTC 24 |
| Finished | Oct 09 04:41:21 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882097414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3882097414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all.611808023 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 43169080577 ps |
| CPU time | 2173.5 seconds |
| Started | Oct 09 04:41:47 PM UTC 24 |
| Finished | Oct 09 05:18:28 PM UTC 24 |
| Peak memory | 315892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611808023 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_stress_all.611808023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/16.alert_handler_stress_all_with_rand_reset.2266103247 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 38478218234 ps |
| CPU time | 461.86 seconds |
| Started | Oct 09 04:41:57 PM UTC 24 |
| Finished | Oct 09 04:49:45 PM UTC 24 |
| Peak memory | 293492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2266103247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.a lert_handler_stress_all_with_rand_reset.2266103247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/16.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_alert_accum_saturation.1800297701 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 38511404 ps |
| CPU time | 4.24 seconds |
| Started | Oct 09 04:44:07 PM UTC 24 |
| Finished | Oct 09 04:44:12 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800297701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1800297701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy.1673244095 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 10405413694 ps |
| CPU time | 1523.66 seconds |
| Started | Oct 09 04:42:59 PM UTC 24 |
| Finished | Oct 09 05:08:41 PM UTC 24 |
| Peak memory | 299516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673244095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1673244095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_entropy_stress.3722393558 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 835274621 ps |
| CPU time | 18.83 seconds |
| Started | Oct 09 04:43:45 PM UTC 24 |
| Finished | Oct 09 04:44:06 PM UTC 24 |
| Peak memory | 260672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3722393558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3722393558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_alert_accum.2993444330 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 1230484820 ps |
| CPU time | 62.28 seconds |
| Started | Oct 09 04:42:59 PM UTC 24 |
| Finished | Oct 09 04:44:03 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993444330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2993444330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_esc_intr_timeout.2646736016 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 1238153711 ps |
| CPU time | 13.23 seconds |
| Started | Oct 09 04:42:53 PM UTC 24 |
| Finished | Oct 09 04:43:08 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646736016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2646736016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg.3931132165 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 119241962150 ps |
| CPU time | 1820.2 seconds |
| Started | Oct 09 04:43:07 PM UTC 24 |
| Finished | Oct 09 05:13:48 PM UTC 24 |
| Peak memory | 283136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931132165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3931132165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_lpg_stub_clk.961672796 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 18898129593 ps |
| CPU time | 665.33 seconds |
| Started | Oct 09 04:43:08 PM UTC 24 |
| Finished | Oct 09 04:54:23 PM UTC 24 |
| Peak memory | 283064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961672796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.961672796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_ping_timeout.3279309216 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 9888970345 ps |
| CPU time | 445.62 seconds |
| Started | Oct 09 04:43:00 PM UTC 24 |
| Finished | Oct 09 04:50:33 PM UTC 24 |
| Peak memory | 260612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279309216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3279309216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_alerts.1798070221 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4566192489 ps |
| CPU time | 34.87 seconds |
| Started | Oct 09 04:42:23 PM UTC 24 |
| Finished | Oct 09 04:43:00 PM UTC 24 |
| Peak memory | 266660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798070221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1798070221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_random_classes.3446141306 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 1082332259 ps |
| CPU time | 93.49 seconds |
| Started | Oct 09 04:42:47 PM UTC 24 |
| Finished | Oct 09 04:44:23 PM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446141306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3446141306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_sig_int_fail.3167601526 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 4252452638 ps |
| CPU time | 43.76 seconds |
| Started | Oct 09 04:42:59 PM UTC 24 |
| Finished | Oct 09 04:43:44 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167601526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3167601526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_smoke.3824539571 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2605366672 ps |
| CPU time | 54.01 seconds |
| Started | Oct 09 04:41:57 PM UTC 24 |
| Finished | Oct 09 04:42:52 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824539571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3824539571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/17.alert_handler_stress_all.3886924371 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 124474005566 ps |
| CPU time | 2271.27 seconds |
| Started | Oct 09 04:44:04 PM UTC 24 |
| Finished | Oct 09 05:22:22 PM UTC 24 |
| Peak memory | 283256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886924371 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_stress_all.3886924371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/17.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_alert_accum_saturation.1492328932 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 21219447 ps |
| CPU time | 3.66 seconds |
| Started | Oct 09 04:46:48 PM UTC 24 |
| Finished | Oct 09 04:46:53 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492328932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1492328932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy.2499025110 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 34171878072 ps |
| CPU time | 2071.52 seconds |
| Started | Oct 09 04:45:29 PM UTC 24 |
| Finished | Oct 09 05:20:27 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499025110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2499025110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_entropy_stress.255953710 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 478164023 ps |
| CPU time | 17.36 seconds |
| Started | Oct 09 04:45:56 PM UTC 24 |
| Finished | Oct 09 04:46:14 PM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255953710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.255953710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_alert_accum.1578079951 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 924452503 ps |
| CPU time | 38.89 seconds |
| Started | Oct 09 04:45:15 PM UTC 24 |
| Finished | Oct 09 04:45:55 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578079951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1578079951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_esc_intr_timeout.3543230787 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 943375731 ps |
| CPU time | 24.72 seconds |
| Started | Oct 09 04:45:13 PM UTC 24 |
| Finished | Oct 09 04:45:39 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543230787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3543230787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg.2012099705 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 65023675746 ps |
| CPU time | 1347.84 seconds |
| Started | Oct 09 04:45:40 PM UTC 24 |
| Finished | Oct 09 05:08:24 PM UTC 24 |
| Peak memory | 283260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012099705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2012099705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_lpg_stub_clk.3055390596 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 13979867523 ps |
| CPU time | 825.03 seconds |
| Started | Oct 09 04:45:54 PM UTC 24 |
| Finished | Oct 09 04:59:49 PM UTC 24 |
| Peak memory | 283140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055390596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3055390596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_alerts.2112107124 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 733169400 ps |
| CPU time | 22.8 seconds |
| Started | Oct 09 04:44:35 PM UTC 24 |
| Finished | Oct 09 04:44:59 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112107124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2112107124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_random_classes.4267022312 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 142421716 ps |
| CPU time | 9.67 seconds |
| Started | Oct 09 04:45:00 PM UTC 24 |
| Finished | Oct 09 04:45:11 PM UTC 24 |
| Peak memory | 260732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267022312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4267022312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_sig_int_fail.1498544458 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 482276894 ps |
| CPU time | 20.08 seconds |
| Started | Oct 09 04:45:18 PM UTC 24 |
| Finished | Oct 09 04:45:39 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498544458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1498544458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_smoke.3167804038 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 338943616 ps |
| CPU time | 48.17 seconds |
| Started | Oct 09 04:44:24 PM UTC 24 |
| Finished | Oct 09 04:45:14 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167804038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3167804038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/18.alert_handler_stress_all.3327880094 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 498907689 ps |
| CPU time | 54.6 seconds |
| Started | Oct 09 04:46:15 PM UTC 24 |
| Finished | Oct 09 04:47:11 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327880094 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_stress_all.3327880094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/18.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_alert_accum_saturation.4081290174 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 319934735 ps |
| CPU time | 4.09 seconds |
| Started | Oct 09 04:49:09 PM UTC 24 |
| Finished | Oct 09 04:49:14 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081290174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.4081290174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy.4141946326 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 32349092736 ps |
| CPU time | 1194.86 seconds |
| Started | Oct 09 04:48:33 PM UTC 24 |
| Finished | Oct 09 05:08:42 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141946326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.4141946326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_entropy_stress.3177204119 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 7684305437 ps |
| CPU time | 46.66 seconds |
| Started | Oct 09 04:48:58 PM UTC 24 |
| Finished | Oct 09 04:49:47 PM UTC 24 |
| Peak memory | 260740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177204119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3177204119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_alert_accum.2964398436 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 5805423182 ps |
| CPU time | 75.62 seconds |
| Started | Oct 09 04:47:56 PM UTC 24 |
| Finished | Oct 09 04:49:13 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964398436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2964398436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_esc_intr_timeout.1529992090 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1859133674 ps |
| CPU time | 84.92 seconds |
| Started | Oct 09 04:47:51 PM UTC 24 |
| Finished | Oct 09 04:49:18 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529992090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1529992090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_lpg_stub_clk.1242143469 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 29448399789 ps |
| CPU time | 1664.62 seconds |
| Started | Oct 09 04:48:51 PM UTC 24 |
| Finished | Oct 09 05:16:55 PM UTC 24 |
| Peak memory | 283072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242143469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1242143469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_ping_timeout.799551690 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 74359896923 ps |
| CPU time | 180.23 seconds |
| Started | Oct 09 04:48:39 PM UTC 24 |
| Finished | Oct 09 04:51:42 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799551690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.799551690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_alerts.2331202698 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 30327225 ps |
| CPU time | 5.04 seconds |
| Started | Oct 09 04:47:12 PM UTC 24 |
| Finished | Oct 09 04:47:19 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331202698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2331202698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_random_classes.717964993 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 264538605 ps |
| CPU time | 28.55 seconds |
| Started | Oct 09 04:47:20 PM UTC 24 |
| Finished | Oct 09 04:47:50 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717964993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.717964993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_sig_int_fail.3248100664 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 693983737 ps |
| CPU time | 17.43 seconds |
| Started | Oct 09 04:48:19 PM UTC 24 |
| Finished | Oct 09 04:48:37 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248100664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3248100664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/19.alert_handler_smoke.2406273225 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 1156883953 ps |
| CPU time | 99.03 seconds |
| Started | Oct 09 04:47:08 PM UTC 24 |
| Finished | Oct 09 04:48:50 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406273225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2406273225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/19.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_alert_accum_saturation.3042204268 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 34094388 ps |
| CPU time | 5.62 seconds |
| Started | Oct 09 04:16:57 PM UTC 24 |
| Finished | Oct 09 04:17:04 PM UTC 24 |
| Peak memory | 260728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042204268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3042204268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy.1157801246 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 15097346372 ps |
| CPU time | 1479.04 seconds |
| Started | Oct 09 04:16:48 PM UTC 24 |
| Finished | Oct 09 04:41:44 PM UTC 24 |
| Peak memory | 299520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157801246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1157801246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_entropy_stress.2128536197 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 262939084 ps |
| CPU time | 12.89 seconds |
| Started | Oct 09 04:16:55 PM UTC 24 |
| Finished | Oct 09 04:17:09 PM UTC 24 |
| Peak memory | 260472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128536197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2128536197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_alert_accum.1729872691 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 7254333989 ps |
| CPU time | 414.34 seconds |
| Started | Oct 09 04:16:45 PM UTC 24 |
| Finished | Oct 09 04:23:46 PM UTC 24 |
| Peak memory | 262836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729872691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1729872691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_esc_intr_timeout.3237977995 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 434662290 ps |
| CPU time | 42.07 seconds |
| Started | Oct 09 04:16:45 PM UTC 24 |
| Finished | Oct 09 04:17:29 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237977995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3237977995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_lpg_stub_clk.3321157247 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 31251293161 ps |
| CPU time | 1982.42 seconds |
| Started | Oct 09 04:16:53 PM UTC 24 |
| Finished | Oct 09 04:50:20 PM UTC 24 |
| Peak memory | 283264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321157247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3321157247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_ping_timeout.1359742513 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 7400784862 ps |
| CPU time | 270.71 seconds |
| Started | Oct 09 04:16:52 PM UTC 24 |
| Finished | Oct 09 04:21:26 PM UTC 24 |
| Peak memory | 260736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359742513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1359742513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_alerts.2843897212 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 147797277 ps |
| CPU time | 16.54 seconds |
| Started | Oct 09 04:16:44 PM UTC 24 |
| Finished | Oct 09 04:17:02 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843897212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2843897212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_random_classes.229061587 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 4944181243 ps |
| CPU time | 67.7 seconds |
| Started | Oct 09 04:16:44 PM UTC 24 |
| Finished | Oct 09 04:17:54 PM UTC 24 |
| Peak memory | 266936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229061587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.229061587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_smoke.1247471125 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 169045422 ps |
| CPU time | 12.61 seconds |
| Started | Oct 09 04:16:42 PM UTC 24 |
| Finished | Oct 09 04:16:56 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247471125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1247471125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/2.alert_handler_stress_all.3834805071 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 230245705281 ps |
| CPU time | 3707.56 seconds |
| Started | Oct 09 04:16:56 PM UTC 24 |
| Finished | Oct 09 05:19:26 PM UTC 24 |
| Peak memory | 312236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834805071 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all.3834805071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/2.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_entropy.1113806932 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 214988385236 ps |
| CPU time | 3082.44 seconds |
| Started | Oct 09 04:49:46 PM UTC 24 |
| Finished | Oct 09 05:41:46 PM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113806932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1113806932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_alert_accum.1698393355 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 909072614 ps |
| CPU time | 79.3 seconds |
| Started | Oct 09 04:49:36 PM UTC 24 |
| Finished | Oct 09 04:50:57 PM UTC 24 |
| Peak memory | 266808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698393355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1698393355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_esc_intr_timeout.812599004 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 89575576 ps |
| CPU time | 6.33 seconds |
| Started | Oct 09 04:49:28 PM UTC 24 |
| Finished | Oct 09 04:49:35 PM UTC 24 |
| Peak memory | 250228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812599004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.812599004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg.400712248 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 15709289053 ps |
| CPU time | 1147.19 seconds |
| Started | Oct 09 04:49:48 PM UTC 24 |
| Finished | Oct 09 05:09:09 PM UTC 24 |
| Peak memory | 293372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400712248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.400712248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_lpg_stub_clk.147383398 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 20603172684 ps |
| CPU time | 912.97 seconds |
| Started | Oct 09 04:50:06 PM UTC 24 |
| Finished | Oct 09 05:05:31 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147383398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.147383398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_ping_timeout.2663259894 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 2106588820 ps |
| CPU time | 140.69 seconds |
| Started | Oct 09 04:49:47 PM UTC 24 |
| Finished | Oct 09 04:52:11 PM UTC 24 |
| Peak memory | 260472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663259894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2663259894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_alerts.822117301 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 78656644 ps |
| CPU time | 7.62 seconds |
| Started | Oct 09 04:49:18 PM UTC 24 |
| Finished | Oct 09 04:49:27 PM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822117301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.822117301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_random_classes.4163308231 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 3291858390 ps |
| CPU time | 68.79 seconds |
| Started | Oct 09 04:49:24 PM UTC 24 |
| Finished | Oct 09 04:50:34 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163308231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.4163308231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_sig_int_fail.4096405740 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 214177296 ps |
| CPU time | 9.31 seconds |
| Started | Oct 09 04:49:37 PM UTC 24 |
| Finished | Oct 09 04:49:47 PM UTC 24 |
| Peak memory | 264632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096405740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4096405740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/20.alert_handler_smoke.417503606 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 5085722083 ps |
| CPU time | 77.83 seconds |
| Started | Oct 09 04:49:15 PM UTC 24 |
| Finished | Oct 09 04:50:35 PM UTC 24 |
| Peak memory | 266748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417503606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.417503606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/20.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_entropy.2510796737 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 27085492585 ps |
| CPU time | 1731.38 seconds |
| Started | Oct 09 04:51:07 PM UTC 24 |
| Finished | Oct 09 05:20:19 PM UTC 24 |
| Peak memory | 283260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510796737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2510796737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_alert_accum.1064060951 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 2545628347 ps |
| CPU time | 76.6 seconds |
| Started | Oct 09 04:50:56 PM UTC 24 |
| Finished | Oct 09 04:52:15 PM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064060951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1064060951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_esc_intr_timeout.1043968416 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 957689583 ps |
| CPU time | 24.75 seconds |
| Started | Oct 09 04:50:53 PM UTC 24 |
| Finished | Oct 09 04:51:20 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043968416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1043968416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg.1176793320 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 7738176105 ps |
| CPU time | 991.29 seconds |
| Started | Oct 09 04:51:24 PM UTC 24 |
| Finished | Oct 09 05:08:08 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176793320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1176793320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_lpg_stub_clk.354970823 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 81588000574 ps |
| CPU time | 1400.24 seconds |
| Started | Oct 09 04:51:43 PM UTC 24 |
| Finished | Oct 09 05:15:21 PM UTC 24 |
| Peak memory | 279168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354970823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.354970823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_ping_timeout.1381558602 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 24381767944 ps |
| CPU time | 444.66 seconds |
| Started | Oct 09 04:51:21 PM UTC 24 |
| Finished | Oct 09 04:58:51 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381558602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1381558602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_alerts.1657876349 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 6089727671 ps |
| CPU time | 46.08 seconds |
| Started | Oct 09 04:50:35 PM UTC 24 |
| Finished | Oct 09 04:51:23 PM UTC 24 |
| Peak memory | 266736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657876349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1657876349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_random_classes.61443033 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 173564596 ps |
| CPU time | 17.56 seconds |
| Started | Oct 09 04:50:36 PM UTC 24 |
| Finished | Oct 09 04:50:55 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61443033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.61443033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_smoke.1341836797 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 452057455 ps |
| CPU time | 17.19 seconds |
| Started | Oct 09 04:50:34 PM UTC 24 |
| Finished | Oct 09 04:50:52 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341836797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1341836797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all.2487931052 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 188384787465 ps |
| CPU time | 1611.17 seconds |
| Started | Oct 09 04:51:59 PM UTC 24 |
| Finished | Oct 09 05:19:10 PM UTC 24 |
| Peak memory | 299508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487931052 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_stress_all.2487931052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/21.alert_handler_stress_all_with_rand_reset.1127038739 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 14374226412 ps |
| CPU time | 489.78 seconds |
| Started | Oct 09 04:52:12 PM UTC 24 |
| Finished | Oct 09 05:00:28 PM UTC 24 |
| Peak memory | 281332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1127038739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.a lert_handler_stress_all_with_rand_reset.1127038739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/21.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_entropy.1288972423 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 11081345840 ps |
| CPU time | 721.78 seconds |
| Started | Oct 09 04:53:48 PM UTC 24 |
| Finished | Oct 09 05:05:59 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288972423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1288972423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_alert_accum.501524213 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 4461797054 ps |
| CPU time | 123.28 seconds |
| Started | Oct 09 04:53:25 PM UTC 24 |
| Finished | Oct 09 04:55:31 PM UTC 24 |
| Peak memory | 266776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501524213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.501524213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_esc_intr_timeout.2566879350 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 4104900915 ps |
| CPU time | 79.01 seconds |
| Started | Oct 09 04:53:17 PM UTC 24 |
| Finished | Oct 09 04:54:38 PM UTC 24 |
| Peak memory | 260732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566879350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2566879350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg.892102561 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 130551018240 ps |
| CPU time | 2328.67 seconds |
| Started | Oct 09 04:54:24 PM UTC 24 |
| Finished | Oct 09 05:33:41 PM UTC 24 |
| Peak memory | 285820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892102561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.892102561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_lpg_stub_clk.1211893855 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 8276828811 ps |
| CPU time | 1104.39 seconds |
| Started | Oct 09 04:54:27 PM UTC 24 |
| Finished | Oct 09 05:13:05 PM UTC 24 |
| Peak memory | 283140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211893855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1211893855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_random_alerts.384137004 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 956774219 ps |
| CPU time | 17.48 seconds |
| Started | Oct 09 04:52:32 PM UTC 24 |
| Finished | Oct 09 04:52:51 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384137004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.384137004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_sig_int_fail.558700491 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2078286544 ps |
| CPU time | 54.67 seconds |
| Started | Oct 09 04:53:36 PM UTC 24 |
| Finished | Oct 09 04:54:33 PM UTC 24 |
| Peak memory | 266844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558700491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.558700491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_smoke.3887500906 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4204740002 ps |
| CPU time | 65.21 seconds |
| Started | Oct 09 04:52:17 PM UTC 24 |
| Finished | Oct 09 04:53:24 PM UTC 24 |
| Peak memory | 260724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887500906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3887500906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all.400412103 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 7286392798 ps |
| CPU time | 281.79 seconds |
| Started | Oct 09 04:54:27 PM UTC 24 |
| Finished | Oct 09 04:59:13 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400412103 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_stress_all.400412103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/22.alert_handler_stress_all_with_rand_reset.1424434085 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 19654424626 ps |
| CPU time | 492.75 seconds |
| Started | Oct 09 04:54:34 PM UTC 24 |
| Finished | Oct 09 05:02:53 PM UTC 24 |
| Peak memory | 293492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1424434085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.a lert_handler_stress_all_with_rand_reset.1424434085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/22.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_alert_accum.523599806 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 6784350985 ps |
| CPU time | 183.54 seconds |
| Started | Oct 09 04:55:32 PM UTC 24 |
| Finished | Oct 09 04:58:39 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523599806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.523599806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_esc_intr_timeout.3789581420 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2880857891 ps |
| CPU time | 36.75 seconds |
| Started | Oct 09 04:55:20 PM UTC 24 |
| Finished | Oct 09 04:55:58 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789581420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3789581420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg.3124831214 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 122180762512 ps |
| CPU time | 1606.58 seconds |
| Started | Oct 09 04:55:58 PM UTC 24 |
| Finished | Oct 09 05:23:05 PM UTC 24 |
| Peak memory | 299516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124831214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3124831214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_lpg_stub_clk.4027386106 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 22721320993 ps |
| CPU time | 1478.7 seconds |
| Started | Oct 09 04:56:06 PM UTC 24 |
| Finished | Oct 09 05:21:02 PM UTC 24 |
| Peak memory | 283064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027386106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4027386106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_ping_timeout.2291123248 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4458680814 ps |
| CPU time | 117.21 seconds |
| Started | Oct 09 04:55:50 PM UTC 24 |
| Finished | Oct 09 04:57:50 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291123248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2291123248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_alerts.24097693 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 393901932 ps |
| CPU time | 25.71 seconds |
| Started | Oct 09 04:55:04 PM UTC 24 |
| Finished | Oct 09 04:55:31 PM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24097693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.24097693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_random_classes.110613843 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 562091387 ps |
| CPU time | 46.42 seconds |
| Started | Oct 09 04:55:15 PM UTC 24 |
| Finished | Oct 09 04:56:03 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110613843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.110613843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_sig_int_fail.905975002 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 113705746 ps |
| CPU time | 7.42 seconds |
| Started | Oct 09 04:55:32 PM UTC 24 |
| Finished | Oct 09 04:55:41 PM UTC 24 |
| Peak memory | 250332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905975002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.905975002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_smoke.511083558 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1299334262 ps |
| CPU time | 68.3 seconds |
| Started | Oct 09 04:54:39 PM UTC 24 |
| Finished | Oct 09 04:55:49 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511083558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.511083558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/23.alert_handler_stress_all.3455607146 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 12298065330 ps |
| CPU time | 1528.65 seconds |
| Started | Oct 09 04:56:06 PM UTC 24 |
| Finished | Oct 09 05:21:53 PM UTC 24 |
| Peak memory | 299636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455607146 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_stress_all.3455607146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/23.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_entropy.67176948 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 139607999876 ps |
| CPU time | 2262.6 seconds |
| Started | Oct 09 04:58:40 PM UTC 24 |
| Finished | Oct 09 05:36:49 PM UTC 24 |
| Peak memory | 296064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67176948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.67176948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_alert_accum.3024280652 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2336647030 ps |
| CPU time | 57.88 seconds |
| Started | Oct 09 04:58:20 PM UTC 24 |
| Finished | Oct 09 04:59:20 PM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024280652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3024280652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_esc_intr_timeout.551371020 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 868348944 ps |
| CPU time | 33.6 seconds |
| Started | Oct 09 04:58:00 PM UTC 24 |
| Finished | Oct 09 04:58:35 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551371020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.551371020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_lpg_stub_clk.4243697076 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 30587649507 ps |
| CPU time | 2045.56 seconds |
| Started | Oct 09 04:59:14 PM UTC 24 |
| Finished | Oct 09 05:33:44 PM UTC 24 |
| Peak memory | 295864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243697076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4243697076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_ping_timeout.1196482025 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 16779474243 ps |
| CPU time | 379.89 seconds |
| Started | Oct 09 04:58:52 PM UTC 24 |
| Finished | Oct 09 05:05:17 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196482025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1196482025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_alerts.3404932852 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 217037856 ps |
| CPU time | 7.31 seconds |
| Started | Oct 09 04:57:51 PM UTC 24 |
| Finished | Oct 09 04:57:59 PM UTC 24 |
| Peak memory | 260720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404932852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3404932852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_random_classes.578861672 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 666068188 ps |
| CPU time | 66.9 seconds |
| Started | Oct 09 04:58:00 PM UTC 24 |
| Finished | Oct 09 04:59:09 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578861672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.578861672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_smoke.3334370356 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 978702697 ps |
| CPU time | 23.55 seconds |
| Started | Oct 09 04:57:34 PM UTC 24 |
| Finished | Oct 09 04:57:59 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334370356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3334370356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all.3051383812 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 25023846200 ps |
| CPU time | 1444.54 seconds |
| Started | Oct 09 04:59:21 PM UTC 24 |
| Finished | Oct 09 05:23:43 PM UTC 24 |
| Peak memory | 299508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051383812 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_stress_all.3051383812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/24.alert_handler_stress_all_with_rand_reset.23289917 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 7803949795 ps |
| CPU time | 214.98 seconds |
| Started | Oct 09 04:59:22 PM UTC 24 |
| Finished | Oct 09 05:03:00 PM UTC 24 |
| Peak memory | 277040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=23289917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.ale rt_handler_stress_all_with_rand_reset.23289917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/24.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_entropy.1268584276 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 23470400556 ps |
| CPU time | 1679.72 seconds |
| Started | Oct 09 05:00:30 PM UTC 24 |
| Finished | Oct 09 05:28:49 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268584276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1268584276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_alert_accum.222082729 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 8258759389 ps |
| CPU time | 183.98 seconds |
| Started | Oct 09 05:00:14 PM UTC 24 |
| Finished | Oct 09 05:03:21 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222082729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.222082729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_esc_intr_timeout.3391554863 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 4322505070 ps |
| CPU time | 53.75 seconds |
| Started | Oct 09 05:00:10 PM UTC 24 |
| Finished | Oct 09 05:01:06 PM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391554863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3391554863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg.1893348986 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 41791770926 ps |
| CPU time | 1803.19 seconds |
| Started | Oct 09 05:01:06 PM UTC 24 |
| Finished | Oct 09 05:31:31 PM UTC 24 |
| Peak memory | 299452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893348986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1893348986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_lpg_stub_clk.3667112591 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 24202786727 ps |
| CPU time | 1599.01 seconds |
| Started | Oct 09 05:01:08 PM UTC 24 |
| Finished | Oct 09 05:28:06 PM UTC 24 |
| Peak memory | 283204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667112591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3667112591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_ping_timeout.996074965 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 10270126918 ps |
| CPU time | 517.25 seconds |
| Started | Oct 09 05:00:36 PM UTC 24 |
| Finished | Oct 09 05:09:20 PM UTC 24 |
| Peak memory | 260740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996074965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.996074965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_alerts.2535314268 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1171928080 ps |
| CPU time | 44.69 seconds |
| Started | Oct 09 04:59:49 PM UTC 24 |
| Finished | Oct 09 05:00:35 PM UTC 24 |
| Peak memory | 266800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535314268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2535314268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_random_classes.1119940006 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 10945040433 ps |
| CPU time | 73.85 seconds |
| Started | Oct 09 04:59:51 PM UTC 24 |
| Finished | Oct 09 05:01:07 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119940006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1119940006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_sig_int_fail.3091545005 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 1916984385 ps |
| CPU time | 43.37 seconds |
| Started | Oct 09 05:00:21 PM UTC 24 |
| Finished | Oct 09 05:01:06 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091545005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3091545005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_smoke.3304429525 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 209693517 ps |
| CPU time | 16.37 seconds |
| Started | Oct 09 04:59:31 PM UTC 24 |
| Finished | Oct 09 04:59:48 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304429525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3304429525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all.1474528604 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 25086293119 ps |
| CPU time | 1516.75 seconds |
| Started | Oct 09 05:01:08 PM UTC 24 |
| Finished | Oct 09 05:26:42 PM UTC 24 |
| Peak memory | 283252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474528604 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_stress_all.1474528604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/25.alert_handler_stress_all_with_rand_reset.3979338403 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 11197785704 ps |
| CPU time | 186.08 seconds |
| Started | Oct 09 05:01:18 PM UTC 24 |
| Finished | Oct 09 05:04:28 PM UTC 24 |
| Peak memory | 277108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3979338403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.a lert_handler_stress_all_with_rand_reset.3979338403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/25.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_entropy.496279882 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 45151267628 ps |
| CPU time | 1192.72 seconds |
| Started | Oct 09 05:03:27 PM UTC 24 |
| Finished | Oct 09 05:23:34 PM UTC 24 |
| Peak memory | 295356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496279882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.496279882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_alert_accum.3861290901 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 16698048359 ps |
| CPU time | 308.7 seconds |
| Started | Oct 09 05:03:22 PM UTC 24 |
| Finished | Oct 09 05:08:35 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861290901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3861290901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_esc_intr_timeout.4235291983 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3716734574 ps |
| CPU time | 44.17 seconds |
| Started | Oct 09 05:03:21 PM UTC 24 |
| Finished | Oct 09 05:04:07 PM UTC 24 |
| Peak memory | 266940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235291983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4235291983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg.1982732637 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 123369878396 ps |
| CPU time | 1519.85 seconds |
| Started | Oct 09 05:03:51 PM UTC 24 |
| Finished | Oct 09 05:29:28 PM UTC 24 |
| Peak memory | 299444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982732637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1982732637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_lpg_stub_clk.332983099 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 11332696496 ps |
| CPU time | 1123.91 seconds |
| Started | Oct 09 05:04:07 PM UTC 24 |
| Finished | Oct 09 05:23:06 PM UTC 24 |
| Peak memory | 283204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332983099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.332983099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_ping_timeout.3774620328 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 46512993593 ps |
| CPU time | 701.68 seconds |
| Started | Oct 09 05:03:37 PM UTC 24 |
| Finished | Oct 09 05:15:28 PM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774620328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3774620328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_alerts.3116938425 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 969827628 ps |
| CPU time | 23.66 seconds |
| Started | Oct 09 05:02:56 PM UTC 24 |
| Finished | Oct 09 05:03:21 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116938425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3116938425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_random_classes.1654058662 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3532935418 ps |
| CPU time | 62.26 seconds |
| Started | Oct 09 05:03:01 PM UTC 24 |
| Finished | Oct 09 05:04:05 PM UTC 24 |
| Peak memory | 260604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654058662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1654058662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_sig_int_fail.2243952150 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 293028357 ps |
| CPU time | 25.4 seconds |
| Started | Oct 09 05:03:24 PM UTC 24 |
| Finished | Oct 09 05:03:50 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243952150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2243952150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_smoke.3672369042 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1091502257 ps |
| CPU time | 25.87 seconds |
| Started | Oct 09 05:02:56 PM UTC 24 |
| Finished | Oct 09 05:03:23 PM UTC 24 |
| Peak memory | 264820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672369042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3672369042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/26.alert_handler_stress_all.2869262638 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 57961418130 ps |
| CPU time | 3606.31 seconds |
| Started | Oct 09 05:04:08 PM UTC 24 |
| Finished | Oct 09 06:04:56 PM UTC 24 |
| Peak memory | 318228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869262638 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_stress_all.2869262638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/26.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_entropy.4025378147 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 18167237406 ps |
| CPU time | 992.42 seconds |
| Started | Oct 09 05:05:48 PM UTC 24 |
| Finished | Oct 09 05:22:33 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025378147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.4025378147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_alert_accum.3016070741 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 4266270179 ps |
| CPU time | 149.59 seconds |
| Started | Oct 09 05:05:33 PM UTC 24 |
| Finished | Oct 09 05:08:06 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016070741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3016070741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_esc_intr_timeout.141605873 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 253668827 ps |
| CPU time | 6.41 seconds |
| Started | Oct 09 05:05:31 PM UTC 24 |
| Finished | Oct 09 05:05:39 PM UTC 24 |
| Peak memory | 250220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141605873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.141605873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg.1047448096 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 37629886655 ps |
| CPU time | 894.13 seconds |
| Started | Oct 09 05:06:10 PM UTC 24 |
| Finished | Oct 09 05:21:15 PM UTC 24 |
| Peak memory | 276992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047448096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1047448096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_lpg_stub_clk.1299692091 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 154812758703 ps |
| CPU time | 2801.47 seconds |
| Started | Oct 09 05:06:12 PM UTC 24 |
| Finished | Oct 09 05:53:25 PM UTC 24 |
| Peak memory | 297912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299692091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.1299692091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_ping_timeout.725160602 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 32983245967 ps |
| CPU time | 319.29 seconds |
| Started | Oct 09 05:06:01 PM UTC 24 |
| Finished | Oct 09 05:11:24 PM UTC 24 |
| Peak memory | 260608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725160602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.725160602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_alerts.548198030 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 574340241 ps |
| CPU time | 51.8 seconds |
| Started | Oct 09 05:05:15 PM UTC 24 |
| Finished | Oct 09 05:06:09 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548198030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.548198030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_random_classes.2409394475 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 651115664 ps |
| CPU time | 27 seconds |
| Started | Oct 09 05:05:18 PM UTC 24 |
| Finished | Oct 09 05:05:47 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409394475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2409394475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_sig_int_fail.3417029402 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3715122996 ps |
| CPU time | 30.47 seconds |
| Started | Oct 09 05:05:40 PM UTC 24 |
| Finished | Oct 09 05:06:11 PM UTC 24 |
| Peak memory | 260600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417029402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3417029402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_smoke.2579277926 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 1840587930 ps |
| CPU time | 43.91 seconds |
| Started | Oct 09 05:04:29 PM UTC 24 |
| Finished | Oct 09 05:05:14 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2579277926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2579277926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/27.alert_handler_stress_all.578092588 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 56484740815 ps |
| CPU time | 1032.14 seconds |
| Started | Oct 09 05:06:23 PM UTC 24 |
| Finished | Oct 09 05:23:47 PM UTC 24 |
| Peak memory | 283052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578092588 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_stress_all.578092588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/27.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_entropy.3345967096 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 30083361114 ps |
| CPU time | 2282.77 seconds |
| Started | Oct 09 05:08:07 PM UTC 24 |
| Finished | Oct 09 05:46:38 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345967096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3345967096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_alert_accum.1820979253 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 4234023683 ps |
| CPU time | 237.65 seconds |
| Started | Oct 09 05:07:31 PM UTC 24 |
| Finished | Oct 09 05:11:33 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820979253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1820979253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_esc_intr_timeout.2564348 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 761341767 ps |
| CPU time | 28.32 seconds |
| Started | Oct 09 05:07:14 PM UTC 24 |
| Finished | Oct 09 05:07:44 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_ intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2564348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg.1304096520 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 151695833975 ps |
| CPU time | 2506.33 seconds |
| Started | Oct 09 05:08:15 PM UTC 24 |
| Finished | Oct 09 05:50:32 PM UTC 24 |
| Peak memory | 285692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304096520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1304096520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_lpg_stub_clk.601005874 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 15119136514 ps |
| CPU time | 1279.58 seconds |
| Started | Oct 09 05:08:26 PM UTC 24 |
| Finished | Oct 09 05:30:02 PM UTC 24 |
| Peak memory | 299648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601005874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.601005874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_ping_timeout.1429085852 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 42952077483 ps |
| CPU time | 78.58 seconds |
| Started | Oct 09 05:08:10 PM UTC 24 |
| Finished | Oct 09 05:09:31 PM UTC 24 |
| Peak memory | 260744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429085852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1429085852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_random_classes.2630567556 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 179368219 ps |
| CPU time | 5.5 seconds |
| Started | Oct 09 05:07:06 PM UTC 24 |
| Finished | Oct 09 05:07:13 PM UTC 24 |
| Peak memory | 250428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630567556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2630567556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_sig_int_fail.80981171 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 162845235 ps |
| CPU time | 28.05 seconds |
| Started | Oct 09 05:07:45 PM UTC 24 |
| Finished | Oct 09 05:08:14 PM UTC 24 |
| Peak memory | 260472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80981171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig _int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.80981171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_smoke.2210878758 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 854205293 ps |
| CPU time | 23.62 seconds |
| Started | Oct 09 05:06:40 PM UTC 24 |
| Finished | Oct 09 05:07:05 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210878758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2210878758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all.4248879897 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 533189158 ps |
| CPU time | 60.66 seconds |
| Started | Oct 09 05:08:34 PM UTC 24 |
| Finished | Oct 09 05:09:37 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248879897 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_stress_all.4248879897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/28.alert_handler_stress_all_with_rand_reset.4120115288 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 3139718679 ps |
| CPU time | 267.22 seconds |
| Started | Oct 09 05:08:36 PM UTC 24 |
| Finished | Oct 09 05:13:07 PM UTC 24 |
| Peak memory | 277108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4120115288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.a lert_handler_stress_all_with_rand_reset.4120115288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/28.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_entropy.934317297 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 50976494540 ps |
| CPU time | 705.54 seconds |
| Started | Oct 09 05:09:21 PM UTC 24 |
| Finished | Oct 09 05:21:16 PM UTC 24 |
| Peak memory | 277120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934317297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.934317297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_alert_accum.1385191506 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 6351095241 ps |
| CPU time | 204.64 seconds |
| Started | Oct 09 05:09:12 PM UTC 24 |
| Finished | Oct 09 05:12:40 PM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385191506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.1385191506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_esc_intr_timeout.2581123413 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 813987434 ps |
| CPU time | 26.22 seconds |
| Started | Oct 09 05:09:12 PM UTC 24 |
| Finished | Oct 09 05:09:39 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581123413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2581123413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg.1103083172 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 30820318707 ps |
| CPU time | 1613.02 seconds |
| Started | Oct 09 05:09:36 PM UTC 24 |
| Finished | Oct 09 05:36:49 PM UTC 24 |
| Peak memory | 299652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103083172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.1103083172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_lpg_stub_clk.2694622341 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 31250390733 ps |
| CPU time | 2728.97 seconds |
| Started | Oct 09 05:09:38 PM UTC 24 |
| Finished | Oct 09 05:55:38 PM UTC 24 |
| Peak memory | 302008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694622341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2694622341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_alerts.4160364332 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 960853034 ps |
| CPU time | 24.97 seconds |
| Started | Oct 09 05:08:45 PM UTC 24 |
| Finished | Oct 09 05:09:11 PM UTC 24 |
| Peak memory | 260656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160364332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4160364332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_random_classes.2955959716 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1050194305 ps |
| CPU time | 19 seconds |
| Started | Oct 09 05:08:52 PM UTC 24 |
| Finished | Oct 09 05:09:12 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955959716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2955959716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_sig_int_fail.2913987498 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 109441508 ps |
| CPU time | 19.99 seconds |
| Started | Oct 09 05:09:13 PM UTC 24 |
| Finished | Oct 09 05:09:34 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913987498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2913987498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_smoke.1466153277 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 3453099401 ps |
| CPU time | 62.55 seconds |
| Started | Oct 09 05:08:44 PM UTC 24 |
| Finished | Oct 09 05:09:49 PM UTC 24 |
| Peak memory | 266664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466153277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1466153277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all.1458631541 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 3434368970 ps |
| CPU time | 149.47 seconds |
| Started | Oct 09 05:09:40 PM UTC 24 |
| Finished | Oct 09 05:12:12 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458631541 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_stress_all.1458631541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/29.alert_handler_stress_all_with_rand_reset.93090753 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4067595555 ps |
| CPU time | 387.43 seconds |
| Started | Oct 09 05:09:50 PM UTC 24 |
| Finished | Oct 09 05:16:23 PM UTC 24 |
| Peak memory | 283184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=93090753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.ale rt_handler_stress_all_with_rand_reset.93090753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/29.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_alert_accum_saturation.408168935 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 60718038 ps |
| CPU time | 3.43 seconds |
| Started | Oct 09 04:17:29 PM UTC 24 |
| Finished | Oct 09 04:17:34 PM UTC 24 |
| Peak memory | 260736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408168935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.408168935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy.2033653150 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 73385211932 ps |
| CPU time | 2429.39 seconds |
| Started | Oct 09 04:17:22 PM UTC 24 |
| Finished | Oct 09 04:58:19 PM UTC 24 |
| Peak memory | 299448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033653150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2033653150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_entropy_stress.3071379986 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 223062533 ps |
| CPU time | 12.7 seconds |
| Started | Oct 09 04:17:24 PM UTC 24 |
| Finished | Oct 09 04:17:38 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071379986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3071379986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_alert_accum.2834743330 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 5488905230 ps |
| CPU time | 321.3 seconds |
| Started | Oct 09 04:17:19 PM UTC 24 |
| Finished | Oct 09 04:22:45 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834743330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2834743330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_esc_intr_timeout.1099811457 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 314756456 ps |
| CPU time | 26.36 seconds |
| Started | Oct 09 04:17:18 PM UTC 24 |
| Finished | Oct 09 04:17:46 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099811457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1099811457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_lpg_stub_clk.4197554704 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 49239136554 ps |
| CPU time | 2909.55 seconds |
| Started | Oct 09 04:17:24 PM UTC 24 |
| Finished | Oct 09 05:06:27 PM UTC 24 |
| Peak memory | 299648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197554704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4197554704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_random_alerts.3737609837 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 149732781 ps |
| CPU time | 10.98 seconds |
| Started | Oct 09 04:17:10 PM UTC 24 |
| Finished | Oct 09 04:17:22 PM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737609837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3737609837 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_sec_cm.3474725925 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 875970024 ps |
| CPU time | 21.11 seconds |
| Started | Oct 09 04:17:35 PM UTC 24 |
| Finished | Oct 09 04:17:57 PM UTC 24 |
| Peak memory | 294816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474725925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3474725925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_smoke.3939722890 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4786492190 ps |
| CPU time | 49.92 seconds |
| Started | Oct 09 04:17:06 PM UTC 24 |
| Finished | Oct 09 04:17:57 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939722890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3939722890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all.3058577060 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 67773442832 ps |
| CPU time | 971.11 seconds |
| Started | Oct 09 04:17:27 PM UTC 24 |
| Finished | Oct 09 04:33:51 PM UTC 24 |
| Peak memory | 277172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058577060 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all.3058577060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/3.alert_handler_stress_all_with_rand_reset.4150060374 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 13410438590 ps |
| CPU time | 460.38 seconds |
| Started | Oct 09 04:17:31 PM UTC 24 |
| Finished | Oct 09 04:25:17 PM UTC 24 |
| Peak memory | 281332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4150060374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.al ert_handler_stress_all_with_rand_reset.4150060374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_entropy.202182819 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 309629193330 ps |
| CPU time | 1912.98 seconds |
| Started | Oct 09 05:11:17 PM UTC 24 |
| Finished | Oct 09 05:43:31 PM UTC 24 |
| Peak memory | 285620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202182819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.202182819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_alert_accum.1398629753 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 6365853039 ps |
| CPU time | 147.25 seconds |
| Started | Oct 09 05:10:47 PM UTC 24 |
| Finished | Oct 09 05:13:17 PM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398629753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1398629753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_esc_intr_timeout.3766686330 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 187804377 ps |
| CPU time | 19.89 seconds |
| Started | Oct 09 05:10:29 PM UTC 24 |
| Finished | Oct 09 05:10:50 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766686330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3766686330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_lpg_stub_clk.2040032102 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 136115417558 ps |
| CPU time | 1853.18 seconds |
| Started | Oct 09 05:11:33 PM UTC 24 |
| Finished | Oct 09 05:42:47 PM UTC 24 |
| Peak memory | 284444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040032102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2040032102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_ping_timeout.1567465454 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 10571500292 ps |
| CPU time | 252.48 seconds |
| Started | Oct 09 05:11:25 PM UTC 24 |
| Finished | Oct 09 05:15:41 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567465454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1567465454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_alerts.3824579159 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 1642251913 ps |
| CPU time | 76.98 seconds |
| Started | Oct 09 05:10:12 PM UTC 24 |
| Finished | Oct 09 05:11:31 PM UTC 24 |
| Peak memory | 266600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824579159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3824579159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_random_classes.1826824424 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 870500689 ps |
| CPU time | 49.43 seconds |
| Started | Oct 09 05:10:24 PM UTC 24 |
| Finished | Oct 09 05:11:16 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826824424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1826824424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_smoke.3545377817 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 1211628222 ps |
| CPU time | 28.49 seconds |
| Started | Oct 09 05:09:58 PM UTC 24 |
| Finished | Oct 09 05:10:28 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545377817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3545377817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all.2644704350 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 24997541993 ps |
| CPU time | 1748.41 seconds |
| Started | Oct 09 05:12:08 PM UTC 24 |
| Finished | Oct 09 05:41:38 PM UTC 24 |
| Peak memory | 283124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644704350 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_stress_all.2644704350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/30.alert_handler_stress_all_with_rand_reset.1606255902 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1987040118 ps |
| CPU time | 142.39 seconds |
| Started | Oct 09 05:12:13 PM UTC 24 |
| Finished | Oct 09 05:14:38 PM UTC 24 |
| Peak memory | 281268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1606255902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.a lert_handler_stress_all_with_rand_reset.1606255902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/30.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_entropy.4136267933 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 32825026902 ps |
| CPU time | 2488.21 seconds |
| Started | Oct 09 05:13:21 PM UTC 24 |
| Finished | Oct 09 05:55:19 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136267933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.4136267933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_alert_accum.895429405 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 16341349121 ps |
| CPU time | 209.08 seconds |
| Started | Oct 09 05:13:09 PM UTC 24 |
| Finished | Oct 09 05:16:41 PM UTC 24 |
| Peak memory | 266776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895429405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.895429405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_esc_intr_timeout.3175531846 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 472712776 ps |
| CPU time | 39.95 seconds |
| Started | Oct 09 05:13:07 PM UTC 24 |
| Finished | Oct 09 05:13:49 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175531846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3175531846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg.2819258433 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 44608626897 ps |
| CPU time | 1000.72 seconds |
| Started | Oct 09 05:13:37 PM UTC 24 |
| Finished | Oct 09 05:30:30 PM UTC 24 |
| Peak memory | 283260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819258433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2819258433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_lpg_stub_clk.1962140914 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 108149025879 ps |
| CPU time | 1717.38 seconds |
| Started | Oct 09 05:13:52 PM UTC 24 |
| Finished | Oct 09 05:42:49 PM UTC 24 |
| Peak memory | 295556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962140914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1962140914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_alerts.2731313639 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 282357895 ps |
| CPU time | 14.83 seconds |
| Started | Oct 09 05:12:41 PM UTC 24 |
| Finished | Oct 09 05:12:57 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731313639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2731313639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_random_classes.3586270531 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 885514433 ps |
| CPU time | 28.34 seconds |
| Started | Oct 09 05:12:58 PM UTC 24 |
| Finished | Oct 09 05:13:28 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586270531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3586270531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_sig_int_fail.534730859 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 570118061 ps |
| CPU time | 39.59 seconds |
| Started | Oct 09 05:13:18 PM UTC 24 |
| Finished | Oct 09 05:13:59 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534730859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.534730859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_smoke.3717269106 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1007488933 ps |
| CPU time | 39.85 seconds |
| Started | Oct 09 05:12:39 PM UTC 24 |
| Finished | Oct 09 05:13:20 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717269106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3717269106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/31.alert_handler_stress_all.2176471772 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 58580423146 ps |
| CPU time | 3722.38 seconds |
| Started | Oct 09 05:13:52 PM UTC 24 |
| Finished | Oct 09 06:16:36 PM UTC 24 |
| Peak memory | 312308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176471772 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_stress_all.2176471772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/31.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_entropy.1572039586 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 20219484787 ps |
| CPU time | 1263.97 seconds |
| Started | Oct 09 05:15:21 PM UTC 24 |
| Finished | Oct 09 05:36:40 PM UTC 24 |
| Peak memory | 283260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572039586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1572039586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_alert_accum.4211128482 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 9301424686 ps |
| CPU time | 307.09 seconds |
| Started | Oct 09 05:14:41 PM UTC 24 |
| Finished | Oct 09 05:19:53 PM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211128482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.4211128482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_esc_intr_timeout.3460873815 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 589923067 ps |
| CPU time | 58.94 seconds |
| Started | Oct 09 05:14:39 PM UTC 24 |
| Finished | Oct 09 05:15:40 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460873815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.3460873815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg.781210736 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 13352270972 ps |
| CPU time | 1240.79 seconds |
| Started | Oct 09 05:15:28 PM UTC 24 |
| Finished | Oct 09 05:36:24 PM UTC 24 |
| Peak memory | 283256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781210736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.781210736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_lpg_stub_clk.3185772797 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 71529011149 ps |
| CPU time | 3404.93 seconds |
| Started | Oct 09 05:15:32 PM UTC 24 |
| Finished | Oct 09 06:12:58 PM UTC 24 |
| Peak memory | 295940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185772797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3185772797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_ping_timeout.2143426274 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2990883397 ps |
| CPU time | 118.22 seconds |
| Started | Oct 09 05:15:23 PM UTC 24 |
| Finished | Oct 09 05:17:24 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143426274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2143426274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_alerts.1886717193 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 91219942 ps |
| CPU time | 7.19 seconds |
| Started | Oct 09 05:14:30 PM UTC 24 |
| Finished | Oct 09 05:14:38 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886717193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1886717193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_random_classes.152726522 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3407453717 ps |
| CPU time | 74.86 seconds |
| Started | Oct 09 05:14:39 PM UTC 24 |
| Finished | Oct 09 05:15:56 PM UTC 24 |
| Peak memory | 260720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152726522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.152726522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_sig_int_fail.3679049336 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 299674618 ps |
| CPU time | 18.56 seconds |
| Started | Oct 09 05:15:12 PM UTC 24 |
| Finished | Oct 09 05:15:32 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679049336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3679049336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_smoke.298010812 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 688704471 ps |
| CPU time | 38.66 seconds |
| Started | Oct 09 05:14:00 PM UTC 24 |
| Finished | Oct 09 05:14:40 PM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298010812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.298010812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/32.alert_handler_stress_all.3488177959 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 125749688822 ps |
| CPU time | 1782.58 seconds |
| Started | Oct 09 05:15:41 PM UTC 24 |
| Finished | Oct 09 05:45:44 PM UTC 24 |
| Peak memory | 295412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488177959 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_stress_all.3488177959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/32.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_entropy.1454097571 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 26012082115 ps |
| CPU time | 1160.49 seconds |
| Started | Oct 09 05:16:25 PM UTC 24 |
| Finished | Oct 09 05:35:58 PM UTC 24 |
| Peak memory | 283056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1454097571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1454097571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_alert_accum.485656703 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1406861010 ps |
| CPU time | 85.81 seconds |
| Started | Oct 09 05:16:09 PM UTC 24 |
| Finished | Oct 09 05:17:37 PM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485656703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.485656703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_esc_intr_timeout.4015997997 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 764407129 ps |
| CPU time | 73.42 seconds |
| Started | Oct 09 05:16:05 PM UTC 24 |
| Finished | Oct 09 05:17:20 PM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015997997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4015997997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg.1376482369 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 33111500875 ps |
| CPU time | 746.51 seconds |
| Started | Oct 09 05:16:42 PM UTC 24 |
| Finished | Oct 09 05:29:18 PM UTC 24 |
| Peak memory | 283140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376482369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1376482369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_lpg_stub_clk.4062256220 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 17323969379 ps |
| CPU time | 1408.13 seconds |
| Started | Oct 09 05:16:47 PM UTC 24 |
| Finished | Oct 09 05:40:32 PM UTC 24 |
| Peak memory | 283068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062256220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.4062256220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_ping_timeout.451024484 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 9575794913 ps |
| CPU time | 209.93 seconds |
| Started | Oct 09 05:16:27 PM UTC 24 |
| Finished | Oct 09 05:20:00 PM UTC 24 |
| Peak memory | 260736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451024484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.451024484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_alerts.2534179740 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 34231762 ps |
| CPU time | 5.79 seconds |
| Started | Oct 09 05:15:57 PM UTC 24 |
| Finished | Oct 09 05:16:04 PM UTC 24 |
| Peak memory | 260656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534179740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2534179740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_random_classes.2666899397 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 380829022 ps |
| CPU time | 9.43 seconds |
| Started | Oct 09 05:16:02 PM UTC 24 |
| Finished | Oct 09 05:16:13 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666899397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2666899397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_sig_int_fail.1261886818 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 565995782 ps |
| CPU time | 31.17 seconds |
| Started | Oct 09 05:16:13 PM UTC 24 |
| Finished | Oct 09 05:16:46 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261886818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1261886818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_smoke.682199680 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 86352467 ps |
| CPU time | 10.34 seconds |
| Started | Oct 09 05:15:57 PM UTC 24 |
| Finished | Oct 09 05:16:09 PM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682199680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.682199680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/33.alert_handler_stress_all.3708460029 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 48860795256 ps |
| CPU time | 1588.11 seconds |
| Started | Oct 09 05:16:57 PM UTC 24 |
| Finished | Oct 09 05:43:44 PM UTC 24 |
| Peak memory | 283052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3708460029 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_stress_all.3708460029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/33.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_entropy.1064658554 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 92770694503 ps |
| CPU time | 2300.5 seconds |
| Started | Oct 09 05:18:16 PM UTC 24 |
| Finished | Oct 09 05:57:03 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064658554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1064658554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_alert_accum.1823554078 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 2405083459 ps |
| CPU time | 76.26 seconds |
| Started | Oct 09 05:17:57 PM UTC 24 |
| Finished | Oct 09 05:19:15 PM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823554078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1823554078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_esc_intr_timeout.3723789349 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 1074507717 ps |
| CPU time | 17.41 seconds |
| Started | Oct 09 05:17:38 PM UTC 24 |
| Finished | Oct 09 05:17:57 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723789349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3723789349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg.4111448141 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 55885301566 ps |
| CPU time | 1709.79 seconds |
| Started | Oct 09 05:18:46 PM UTC 24 |
| Finished | Oct 09 05:47:36 PM UTC 24 |
| Peak memory | 283264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111448141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.4111448141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_lpg_stub_clk.1430310648 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 31428270571 ps |
| CPU time | 891.08 seconds |
| Started | Oct 09 05:18:58 PM UTC 24 |
| Finished | Oct 09 05:34:01 PM UTC 24 |
| Peak memory | 283064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430310648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1430310648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_ping_timeout.3166879368 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 25663106936 ps |
| CPU time | 356.47 seconds |
| Started | Oct 09 05:18:31 PM UTC 24 |
| Finished | Oct 09 05:24:33 PM UTC 24 |
| Peak memory | 260616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166879368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3166879368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_alerts.3956048438 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 51046448 ps |
| CPU time | 7.78 seconds |
| Started | Oct 09 05:17:25 PM UTC 24 |
| Finished | Oct 09 05:17:34 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956048438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3956048438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_random_classes.3518595814 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 764555046 ps |
| CPU time | 68.75 seconds |
| Started | Oct 09 05:17:35 PM UTC 24 |
| Finished | Oct 09 05:18:46 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518595814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3518595814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_sig_int_fail.1264557529 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 830442141 ps |
| CPU time | 69.02 seconds |
| Started | Oct 09 05:18:09 PM UTC 24 |
| Finished | Oct 09 05:19:20 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264557529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1264557529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_smoke.3586926459 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 1241533701 ps |
| CPU time | 94.12 seconds |
| Started | Oct 09 05:17:22 PM UTC 24 |
| Finished | Oct 09 05:18:58 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586926459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3586926459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/34.alert_handler_stress_all.308082780 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 57856719222 ps |
| CPU time | 3560.7 seconds |
| Started | Oct 09 05:19:12 PM UTC 24 |
| Finished | Oct 09 06:19:13 PM UTC 24 |
| Peak memory | 301996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308082780 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_stress_all.308082780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/34.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_entropy.368146149 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 203801774298 ps |
| CPU time | 3469.84 seconds |
| Started | Oct 09 05:20:20 PM UTC 24 |
| Finished | Oct 09 06:18:51 PM UTC 24 |
| Peak memory | 302208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368146149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.368146149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_alert_accum.1392880232 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3583822853 ps |
| CPU time | 247.73 seconds |
| Started | Oct 09 05:20:01 PM UTC 24 |
| Finished | Oct 09 05:24:13 PM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392880232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1392880232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_esc_intr_timeout.231830640 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 711372122 ps |
| CPU time | 27.51 seconds |
| Started | Oct 09 05:19:54 PM UTC 24 |
| Finished | Oct 09 05:20:22 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231830640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.231830640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg.3606862499 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 12904420141 ps |
| CPU time | 1019.54 seconds |
| Started | Oct 09 05:20:29 PM UTC 24 |
| Finished | Oct 09 05:37:40 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606862499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3606862499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_lpg_stub_clk.1473261714 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 53867589149 ps |
| CPU time | 1546.62 seconds |
| Started | Oct 09 05:21:04 PM UTC 24 |
| Finished | Oct 09 05:47:09 PM UTC 24 |
| Peak memory | 283068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473261714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1473261714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_ping_timeout.3993344759 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 20667637026 ps |
| CPU time | 432.63 seconds |
| Started | Oct 09 05:20:23 PM UTC 24 |
| Finished | Oct 09 05:27:42 PM UTC 24 |
| Peak memory | 260616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993344759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3993344759 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_alerts.2031986502 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 266821667 ps |
| CPU time | 18.96 seconds |
| Started | Oct 09 05:19:29 PM UTC 24 |
| Finished | Oct 09 05:19:49 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031986502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2031986502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_random_classes.2409420680 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 4915405898 ps |
| CPU time | 84.61 seconds |
| Started | Oct 09 05:19:50 PM UTC 24 |
| Finished | Oct 09 05:21:17 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409420680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2409420680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_sig_int_fail.3777273885 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2377138272 ps |
| CPU time | 85.76 seconds |
| Started | Oct 09 05:20:15 PM UTC 24 |
| Finished | Oct 09 05:21:43 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777273885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3777273885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_smoke.763897805 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1829516042 ps |
| CPU time | 51.17 seconds |
| Started | Oct 09 05:19:21 PM UTC 24 |
| Finished | Oct 09 05:20:14 PM UTC 24 |
| Peak memory | 266684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763897805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.763897805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/35.alert_handler_stress_all.3095965923 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 82940268418 ps |
| CPU time | 1627.5 seconds |
| Started | Oct 09 05:21:16 PM UTC 24 |
| Finished | Oct 09 05:48:44 PM UTC 24 |
| Peak memory | 283124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095965923 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_stress_all.3095965923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/35.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_entropy.2155459367 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 44981555705 ps |
| CPU time | 2542.35 seconds |
| Started | Oct 09 05:22:30 PM UTC 24 |
| Finished | Oct 09 06:05:23 PM UTC 24 |
| Peak memory | 299952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155459367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2155459367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_alert_accum.3448294196 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 2369061712 ps |
| CPU time | 127.68 seconds |
| Started | Oct 09 05:22:24 PM UTC 24 |
| Finished | Oct 09 05:24:34 PM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448294196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3448294196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_esc_intr_timeout.182241906 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 7398051671 ps |
| CPU time | 63.09 seconds |
| Started | Oct 09 05:22:24 PM UTC 24 |
| Finished | Oct 09 05:23:29 PM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182241906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.182241906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_ping_timeout.2557272115 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 4866222209 ps |
| CPU time | 270.62 seconds |
| Started | Oct 09 05:22:35 PM UTC 24 |
| Finished | Oct 09 05:27:10 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557272115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2557272115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_alerts.365296586 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1466917041 ps |
| CPU time | 44.72 seconds |
| Started | Oct 09 05:21:43 PM UTC 24 |
| Finished | Oct 09 05:22:30 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365296586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.365296586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_random_classes.402978216 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1665863087 ps |
| CPU time | 72.43 seconds |
| Started | Oct 09 05:21:55 PM UTC 24 |
| Finished | Oct 09 05:23:10 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402978216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.402978216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_smoke.2247968522 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3399045775 ps |
| CPU time | 68.61 seconds |
| Started | Oct 09 05:21:18 PM UTC 24 |
| Finished | Oct 09 05:22:29 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247968522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2247968522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all.4015211762 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 63797008404 ps |
| CPU time | 3817.11 seconds |
| Started | Oct 09 05:23:09 PM UTC 24 |
| Finished | Oct 09 06:27:31 PM UTC 24 |
| Peak memory | 302068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015211762 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_stress_all.4015211762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/36.alert_handler_stress_all_with_rand_reset.1713643842 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 2076968213 ps |
| CPU time | 185.76 seconds |
| Started | Oct 09 05:23:11 PM UTC 24 |
| Finished | Oct 09 05:26:20 PM UTC 24 |
| Peak memory | 281068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=1713643842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.a lert_handler_stress_all_with_rand_reset.1713643842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/36.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_entropy.1668633069 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 20750986794 ps |
| CPU time | 2176.32 seconds |
| Started | Oct 09 05:23:49 PM UTC 24 |
| Finished | Oct 09 06:00:32 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668633069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1668633069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_alert_accum.2071674758 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1912526158 ps |
| CPU time | 152.67 seconds |
| Started | Oct 09 05:23:46 PM UTC 24 |
| Finished | Oct 09 05:26:21 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071674758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2071674758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_esc_intr_timeout.2494384318 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 1728784218 ps |
| CPU time | 54.51 seconds |
| Started | Oct 09 05:23:37 PM UTC 24 |
| Finished | Oct 09 05:24:33 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494384318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2494384318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg.3749511973 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 75758695227 ps |
| CPU time | 1784.87 seconds |
| Started | Oct 09 05:24:14 PM UTC 24 |
| Finished | Oct 09 05:54:20 PM UTC 24 |
| Peak memory | 299648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749511973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3749511973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_lpg_stub_clk.4039817462 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 21347922499 ps |
| CPU time | 1663.66 seconds |
| Started | Oct 09 05:24:23 PM UTC 24 |
| Finished | Oct 09 05:52:28 PM UTC 24 |
| Peak memory | 283336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039817462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4039817462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_ping_timeout.3737969127 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 13846409778 ps |
| CPU time | 166.48 seconds |
| Started | Oct 09 05:24:10 PM UTC 24 |
| Finished | Oct 09 05:26:59 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737969127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3737969127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_alerts.3460690524 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 416408391 ps |
| CPU time | 16.18 seconds |
| Started | Oct 09 05:23:30 PM UTC 24 |
| Finished | Oct 09 05:23:47 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460690524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3460690524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_random_classes.1335900633 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 3447814264 ps |
| CPU time | 50.78 seconds |
| Started | Oct 09 05:23:30 PM UTC 24 |
| Finished | Oct 09 05:24:22 PM UTC 24 |
| Peak memory | 260764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335900633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1335900633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_sig_int_fail.4034446920 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 926909244 ps |
| CPU time | 63.5 seconds |
| Started | Oct 09 05:23:49 PM UTC 24 |
| Finished | Oct 09 05:24:54 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034446920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4034446920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_smoke.1514051975 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 615384765 ps |
| CPU time | 14.61 seconds |
| Started | Oct 09 05:23:14 PM UTC 24 |
| Finished | Oct 09 05:23:29 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514051975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1514051975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/37.alert_handler_stress_all.1718571890 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 246063096770 ps |
| CPU time | 4068.13 seconds |
| Started | Oct 09 05:24:33 PM UTC 24 |
| Finished | Oct 09 06:33:11 PM UTC 24 |
| Peak memory | 302196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718571890 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_stress_all.1718571890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/37.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_entropy.1825029903 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 51195611892 ps |
| CPU time | 1771.43 seconds |
| Started | Oct 09 05:25:16 PM UTC 24 |
| Finished | Oct 09 05:55:08 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825029903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1825029903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_alert_accum.182133719 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 1644567710 ps |
| CPU time | 27.31 seconds |
| Started | Oct 09 05:25:11 PM UTC 24 |
| Finished | Oct 09 05:25:40 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182133719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.182133719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_esc_intr_timeout.1780985610 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1679030182 ps |
| CPU time | 48.06 seconds |
| Started | Oct 09 05:24:57 PM UTC 24 |
| Finished | Oct 09 05:25:47 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780985610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1780985610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_lpg.1570626500 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 56051879254 ps |
| CPU time | 3529.09 seconds |
| Started | Oct 09 05:25:48 PM UTC 24 |
| Finished | Oct 09 06:25:21 PM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570626500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1570626500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_alerts.2843947266 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 1343904297 ps |
| CPU time | 23.39 seconds |
| Started | Oct 09 05:24:50 PM UTC 24 |
| Finished | Oct 09 05:25:15 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843947266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2843947266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_random_classes.595998099 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 231608022 ps |
| CPU time | 16.36 seconds |
| Started | Oct 09 05:24:57 PM UTC 24 |
| Finished | Oct 09 05:25:15 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595998099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.595998099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_sig_int_fail.3863397448 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2295847015 ps |
| CPU time | 96.96 seconds |
| Started | Oct 09 05:25:16 PM UTC 24 |
| Finished | Oct 09 05:26:55 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863397448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3863397448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_smoke.982420322 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2318969277 ps |
| CPU time | 13.27 seconds |
| Started | Oct 09 05:24:35 PM UTC 24 |
| Finished | Oct 09 05:24:49 PM UTC 24 |
| Peak memory | 264704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982420322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.982420322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/38.alert_handler_stress_all.3915893747 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 44255311540 ps |
| CPU time | 1614.58 seconds |
| Started | Oct 09 05:26:09 PM UTC 24 |
| Finished | Oct 09 05:53:23 PM UTC 24 |
| Peak memory | 283052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915893747 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_stress_all.3915893747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/38.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_entropy.2326899393 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 34992976510 ps |
| CPU time | 2497.82 seconds |
| Started | Oct 09 05:27:18 PM UTC 24 |
| Finished | Oct 09 06:09:25 PM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326899393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2326899393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_alert_accum.3240612577 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 14809875290 ps |
| CPU time | 254.66 seconds |
| Started | Oct 09 05:27:11 PM UTC 24 |
| Finished | Oct 09 05:31:29 PM UTC 24 |
| Peak memory | 266664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240612577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3240612577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_esc_intr_timeout.366291649 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 320686212 ps |
| CPU time | 38.91 seconds |
| Started | Oct 09 05:27:00 PM UTC 24 |
| Finished | Oct 09 05:27:41 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366291649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.366291649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg.1635908702 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 35289439745 ps |
| CPU time | 1252.2 seconds |
| Started | Oct 09 05:27:42 PM UTC 24 |
| Finished | Oct 09 05:48:49 PM UTC 24 |
| Peak memory | 299444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635908702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1635908702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_lpg_stub_clk.3581345586 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 74725641196 ps |
| CPU time | 2638.31 seconds |
| Started | Oct 09 05:27:42 PM UTC 24 |
| Finished | Oct 09 06:12:11 PM UTC 24 |
| Peak memory | 302008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581345586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3581345586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_ping_timeout.3860111420 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 3891187611 ps |
| CPU time | 142.85 seconds |
| Started | Oct 09 05:27:39 PM UTC 24 |
| Finished | Oct 09 05:30:04 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860111420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3860111420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_alerts.992392024 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 672965215 ps |
| CPU time | 24.37 seconds |
| Started | Oct 09 05:26:44 PM UTC 24 |
| Finished | Oct 09 05:27:10 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992392024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.992392024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_random_classes.221661385 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 880943870 ps |
| CPU time | 41.64 seconds |
| Started | Oct 09 05:26:55 PM UTC 24 |
| Finished | Oct 09 05:27:38 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221661385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.221661385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_sig_int_fail.2510145135 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 185212006 ps |
| CPU time | 5.32 seconds |
| Started | Oct 09 05:27:11 PM UTC 24 |
| Finished | Oct 09 05:27:17 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510145135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2510145135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_smoke.4106755463 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4316780079 ps |
| CPU time | 98.76 seconds |
| Started | Oct 09 05:26:22 PM UTC 24 |
| Finished | Oct 09 05:28:03 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106755463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4106755463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all.1900395751 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 25718033252 ps |
| CPU time | 200.99 seconds |
| Started | Oct 09 05:28:04 PM UTC 24 |
| Finished | Oct 09 05:31:28 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900395751 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_stress_all.1900395751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/39.alert_handler_stress_all_with_rand_reset.4283661319 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 5893957060 ps |
| CPU time | 556.44 seconds |
| Started | Oct 09 05:28:08 PM UTC 24 |
| Finished | Oct 09 05:37:32 PM UTC 24 |
| Peak memory | 281332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=4283661319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.a lert_handler_stress_all_with_rand_reset.4283661319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/39.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_alert_accum_saturation.1574522132 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 114922977 ps |
| CPU time | 5.03 seconds |
| Started | Oct 09 04:18:16 PM UTC 24 |
| Finished | Oct 09 04:18:23 PM UTC 24 |
| Peak memory | 260732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574522132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1574522132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy.2864299259 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 36007551859 ps |
| CPU time | 2695.58 seconds |
| Started | Oct 09 04:17:58 PM UTC 24 |
| Finished | Oct 09 05:03:24 PM UTC 24 |
| Peak memory | 299448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864299259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2864299259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_entropy_stress.1167436335 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 3264014026 ps |
| CPU time | 46.61 seconds |
| Started | Oct 09 04:18:09 PM UTC 24 |
| Finished | Oct 09 04:18:57 PM UTC 24 |
| Peak memory | 260524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167436335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1167436335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_esc_alert_accum.1829173848 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 8842948091 ps |
| CPU time | 331.55 seconds |
| Started | Oct 09 04:17:46 PM UTC 24 |
| Finished | Oct 09 04:23:23 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829173848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1829173848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg.783808549 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 38285463322 ps |
| CPU time | 1333.61 seconds |
| Started | Oct 09 04:18:00 PM UTC 24 |
| Finished | Oct 09 04:40:30 PM UTC 24 |
| Peak memory | 276912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783808549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.783808549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_lpg_stub_clk.689832634 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 49646329489 ps |
| CPU time | 3087.34 seconds |
| Started | Oct 09 04:18:08 PM UTC 24 |
| Finished | Oct 09 05:10:10 PM UTC 24 |
| Peak memory | 293304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689832634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.689832634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_ping_timeout.3347366275 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 15317021757 ps |
| CPU time | 332.79 seconds |
| Started | Oct 09 04:17:59 PM UTC 24 |
| Finished | Oct 09 04:23:36 PM UTC 24 |
| Peak memory | 260736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347366275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3347366275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_random_alerts.4105710690 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 331140602 ps |
| CPU time | 27.84 seconds |
| Started | Oct 09 04:17:39 PM UTC 24 |
| Finished | Oct 09 04:18:08 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105710690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.4105710690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_sec_cm.2898623811 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1499848044 ps |
| CPU time | 21.39 seconds |
| Started | Oct 09 04:18:20 PM UTC 24 |
| Finished | Oct 09 04:18:43 PM UTC 24 |
| Peak memory | 292572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898623811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM _TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_ handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2898623811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_sig_int_fail.1231725704 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 278574138 ps |
| CPU time | 19.59 seconds |
| Started | Oct 09 04:17:54 PM UTC 24 |
| Finished | Oct 09 04:18:15 PM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231725704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1231725704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_smoke.3542149655 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 262936326 ps |
| CPU time | 28.06 seconds |
| Started | Oct 09 04:17:38 PM UTC 24 |
| Finished | Oct 09 04:18:07 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542149655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3542149655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/4.alert_handler_stress_all_with_rand_reset.3204123373 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 2379971446 ps |
| CPU time | 260.84 seconds |
| Started | Oct 09 04:18:17 PM UTC 24 |
| Finished | Oct 09 04:22:41 PM UTC 24 |
| Peak memory | 277108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3204123373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.al ert_handler_stress_all_with_rand_reset.3204123373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_entropy.2020657392 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 109697763342 ps |
| CPU time | 1577.88 seconds |
| Started | Oct 09 05:29:26 PM UTC 24 |
| Finished | Oct 09 05:56:02 PM UTC 24 |
| Peak memory | 283056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020657392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2020657392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_alert_accum.934690639 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1768897420 ps |
| CPU time | 83.76 seconds |
| Started | Oct 09 05:28:52 PM UTC 24 |
| Finished | Oct 09 05:30:18 PM UTC 24 |
| Peak memory | 266712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934690639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.934690639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_esc_intr_timeout.3337719120 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 1494174964 ps |
| CPU time | 32.1 seconds |
| Started | Oct 09 05:28:52 PM UTC 24 |
| Finished | Oct 09 05:29:25 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337719120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.3337719120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg.3215192640 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 60071843076 ps |
| CPU time | 1761.17 seconds |
| Started | Oct 09 05:29:46 PM UTC 24 |
| Finished | Oct 09 05:59:30 PM UTC 24 |
| Peak memory | 299712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215192640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.3215192640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_lpg_stub_clk.207201777 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 11757206287 ps |
| CPU time | 764.4 seconds |
| Started | Oct 09 05:29:56 PM UTC 24 |
| Finished | Oct 09 05:42:50 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207201777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.207201777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_ping_timeout.428770922 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 4146073318 ps |
| CPU time | 170.71 seconds |
| Started | Oct 09 05:29:31 PM UTC 24 |
| Finished | Oct 09 05:32:25 PM UTC 24 |
| Peak memory | 260608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428770922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.428770922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_alerts.1309455174 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 350037987 ps |
| CPU time | 21.27 seconds |
| Started | Oct 09 05:28:28 PM UTC 24 |
| Finished | Oct 09 05:28:51 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309455174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1309455174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_random_classes.4008280490 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 5510578773 ps |
| CPU time | 74.9 seconds |
| Started | Oct 09 05:28:37 PM UTC 24 |
| Finished | Oct 09 05:29:54 PM UTC 24 |
| Peak memory | 266776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008280490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4008280490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_sig_int_fail.2630412350 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 866148709 ps |
| CPU time | 33.98 seconds |
| Started | Oct 09 05:29:20 PM UTC 24 |
| Finished | Oct 09 05:29:55 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630412350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2630412350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_smoke.308128350 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 882670120 ps |
| CPU time | 84.18 seconds |
| Started | Oct 09 05:28:20 PM UTC 24 |
| Finished | Oct 09 05:29:46 PM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308128350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.308128350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all.1718612589 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 73144013173 ps |
| CPU time | 3376.59 seconds |
| Started | Oct 09 05:29:57 PM UTC 24 |
| Finished | Oct 09 06:26:52 PM UTC 24 |
| Peak memory | 301996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718612589 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_stress_all.1718612589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/40.alert_handler_stress_all_with_rand_reset.3326350310 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 10456639171 ps |
| CPU time | 316.72 seconds |
| Started | Oct 09 05:30:05 PM UTC 24 |
| Finished | Oct 09 05:35:26 PM UTC 24 |
| Peak memory | 279156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=3326350310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.a lert_handler_stress_all_with_rand_reset.3326350310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/40.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_entropy.2772153116 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 241389044168 ps |
| CPU time | 1897.74 seconds |
| Started | Oct 09 05:31:29 PM UTC 24 |
| Finished | Oct 09 06:03:30 PM UTC 24 |
| Peak memory | 295548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772153116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2772153116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_alert_accum.528475531 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 5171802083 ps |
| CPU time | 364.08 seconds |
| Started | Oct 09 05:30:54 PM UTC 24 |
| Finished | Oct 09 05:37:04 PM UTC 24 |
| Peak memory | 266704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528475531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.528475531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_esc_intr_timeout.3195053862 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 661906795 ps |
| CPU time | 70.71 seconds |
| Started | Oct 09 05:30:32 PM UTC 24 |
| Finished | Oct 09 05:31:45 PM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195053862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3195053862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_lpg_stub_clk.2740941870 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 543288318245 ps |
| CPU time | 3370.3 seconds |
| Started | Oct 09 05:31:38 PM UTC 24 |
| Finished | Oct 09 06:28:30 PM UTC 24 |
| Peak memory | 302008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740941870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2740941870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_ping_timeout.772574036 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 20719751251 ps |
| CPU time | 345.37 seconds |
| Started | Oct 09 05:31:30 PM UTC 24 |
| Finished | Oct 09 05:37:21 PM UTC 24 |
| Peak memory | 260608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772574036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.772574036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_alerts.3264578064 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1205477577 ps |
| CPU time | 33.61 seconds |
| Started | Oct 09 05:30:19 PM UTC 24 |
| Finished | Oct 09 05:30:54 PM UTC 24 |
| Peak memory | 260528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264578064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3264578064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_random_classes.2484116349 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 492194131 ps |
| CPU time | 24.51 seconds |
| Started | Oct 09 05:30:27 PM UTC 24 |
| Finished | Oct 09 05:30:53 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484116349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2484116349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_sig_int_fail.2468099245 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 2301794099 ps |
| CPU time | 61.17 seconds |
| Started | Oct 09 05:30:55 PM UTC 24 |
| Finished | Oct 09 05:31:59 PM UTC 24 |
| Peak memory | 266744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468099245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2468099245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_smoke.702258244 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 1406006586 ps |
| CPU time | 18.92 seconds |
| Started | Oct 09 05:30:06 PM UTC 24 |
| Finished | Oct 09 05:30:26 PM UTC 24 |
| Peak memory | 264768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=702258244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.702258244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/41.alert_handler_stress_all.2349970899 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 41963171580 ps |
| CPU time | 2992.82 seconds |
| Started | Oct 09 05:31:47 PM UTC 24 |
| Finished | Oct 09 06:22:15 PM UTC 24 |
| Peak memory | 301996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349970899 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_stress_all.2349970899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/41.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_entropy.961550989 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 85814786814 ps |
| CPU time | 2549.36 seconds |
| Started | Oct 09 05:33:27 PM UTC 24 |
| Finished | Oct 09 06:16:26 PM UTC 24 |
| Peak memory | 298116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961550989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.961550989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_alert_accum.4154301215 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2242812092 ps |
| CPU time | 157.45 seconds |
| Started | Oct 09 05:33:25 PM UTC 24 |
| Finished | Oct 09 05:36:05 PM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154301215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.4154301215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_esc_intr_timeout.1190977818 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 213090360 ps |
| CPU time | 6.48 seconds |
| Started | Oct 09 05:33:17 PM UTC 24 |
| Finished | Oct 09 05:33:24 PM UTC 24 |
| Peak memory | 250492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190977818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1190977818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg.3313171019 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 192710464546 ps |
| CPU time | 1374.53 seconds |
| Started | Oct 09 05:33:47 PM UTC 24 |
| Finished | Oct 09 05:56:57 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313171019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3313171019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_lpg_stub_clk.50497395 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 279207696140 ps |
| CPU time | 2284.14 seconds |
| Started | Oct 09 05:34:02 PM UTC 24 |
| Finished | Oct 09 06:12:34 PM UTC 24 |
| Peak memory | 297976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50497395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.50497395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_ping_timeout.1489290228 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 7423341858 ps |
| CPU time | 331.38 seconds |
| Started | Oct 09 05:33:42 PM UTC 24 |
| Finished | Oct 09 05:39:18 PM UTC 24 |
| Peak memory | 260612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489290228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1489290228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_alerts.3032548067 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2481993106 ps |
| CPU time | 55.79 seconds |
| Started | Oct 09 05:32:26 PM UTC 24 |
| Finished | Oct 09 05:33:24 PM UTC 24 |
| Peak memory | 260592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032548067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3032548067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_random_classes.2737907004 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 314831304 ps |
| CPU time | 30.11 seconds |
| Started | Oct 09 05:32:54 PM UTC 24 |
| Finished | Oct 09 05:33:26 PM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737907004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2737907004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_sig_int_fail.382833843 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 379430645 ps |
| CPU time | 34.24 seconds |
| Started | Oct 09 05:33:25 PM UTC 24 |
| Finished | Oct 09 05:34:01 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382833843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.382833843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_smoke.2684465221 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 1536661020 ps |
| CPU time | 52.21 seconds |
| Started | Oct 09 05:32:00 PM UTC 24 |
| Finished | Oct 09 05:32:54 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684465221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2684465221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/42.alert_handler_stress_all.2617837533 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 197555028874 ps |
| CPU time | 2616.95 seconds |
| Started | Oct 09 05:34:02 PM UTC 24 |
| Finished | Oct 09 06:18:10 PM UTC 24 |
| Peak memory | 301996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617837533 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_stress_all.2617837533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/42.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_entropy.1282927895 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 36494191454 ps |
| CPU time | 2302.98 seconds |
| Started | Oct 09 05:36:47 PM UTC 24 |
| Finished | Oct 09 06:15:37 PM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1282927895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1282927895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_alert_accum.121685275 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 772622296 ps |
| CPU time | 97.55 seconds |
| Started | Oct 09 05:36:26 PM UTC 24 |
| Finished | Oct 09 05:38:06 PM UTC 24 |
| Peak memory | 266840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121685275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.121685275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_esc_intr_timeout.3826339915 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 1535013951 ps |
| CPU time | 29.59 seconds |
| Started | Oct 09 05:36:16 PM UTC 24 |
| Finished | Oct 09 05:36:47 PM UTC 24 |
| Peak memory | 260464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826339915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3826339915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg.2153375855 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 64691024719 ps |
| CPU time | 1631.62 seconds |
| Started | Oct 09 05:36:53 PM UTC 24 |
| Finished | Oct 09 06:04:24 PM UTC 24 |
| Peak memory | 299644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153375855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2153375855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_lpg_stub_clk.242962507 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 5864113969 ps |
| CPU time | 881.54 seconds |
| Started | Oct 09 05:36:53 PM UTC 24 |
| Finished | Oct 09 05:51:46 PM UTC 24 |
| Peak memory | 283264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242962507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.242962507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_ping_timeout.461256013 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 29195243796 ps |
| CPU time | 324.86 seconds |
| Started | Oct 09 05:36:48 PM UTC 24 |
| Finished | Oct 09 05:42:18 PM UTC 24 |
| Peak memory | 260608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461256013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.461256013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_alerts.3003314596 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1889268361 ps |
| CPU time | 45.65 seconds |
| Started | Oct 09 05:36:00 PM UTC 24 |
| Finished | Oct 09 05:36:47 PM UTC 24 |
| Peak memory | 266596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003314596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3003314596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_random_classes.1668506769 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 2312037765 ps |
| CPU time | 55.73 seconds |
| Started | Oct 09 05:36:06 PM UTC 24 |
| Finished | Oct 09 05:37:04 PM UTC 24 |
| Peak memory | 266940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668506769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1668506769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_sig_int_fail.1121717895 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 461934175 ps |
| CPU time | 46.53 seconds |
| Started | Oct 09 05:36:42 PM UTC 24 |
| Finished | Oct 09 05:37:30 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121717895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1121717895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_smoke.1677246111 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 183595643 ps |
| CPU time | 28.67 seconds |
| Started | Oct 09 05:35:44 PM UTC 24 |
| Finished | Oct 09 05:36:14 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677246111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1677246111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all.2228501849 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 25122548275 ps |
| CPU time | 1502.16 seconds |
| Started | Oct 09 05:37:05 PM UTC 24 |
| Finished | Oct 09 06:02:26 PM UTC 24 |
| Peak memory | 299688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228501849 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_stress_all.2228501849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/43.alert_handler_stress_all_with_rand_reset.2573328272 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2041917795 ps |
| CPU time | 366.66 seconds |
| Started | Oct 09 05:37:05 PM UTC 24 |
| Finished | Oct 09 05:43:17 PM UTC 24 |
| Peak memory | 279076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=2573328272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.a lert_handler_stress_all_with_rand_reset.2573328272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/43.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_entropy.1296548171 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 58310027883 ps |
| CPU time | 2636.19 seconds |
| Started | Oct 09 05:38:38 PM UTC 24 |
| Finished | Oct 09 06:23:08 PM UTC 24 |
| Peak memory | 298236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296548171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1296548171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_alert_accum.393975002 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 1987108224 ps |
| CPU time | 175.67 seconds |
| Started | Oct 09 05:37:42 PM UTC 24 |
| Finished | Oct 09 05:40:41 PM UTC 24 |
| Peak memory | 266628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393975002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.393975002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_esc_intr_timeout.393862734 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 402625056 ps |
| CPU time | 62.37 seconds |
| Started | Oct 09 05:37:33 PM UTC 24 |
| Finished | Oct 09 05:38:37 PM UTC 24 |
| Peak memory | 266676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393862734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.393862734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg.3341918463 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 38804700609 ps |
| CPU time | 1383.58 seconds |
| Started | Oct 09 05:39:10 PM UTC 24 |
| Finished | Oct 09 06:02:30 PM UTC 24 |
| Peak memory | 283140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341918463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3341918463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_lpg_stub_clk.3347073746 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 12887108918 ps |
| CPU time | 1168.44 seconds |
| Started | Oct 09 05:39:16 PM UTC 24 |
| Finished | Oct 09 05:58:58 PM UTC 24 |
| Peak memory | 283064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347073746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3347073746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_ping_timeout.3799196836 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 5012789224 ps |
| CPU time | 243.68 seconds |
| Started | Oct 09 05:38:55 PM UTC 24 |
| Finished | Oct 09 05:43:03 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799196836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3799196836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_alerts.632044463 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 920950101 ps |
| CPU time | 81.51 seconds |
| Started | Oct 09 05:37:31 PM UTC 24 |
| Finished | Oct 09 05:38:54 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632044463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.632044463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_random_classes.2666235463 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1028568890 ps |
| CPU time | 95.26 seconds |
| Started | Oct 09 05:37:32 PM UTC 24 |
| Finished | Oct 09 05:39:09 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666235463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2666235463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_sig_int_fail.3764871542 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 1015715883 ps |
| CPU time | 78.71 seconds |
| Started | Oct 09 05:38:07 PM UTC 24 |
| Finished | Oct 09 05:39:28 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3764871542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3764871542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_smoke.3963946592 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 119312700 ps |
| CPU time | 7.57 seconds |
| Started | Oct 09 05:37:22 PM UTC 24 |
| Finished | Oct 09 05:37:31 PM UTC 24 |
| Peak memory | 262708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963946592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3963946592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/44.alert_handler_stress_all.2279387458 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 5181577059 ps |
| CPU time | 486.17 seconds |
| Started | Oct 09 05:39:19 PM UTC 24 |
| Finished | Oct 09 05:47:32 PM UTC 24 |
| Peak memory | 266868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279387458 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_stress_all.2279387458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/44.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_entropy.87319985 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 44539888627 ps |
| CPU time | 2992.07 seconds |
| Started | Oct 09 05:41:51 PM UTC 24 |
| Finished | Oct 09 06:32:21 PM UTC 24 |
| Peak memory | 302004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=87319985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.87319985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_alert_accum.540727948 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 16142983383 ps |
| CPU time | 180.62 seconds |
| Started | Oct 09 05:41:48 PM UTC 24 |
| Finished | Oct 09 05:44:52 PM UTC 24 |
| Peak memory | 266684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540727948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.540727948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_esc_intr_timeout.3182096339 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 44719735 ps |
| CPU time | 5.97 seconds |
| Started | Oct 09 05:41:40 PM UTC 24 |
| Finished | Oct 09 05:41:47 PM UTC 24 |
| Peak memory | 250296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182096339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3182096339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_lpg_stub_clk.2350702130 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 106223286938 ps |
| CPU time | 2205.52 seconds |
| Started | Oct 09 05:42:19 PM UTC 24 |
| Finished | Oct 09 06:19:31 PM UTC 24 |
| Peak memory | 283072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350702130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2350702130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_ping_timeout.1339567357 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 20246468844 ps |
| CPU time | 390.7 seconds |
| Started | Oct 09 05:42:02 PM UTC 24 |
| Finished | Oct 09 05:48:38 PM UTC 24 |
| Peak memory | 260544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339567357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1339567357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_alerts.3131942795 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 879947864 ps |
| CPU time | 76.87 seconds |
| Started | Oct 09 05:40:43 PM UTC 24 |
| Finished | Oct 09 05:42:02 PM UTC 24 |
| Peak memory | 266600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131942795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3131942795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_random_classes.2121413277 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 781902742 ps |
| CPU time | 31.97 seconds |
| Started | Oct 09 05:41:17 PM UTC 24 |
| Finished | Oct 09 05:41:51 PM UTC 24 |
| Peak memory | 260492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121413277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2121413277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_sig_int_fail.761710065 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 417765568 ps |
| CPU time | 17.98 seconds |
| Started | Oct 09 05:41:48 PM UTC 24 |
| Finished | Oct 09 05:42:07 PM UTC 24 |
| Peak memory | 260496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761710065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.761710065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_smoke.1445535926 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 1217914209 ps |
| CPU time | 40.02 seconds |
| Started | Oct 09 05:40:34 PM UTC 24 |
| Finished | Oct 09 05:41:16 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445535926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1445535926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/45.alert_handler_stress_all.2143052673 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 9502562535 ps |
| CPU time | 493.08 seconds |
| Started | Oct 09 05:42:49 PM UTC 24 |
| Finished | Oct 09 05:51:09 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143052673 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_stress_all.2143052673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/45.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_entropy.97584961 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 30592654689 ps |
| CPU time | 2295.75 seconds |
| Started | Oct 09 05:43:30 PM UTC 24 |
| Finished | Oct 09 06:22:14 PM UTC 24 |
| Peak memory | 295864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97584961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/a lert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.97584961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_alert_accum.2431608425 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 15598689167 ps |
| CPU time | 230.87 seconds |
| Started | Oct 09 05:43:18 PM UTC 24 |
| Finished | Oct 09 05:47:13 PM UTC 24 |
| Peak memory | 266872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431608425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2431608425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_esc_intr_timeout.2645934139 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 3707384065 ps |
| CPU time | 74.54 seconds |
| Started | Oct 09 05:43:16 PM UTC 24 |
| Finished | Oct 09 05:44:33 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645934139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2645934139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg.107511099 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 89923998454 ps |
| CPU time | 1600.32 seconds |
| Started | Oct 09 05:43:46 PM UTC 24 |
| Finished | Oct 09 06:10:46 PM UTC 24 |
| Peak memory | 283056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107511099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.107511099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_lpg_stub_clk.3643048208 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 40304090079 ps |
| CPU time | 1342.39 seconds |
| Started | Oct 09 05:43:54 PM UTC 24 |
| Finished | Oct 09 06:06:35 PM UTC 24 |
| Peak memory | 295356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643048208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3643048208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_ping_timeout.1703507291 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 14440626338 ps |
| CPU time | 339.42 seconds |
| Started | Oct 09 05:43:33 PM UTC 24 |
| Finished | Oct 09 05:49:17 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703507291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1703507291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_alerts.1272623725 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 1209509745 ps |
| CPU time | 34.59 seconds |
| Started | Oct 09 05:42:53 PM UTC 24 |
| Finished | Oct 09 05:43:29 PM UTC 24 |
| Peak memory | 266672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272623725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1272623725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_random_classes.3491405251 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 1612158776 ps |
| CPU time | 48.4 seconds |
| Started | Oct 09 05:43:04 PM UTC 24 |
| Finished | Oct 09 05:43:54 PM UTC 24 |
| Peak memory | 260540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491405251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3491405251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_sig_int_fail.3173845813 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 729118011 ps |
| CPU time | 75.03 seconds |
| Started | Oct 09 05:43:23 PM UTC 24 |
| Finished | Oct 09 05:44:41 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173845813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3173845813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_smoke.2915627282 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 146632981 ps |
| CPU time | 21.27 seconds |
| Started | Oct 09 05:42:53 PM UTC 24 |
| Finished | Oct 09 05:43:15 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915627282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2915627282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all.3434565725 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 30381042476 ps |
| CPU time | 1965.29 seconds |
| Started | Oct 09 05:44:17 PM UTC 24 |
| Finished | Oct 09 06:17:25 PM UTC 24 |
| Peak memory | 293492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434565725 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_stress_all.3434565725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/46.alert_handler_stress_all_with_rand_reset.646877992 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 19784597250 ps |
| CPU time | 671.26 seconds |
| Started | Oct 09 05:44:34 PM UTC 24 |
| Finished | Oct 09 05:55:54 PM UTC 24 |
| Peak memory | 283384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=646877992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.al ert_handler_stress_all_with_rand_reset.646877992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/46.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_entropy.3796108444 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 100665595367 ps |
| CPU time | 3275.67 seconds |
| Started | Oct 09 05:45:47 PM UTC 24 |
| Finished | Oct 09 06:41:03 PM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796108444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3796108444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_alert_accum.3649465883 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3364805083 ps |
| CPU time | 141.64 seconds |
| Started | Oct 09 05:45:25 PM UTC 24 |
| Finished | Oct 09 05:47:49 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649465883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3649465883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_esc_intr_timeout.298837629 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 116903341 ps |
| CPU time | 14.12 seconds |
| Started | Oct 09 05:45:13 PM UTC 24 |
| Finished | Oct 09 05:45:28 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298837629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.298837629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg.321031806 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 78810012870 ps |
| CPU time | 2321.37 seconds |
| Started | Oct 09 05:46:40 PM UTC 24 |
| Finished | Oct 09 06:25:50 PM UTC 24 |
| Peak memory | 302204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321031806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.321031806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_lpg_stub_clk.305554522 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 47266318712 ps |
| CPU time | 1679.76 seconds |
| Started | Oct 09 05:47:10 PM UTC 24 |
| Finished | Oct 09 06:15:30 PM UTC 24 |
| Peak memory | 283060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305554522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.305554522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_ping_timeout.2070607666 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 83860559822 ps |
| CPU time | 544.21 seconds |
| Started | Oct 09 05:46:13 PM UTC 24 |
| Finished | Oct 09 05:55:24 PM UTC 24 |
| Peak memory | 260804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070607666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2070607666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_alerts.20852376 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 180652431 ps |
| CPU time | 18.31 seconds |
| Started | Oct 09 05:44:52 PM UTC 24 |
| Finished | Oct 09 05:45:12 PM UTC 24 |
| Peak memory | 264664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20852376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ran dom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.20852376 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_random_classes.1914980517 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 270941317 ps |
| CPU time | 9.7 seconds |
| Started | Oct 09 05:45:13 PM UTC 24 |
| Finished | Oct 09 05:45:23 PM UTC 24 |
| Peak memory | 264564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914980517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1914980517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_sig_int_fail.1937750114 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 1532389459 ps |
| CPU time | 40.89 seconds |
| Started | Oct 09 05:45:29 PM UTC 24 |
| Finished | Oct 09 05:46:11 PM UTC 24 |
| Peak memory | 266808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937750114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1937750114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_smoke.1430555957 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 240477812 ps |
| CPU time | 27.69 seconds |
| Started | Oct 09 05:44:42 PM UTC 24 |
| Finished | Oct 09 05:45:11 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430555957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1430555957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/47.alert_handler_stress_all_with_rand_reset.243532267 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 8403583188 ps |
| CPU time | 283.43 seconds |
| Started | Oct 09 05:47:33 PM UTC 24 |
| Finished | Oct 09 05:52:21 PM UTC 24 |
| Peak memory | 277240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +str ess_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random _seed=243532267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.al ert_handler_stress_all_with_rand_reset.243532267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/47.alert_handler_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_entropy.2749646555 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 394262526507 ps |
| CPU time | 3498.93 seconds |
| Started | Oct 09 05:48:52 PM UTC 24 |
| Finished | Oct 09 06:47:54 PM UTC 24 |
| Peak memory | 302268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749646555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.2749646555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_alert_accum.4088854194 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2563080096 ps |
| CPU time | 149.83 seconds |
| Started | Oct 09 05:48:40 PM UTC 24 |
| Finished | Oct 09 05:51:12 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088854194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.4088854194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_esc_intr_timeout.3465883963 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 1825934896 ps |
| CPU time | 53.44 seconds |
| Started | Oct 09 05:48:38 PM UTC 24 |
| Finished | Oct 09 05:49:34 PM UTC 24 |
| Peak memory | 266608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465883963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3465883963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg.1160820717 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 216848837204 ps |
| CPU time | 2789.57 seconds |
| Started | Oct 09 05:49:18 PM UTC 24 |
| Finished | Oct 09 06:36:23 PM UTC 24 |
| Peak memory | 302076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160820717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1160820717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_lpg_stub_clk.124628631 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 156705903220 ps |
| CPU time | 2693.44 seconds |
| Started | Oct 09 05:49:34 PM UTC 24 |
| Finished | Oct 09 06:35:02 PM UTC 24 |
| Peak memory | 302000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124628631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.124628631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_ping_timeout.2625886639 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 12305237885 ps |
| CPU time | 462.58 seconds |
| Started | Oct 09 05:49:12 PM UTC 24 |
| Finished | Oct 09 05:57:00 PM UTC 24 |
| Peak memory | 260612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625886639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2625886639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_alerts.180244496 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 1061598782 ps |
| CPU time | 45.15 seconds |
| Started | Oct 09 05:47:51 PM UTC 24 |
| Finished | Oct 09 05:48:37 PM UTC 24 |
| Peak memory | 266908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180244496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.180244496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_random_classes.3479489535 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 453870823 ps |
| CPU time | 42.32 seconds |
| Started | Oct 09 05:48:27 PM UTC 24 |
| Finished | Oct 09 05:49:11 PM UTC 24 |
| Peak memory | 260568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479489535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3479489535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_sig_int_fail.915008950 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 2631188030 ps |
| CPU time | 46.81 seconds |
| Started | Oct 09 05:48:46 PM UTC 24 |
| Finished | Oct 09 05:49:34 PM UTC 24 |
| Peak memory | 260636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915008950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_si g_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.915008950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_smoke.1168883707 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 1981325524 ps |
| CPU time | 45.64 seconds |
| Started | Oct 09 05:47:38 PM UTC 24 |
| Finished | Oct 09 05:48:26 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168883707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1168883707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/48.alert_handler_stress_all.1318047044 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 17991957040 ps |
| CPU time | 1846.71 seconds |
| Started | Oct 09 05:49:35 PM UTC 24 |
| Finished | Oct 09 06:20:45 PM UTC 24 |
| Peak memory | 299436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318047044 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_stress_all.1318047044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/48.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_entropy.3669068820 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 11360017403 ps |
| CPU time | 1218.35 seconds |
| Started | Oct 09 05:51:51 PM UTC 24 |
| Finished | Oct 09 06:12:25 PM UTC 24 |
| Peak memory | 293376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669068820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3669068820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_alert_accum.1355683065 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2000966269 ps |
| CPU time | 49.46 seconds |
| Started | Oct 09 05:51:13 PM UTC 24 |
| Finished | Oct 09 05:52:04 PM UTC 24 |
| Peak memory | 266680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355683065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1355683065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_esc_intr_timeout.504172878 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2271851271 ps |
| CPU time | 90.84 seconds |
| Started | Oct 09 05:51:10 PM UTC 24 |
| Finished | Oct 09 05:52:43 PM UTC 24 |
| Peak memory | 260596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504172878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.504172878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg.2548248551 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 223282401185 ps |
| CPU time | 1877.57 seconds |
| Started | Oct 09 05:52:22 PM UTC 24 |
| Finished | Oct 09 06:24:03 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548248551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2548248551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_lpg_stub_clk.685660692 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 12808865009 ps |
| CPU time | 924.82 seconds |
| Started | Oct 09 05:52:29 PM UTC 24 |
| Finished | Oct 09 06:08:07 PM UTC 24 |
| Peak memory | 283136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685660692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.685660692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_ping_timeout.3942868776 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 8633786195 ps |
| CPU time | 426.54 seconds |
| Started | Oct 09 05:52:05 PM UTC 24 |
| Finished | Oct 09 05:59:17 PM UTC 24 |
| Peak memory | 266884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942868776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3942868776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_alerts.3991498520 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 115807262 ps |
| CPU time | 8.41 seconds |
| Started | Oct 09 05:50:52 PM UTC 24 |
| Finished | Oct 09 05:51:02 PM UTC 24 |
| Peak memory | 250292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991498520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3991498520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_random_classes.792389560 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 716337775 ps |
| CPU time | 45.92 seconds |
| Started | Oct 09 05:51:02 PM UTC 24 |
| Finished | Oct 09 05:51:50 PM UTC 24 |
| Peak memory | 260456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792389560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.792389560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_sig_int_fail.3749651781 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 1000825130 ps |
| CPU time | 41.47 seconds |
| Started | Oct 09 05:51:47 PM UTC 24 |
| Finished | Oct 09 05:52:30 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749651781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3749651781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_smoke.1398578664 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 178430037 ps |
| CPU time | 15.74 seconds |
| Started | Oct 09 05:50:34 PM UTC 24 |
| Finished | Oct 09 05:50:51 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398578664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1398578664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/49.alert_handler_stress_all.192975397 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 38052843693 ps |
| CPU time | 2460.89 seconds |
| Started | Oct 09 05:52:31 PM UTC 24 |
| Finished | Oct 09 06:34:03 PM UTC 24 |
| Peak memory | 301996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192975397 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_stress_all.192975397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/49.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_alert_accum_saturation.1743695306 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 135224747 ps |
| CPU time | 5.08 seconds |
| Started | Oct 09 04:19:00 PM UTC 24 |
| Finished | Oct 09 04:19:06 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743695306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1743695306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy.111490620 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 49984233815 ps |
| CPU time | 1724.63 seconds |
| Started | Oct 09 04:18:50 PM UTC 24 |
| Finished | Oct 09 04:47:54 PM UTC 24 |
| Peak memory | 283064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111490620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.111490620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_entropy_stress.2460962226 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 253808776 ps |
| CPU time | 16.51 seconds |
| Started | Oct 09 04:18:58 PM UTC 24 |
| Finished | Oct 09 04:19:16 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460962226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2460962226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_esc_alert_accum.4147645688 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 12904519807 ps |
| CPU time | 306.45 seconds |
| Started | Oct 09 04:18:32 PM UTC 24 |
| Finished | Oct 09 04:23:44 PM UTC 24 |
| Peak memory | 266932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147645688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4147645688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_lpg.2319797559 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 17622899483 ps |
| CPU time | 1426.89 seconds |
| Started | Oct 09 04:18:52 PM UTC 24 |
| Finished | Oct 09 04:42:55 PM UTC 24 |
| Peak memory | 297392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319797559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2319797559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_ping_timeout.3501331207 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 9745084294 ps |
| CPU time | 263.78 seconds |
| Started | Oct 09 04:18:52 PM UTC 24 |
| Finished | Oct 09 04:23:20 PM UTC 24 |
| Peak memory | 260736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501331207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3501331207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_alerts.3832422392 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 4797482986 ps |
| CPU time | 85.17 seconds |
| Started | Oct 09 04:18:24 PM UTC 24 |
| Finished | Oct 09 04:19:51 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832422392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3832422392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_random_classes.2115500687 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 442547379 ps |
| CPU time | 40.03 seconds |
| Started | Oct 09 04:18:27 PM UTC 24 |
| Finished | Oct 09 04:19:09 PM UTC 24 |
| Peak memory | 260572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115500687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2115500687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/5.alert_handler_smoke.1637264002 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 72310735 ps |
| CPU time | 9.12 seconds |
| Started | Oct 09 04:18:21 PM UTC 24 |
| Finished | Oct 09 04:18:31 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637264002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1637264002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/5.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_alert_accum_saturation.1253071251 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 24568761 ps |
| CPU time | 2.93 seconds |
| Started | Oct 09 04:20:35 PM UTC 24 |
| Finished | Oct 09 04:20:39 PM UTC 24 |
| Peak memory | 260736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253071251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1253071251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy.1821428121 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 15180887687 ps |
| CPU time | 1723.05 seconds |
| Started | Oct 09 04:20:00 PM UTC 24 |
| Finished | Oct 09 04:49:04 PM UTC 24 |
| Peak memory | 299444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821428121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1821428121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_entropy_stress.484677860 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 2267310645 ps |
| CPU time | 23.02 seconds |
| Started | Oct 09 04:20:29 PM UTC 24 |
| Finished | Oct 09 04:20:53 PM UTC 24 |
| Peak memory | 260604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484677860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler- sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.484677860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_alert_accum.2895572486 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 1051056033 ps |
| CPU time | 47.14 seconds |
| Started | Oct 09 04:19:52 PM UTC 24 |
| Finished | Oct 09 04:20:41 PM UTC 24 |
| Peak memory | 260460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895572486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2895572486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_esc_intr_timeout.4089585162 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 1839513153 ps |
| CPU time | 55.31 seconds |
| Started | Oct 09 04:19:50 PM UTC 24 |
| Finished | Oct 09 04:20:46 PM UTC 24 |
| Peak memory | 260660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089585162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.4089585162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg.708984867 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 15768381826 ps |
| CPU time | 1237 seconds |
| Started | Oct 09 04:20:11 PM UTC 24 |
| Finished | Oct 09 04:41:03 PM UTC 24 |
| Peak memory | 293296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708984867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/aler t_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.708984867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_lpg_stub_clk.2929032979 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 24406834345 ps |
| CPU time | 1183.56 seconds |
| Started | Oct 09 04:20:26 PM UTC 24 |
| Finished | Oct 09 04:40:23 PM UTC 24 |
| Peak memory | 299648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929032979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2929032979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_ping_timeout.3517734812 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 30647267016 ps |
| CPU time | 302.62 seconds |
| Started | Oct 09 04:20:03 PM UTC 24 |
| Finished | Oct 09 04:25:10 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517734812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3517734812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_alerts.915009437 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 552170030 ps |
| CPU time | 30.32 seconds |
| Started | Oct 09 04:19:17 PM UTC 24 |
| Finished | Oct 09 04:19:49 PM UTC 24 |
| Peak memory | 266840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915009437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.915009437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_random_classes.3003991823 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 397416763 ps |
| CPU time | 20.6 seconds |
| Started | Oct 09 04:19:48 PM UTC 24 |
| Finished | Oct 09 04:20:10 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003991823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3003991823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_smoke.3292397152 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 3585569577 ps |
| CPU time | 81.02 seconds |
| Started | Oct 09 04:19:10 PM UTC 24 |
| Finished | Oct 09 04:20:33 PM UTC 24 |
| Peak memory | 266668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292397152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3292397152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/6.alert_handler_stress_all.1130553455 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 62896620397 ps |
| CPU time | 1691.49 seconds |
| Started | Oct 09 04:20:34 PM UTC 24 |
| Finished | Oct 09 04:49:06 PM UTC 24 |
| Peak memory | 299508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130553455 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all.1130553455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/6.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_alert_accum_saturation.1937354214 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 139838073 ps |
| CPU time | 5.64 seconds |
| Started | Oct 09 04:21:26 PM UTC 24 |
| Finished | Oct 09 04:21:33 PM UTC 24 |
| Peak memory | 260640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937354214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1937354214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy.2134907384 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 17008507476 ps |
| CPU time | 1936.51 seconds |
| Started | Oct 09 04:21:06 PM UTC 24 |
| Finished | Oct 09 04:53:46 PM UTC 24 |
| Peak memory | 299716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134907384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08 /alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2134907384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_entropy_stress.2586009079 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 344271920 ps |
| CPU time | 21.32 seconds |
| Started | Oct 09 04:21:19 PM UTC 24 |
| Finished | Oct 09 04:21:42 PM UTC 24 |
| Peak memory | 260664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586009079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2586009079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_alert_accum.171345418 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 1119315700 ps |
| CPU time | 55.59 seconds |
| Started | Oct 09 04:20:54 PM UTC 24 |
| Finished | Oct 09 04:21:51 PM UTC 24 |
| Peak memory | 266684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171345418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.171345418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_esc_intr_timeout.4199673914 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 235706796 ps |
| CPU time | 37.19 seconds |
| Started | Oct 09 04:20:47 PM UTC 24 |
| Finished | Oct 09 04:21:26 PM UTC 24 |
| Peak memory | 266604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199673914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4199673914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_lpg_stub_clk.2252154208 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 46176317505 ps |
| CPU time | 1282.33 seconds |
| Started | Oct 09 04:21:18 PM UTC 24 |
| Finished | Oct 09 04:42:55 PM UTC 24 |
| Peak memory | 299520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252154208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2252154208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_ping_timeout.4203905474 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 106320890205 ps |
| CPU time | 231.74 seconds |
| Started | Oct 09 04:21:13 PM UTC 24 |
| Finished | Oct 09 04:25:09 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203905474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.4203905474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_alerts.488082106 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 1368356584 ps |
| CPU time | 65.93 seconds |
| Started | Oct 09 04:20:42 PM UTC 24 |
| Finished | Oct 09 04:21:49 PM UTC 24 |
| Peak memory | 266640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488082106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.488082106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_random_classes.4138339728 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 211785132 ps |
| CPU time | 19.71 seconds |
| Started | Oct 09 04:20:42 PM UTC 24 |
| Finished | Oct 09 04:21:03 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138339728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4138339728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_sig_int_fail.4042901819 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 246207721 ps |
| CPU time | 13.42 seconds |
| Started | Oct 09 04:21:03 PM UTC 24 |
| Finished | Oct 09 04:21:18 PM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042901819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.4042901819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_smoke.956065472 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 1256534445 ps |
| CPU time | 35.69 seconds |
| Started | Oct 09 04:20:40 PM UTC 24 |
| Finished | Oct 09 04:21:17 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956065472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.956065472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/7.alert_handler_stress_all.1564301493 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 73660883484 ps |
| CPU time | 1604.24 seconds |
| Started | Oct 09 04:21:26 PM UTC 24 |
| Finished | Oct 09 04:48:30 PM UTC 24 |
| Peak memory | 299304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564301493 -assert nopostproc +UVM_T ESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all.1564301493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/7.alert_handler_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_alert_accum_saturation.1224329948 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 39638603 ps |
| CPU time | 3.55 seconds |
| Started | Oct 09 04:22:46 PM UTC 24 |
| Finished | Oct 09 04:22:50 PM UTC 24 |
| Peak memory | 260804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224329948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1224329948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy.294766435 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 32645370139 ps |
| CPU time | 2211.93 seconds |
| Started | Oct 09 04:22:01 PM UTC 24 |
| Finished | Oct 09 04:59:20 PM UTC 24 |
| Peak memory | 297476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294766435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.294766435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_entropy_stress.3110028916 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1367075891 ps |
| CPU time | 49.75 seconds |
| Started | Oct 09 04:22:24 PM UTC 24 |
| Finished | Oct 09 04:23:16 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110028916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3110028916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_alert_accum.649534806 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 8698365936 ps |
| CPU time | 281.38 seconds |
| Started | Oct 09 04:21:52 PM UTC 24 |
| Finished | Oct 09 04:26:38 PM UTC 24 |
| Peak memory | 266876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649534806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_es c_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.649534806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_esc_intr_timeout.2772839953 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3412346792 ps |
| CPU time | 23.5 seconds |
| Started | Oct 09 04:21:50 PM UTC 24 |
| Finished | Oct 09 04:22:15 PM UTC 24 |
| Peak memory | 266740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772839953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2772839953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg.3831150904 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 43650921326 ps |
| CPU time | 2563.11 seconds |
| Started | Oct 09 04:22:16 PM UTC 24 |
| Finished | Oct 09 05:05:29 PM UTC 24 |
| Peak memory | 299512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831150904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3831150904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_lpg_stub_clk.2218712071 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 11711929536 ps |
| CPU time | 711.63 seconds |
| Started | Oct 09 04:22:18 PM UTC 24 |
| Finished | Oct 09 04:34:19 PM UTC 24 |
| Peak memory | 283132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218712071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2218712071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_alerts.510967273 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 212150657 ps |
| CPU time | 27.21 seconds |
| Started | Oct 09 04:21:43 PM UTC 24 |
| Finished | Oct 09 04:22:11 PM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510967273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ra ndom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.510967273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_random_classes.1602453757 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 735693531 ps |
| CPU time | 32.86 seconds |
| Started | Oct 09 04:21:49 PM UTC 24 |
| Finished | Oct 09 04:22:23 PM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602453757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1602453757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_sig_int_fail.3583007791 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 246365255 ps |
| CPU time | 21.96 seconds |
| Started | Oct 09 04:21:53 PM UTC 24 |
| Finished | Oct 09 04:22:16 PM UTC 24 |
| Peak memory | 260496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583007791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3583007791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/8.alert_handler_smoke.337630618 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 581844775 ps |
| CPU time | 16.85 seconds |
| Started | Oct 09 04:21:33 PM UTC 24 |
| Finished | Oct 09 04:21:52 PM UTC 24 |
| Peak memory | 260536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337630618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sm oke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/de fault.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.337630618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/8.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_alert_accum_saturation.3567520169 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 167775060 ps |
| CPU time | 5.61 seconds |
| Started | Oct 09 04:23:50 PM UTC 24 |
| Finished | Oct 09 04:23:57 PM UTC 24 |
| Peak memory | 260808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567520169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert _handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3567520169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy.955275946 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 10930559755 ps |
| CPU time | 885.57 seconds |
| Started | Oct 09 04:23:25 PM UTC 24 |
| Finished | Oct 09 04:38:22 PM UTC 24 |
| Peak memory | 283140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955275946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.955275946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_entropy/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_entropy_stress.1759050051 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 167247657 ps |
| CPU time | 16.27 seconds |
| Started | Oct 09 04:23:45 PM UTC 24 |
| Finished | Oct 09 04:24:03 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759050051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert _handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1759050051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_alert_accum.2218046228 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1886568424 ps |
| CPU time | 117.61 seconds |
| Started | Oct 09 04:23:22 PM UTC 24 |
| Finished | Oct 09 04:25:22 PM UTC 24 |
| Peak memory | 266804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218046228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2218046228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_esc_intr_timeout.1068942994 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 407507344 ps |
| CPU time | 52.76 seconds |
| Started | Oct 09 04:23:20 PM UTC 24 |
| Finished | Oct 09 04:24:15 PM UTC 24 |
| Peak memory | 260532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068942994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_e sc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs /coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1068942994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg.3863740596 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 60149765036 ps |
| CPU time | 3481.58 seconds |
| Started | Oct 09 04:23:36 PM UTC 24 |
| Finished | Oct 09 05:22:20 PM UTC 24 |
| Peak memory | 301996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863740596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/ale rt_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3863740596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_lpg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_lpg_stub_clk.1283462805 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 41007559013 ps |
| CPU time | 1294.93 seconds |
| Started | Oct 09 04:23:37 PM UTC 24 |
| Finished | Oct 09 04:45:27 PM UTC 24 |
| Peak memory | 283264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283462805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_tes t +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1283462805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_alerts.2899822408 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 38261549 ps |
| CPU time | 8.74 seconds |
| Started | Oct 09 04:23:09 PM UTC 24 |
| Finished | Oct 09 04:23:19 PM UTC 24 |
| Peak memory | 260468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899822408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2899822408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_random_classes.3909311318 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 1551298612 ps |
| CPU time | 59.11 seconds |
| Started | Oct 09 04:23:16 PM UTC 24 |
| Finished | Oct 09 04:24:17 PM UTC 24 |
| Peak memory | 266620 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909311318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_r andom_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3909311318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_random_classes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_sig_int_fail.1318672826 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 714102705 ps |
| CPU time | 37.68 seconds |
| Started | Oct 09 04:23:24 PM UTC 24 |
| Finished | Oct 09 04:24:03 PM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318672826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s ig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1318672826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_smoke.1417769590 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 464379828 ps |
| CPU time | 36.34 seconds |
| Started | Oct 09 04:22:52 PM UTC 24 |
| Finished | Oct 09 04:23:30 PM UTC 24 |
| Peak memory | 266600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work spaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417769590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_s moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/d efault.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1417769590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default/9.alert_handler_stress_all.314982752 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 25646001359 ps |
| CPU time | 1527.04 seconds |
| Started | Oct 09 04:23:46 PM UTC 24 |
| Finished | Oct 09 04:49:33 PM UTC 24 |
| Peak memory | 299440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314982752 -assert nopostproc +UVM_TE STNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_08/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all.314982752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_08/alert_handler-sim-vcs/9.alert_handler_stress_all/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |