Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	46053	1			T13	609		T147	30		T79	18
class_i[0x1]	57985	1			T45	33		T147	13		T79	245
class_i[0x2]	35446	1			T10	9		T45	2		T17	1
class_i[0x3]	45172	1			T10	300		T13	15		T147	11

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	46483	1			T10	114		T13	13		T45	6
alert[0x1]	46185	1			T10	7		T13	25		T45	6
alert[0x2]	44635	1			T10	184		T13	16		T45	21
alert[0x3]	47353	1			T10	4		T13	570		T45	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

184377

1

T10

309

T13

624

T45

35

esc_ping_fail

279

1

T17

1

T18

4

T19

4

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	46406	1			T10	114		T13	13		T45	6
esc_integrity_fail	alert[0x1]	46113	1			T10	7		T13	25		T45	6
esc_integrity_fail	alert[0x2]	44564	1			T10	184		T13	16		T45	21
esc_integrity_fail	alert[0x3]	47294	1			T10	4		T13	570		T45	2
esc_ping_fail	alert[0x0]	77	1			T18	1		T19	1		T124	2
esc_ping_fail	alert[0x1]	72	1			T18	1		T19	1		T124	1
esc_ping_fail	alert[0x2]	71	1			T18	1		T19	2		T314	1
esc_ping_fail	alert[0x3]	59	1			T17	1		T18	1		T124	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	46022	1			T13	609		T147	30		T79	18
esc_integrity_fail	class_i[0x1]	57889	1			T45	33		T147	13		T79	245
esc_integrity_fail	class_i[0x2]	35371	1			T10	9		T45	2		T147	1
esc_integrity_fail	class_i[0x3]	45095	1			T10	300		T13	15		T147	11
esc_ping_fail	class_i[0x0]	31	1			T19	4		T315	2		T330	1
esc_ping_fail	class_i[0x1]	96	1			T314	3		T322	1		T316	9
esc_ping_fail	class_i[0x2]	75	1			T17	1		T18	4		T124	4
esc_ping_fail	class_i[0x3]	77	1			T288	1		T321	5		T315	2