Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	536682127	0	0	623
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	536682127	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	536682127	536511140	0	0
tb.dut.CheckAccuCntDw	0	0	623	623	0	0
tb.dut.CheckEscCntDw	0	0	623	623	0	0
tb.dut.CheckNAlerts	0	0	623	623	0	0
tb.dut.CheckNClasses	0	0	623	623	0	0
tb.dut.CheckNEscSev	0	0	623	623	0	0
tb.dut.CrashdumpKnownO_A	0	0	536682127	536511140	0	0
tb.dut.EdnKnownO_A	0	0	536682127	536511140	0	0
tb.dut.EscPKnownO_A	0	0	536682127	536511140	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	536682127	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	536682127	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	536682127	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	536682127	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	536682127	80	0	0
tb.dut.IrqAKnownO_A	0	0	536682127	536511140	0	0
tb.dut.IrqBKnownO_A	0	0	536682127	536511140	0	0
tb.dut.IrqCKnownO_A	0	0	536682127	536511140	0	0
tb.dut.IrqDKnownO_A	0	0	536682127	536511140	0	0
tb.dut.TlAReadyKnownO_A	0	0	536682127	536511140	0	0
tb.dut.TlDValidKnownO_A	0	0	536682127	536511140	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	562948672	185899	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	562948672	13665	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	562948672	14916	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	562948672	13860	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	562948672	13744	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	562948672	15169	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	562948672	13524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	562948672	13631	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	562948672	14863	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	562948672	13622	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	562948672	14951	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	562948672	14938	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	562948672	13891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	562948672	14022	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	562948672	15411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	562948672	13852	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	562948672	13523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	562948672	13772	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	562948672	13766	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	562948672	14982	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	562948672	13842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	562948672	15094	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	562948672	15131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	562948672	13793	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	562948672	13608	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	562948672	13687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	562948672	14074	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	562948672	14668	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	562948672	15006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	562948672	14558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	562948672	14677	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	562948672	14872	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	562948672	13635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	562948672	13902	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	562948672	14921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	562948672	14990	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	562948672	13526	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	562948672	16190	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	562948672	14063	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	562948672	14731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	562948672	13735	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	562948672	13724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	562948672	15997	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	562948672	13637	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	562948672	15009	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	562948672	14038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	562948672	13777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	562948672	13799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	562948672	15083	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	562948672	14772	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	562948672	14946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	562948672	15921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	562948672	15119	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	562948672	13722	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	562948672	13859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	562948672	13561	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	562948672	14965	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	562948672	13787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	562948672	14918	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	562948672	14536	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	562948672	14783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	562948672	13803	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	562948672	14312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	562948672	14795	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	562948672	14891	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	562948672	14463	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	562948672	14818	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	562948672	15025	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	562948672	14979	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	562948672	15014	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	562948672	26473	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	562948672	14622	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	562948672	15095	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	562948672	14957	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	562948672	13724	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	562948672	13624	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	562948672	13786	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	562948672	13692	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	562948672	13577	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	536682127	4119	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	536682127	154282	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	536682127	280486059	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	536682127	294	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	536682127	757	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	536682127	45	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	536682127	366	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	536485196	228968521	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	536682127	832	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	536682127	807	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	536682127	791	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	536682127	773	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	536682127	587	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	536682127	73291	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	536682127	485	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	536682127	53	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	536682127	1317	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	536682127	1077	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	536483884	536415576	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	536682127	536511140	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	536682127	4687	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	536682127	124599	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	536682127	320372827	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	536682127	234	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	536682127	423	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	536682127	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	536682127	179	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	536485196	261059078	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	536682127	497	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	536682127	482	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	536682127	474	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	536682127	468	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	536682127	510	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	536682127	64694	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	536682127	424	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	536682127	58	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	536682127	1323	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	536682127	1083	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	536483884	536415576	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	536682127	536511140	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	536682127	1364	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	536682127	176940	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	536682127	283515367	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	536682127	232	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	536682127	517	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	536682127	16	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	536682127	259	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	536485196	227986287	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	536682127	576	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	536682127	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	536682127	555	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	536682127	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	536682127	660	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	536682127	76169	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	536682127	575	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	536682127	66	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	536682127	1276	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	536682127	1036	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	536483884	536415576	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	536682127	536511140	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	536682127	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	536682127	5253	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	536682127	119831	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	536682127	312847336	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	536682127	229	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	536682127	462	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	536682127	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	536682127	193	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	536485196	223143075	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	536682127	523	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	536682127	512	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	536682127	507	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	536682127	498	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	536682127	471	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	536682127	60267	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	536682127	396	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	536682127	51	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	536682127	1228	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	536682127	988	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	536483884	536415576	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	536682127	536511140	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	562948672	81036933	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	562948672	562248688	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	562948672	562248688	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	562948672	143289234	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	562948672	562248688	0	0
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