Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	149	1			T36	1		T47	2		T50	1
index[0x1]	145	1			T13	1		T26	1		T45	1
index[0x2]	146	1			T26	1		T38	1		T45	1
index[0x3]	155	1			T10	2		T12	1		T45	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	198	1			T10	1		T45	1		T36	1
lens_less_than_1000[1]	103	1			T13	1		T38	1		T45	2
lens_less_than_1000[2]	85	1			T12	1		T50	2		T121	1
lens_less_than_1000[3]	63	1			T26	1		T147	1		T121	1
lens_less_than_1000[4]	37	1			T231	1		T54	1		T40	1
lens_less_than_1000[5]	34	1			T54	1		T57	1		T115	1
lens_less_than_1000[6]	35	1			T10	1		T26	1		T265	1
lens_less_than_1000[7]	17	1			T142	3		T91	1		T266	1
lens_less_than_1000[8]	11	1			T59	1		T267	1		T268	1
lens_less_than_1000[9]	2	1			T262	1		T269	1		-	-
len_2	10	1			T56	1		T115	1		T100	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x1]]	[len_2]	0	1	1
[index[0x2] , index[0x3]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	59	1			T36	1		T47	1		T50	1
index[0x0]	lens_less_than_1000[1]	25	1			T47	1		T213	1		T270	1
index[0x0]	lens_less_than_1000[2]	13	1			T53	1		T99	1		T271	1
index[0x0]	lens_less_than_1000[3]	19	1			T147	1		T121	1		T73	1
index[0x0]	lens_less_than_1000[4]	4	1			T40	1		T272	1		T273	1
index[0x0]	lens_less_than_1000[5]	4	1			T57	1		T274	1		T107	1
index[0x0]	lens_less_than_1000[6]	11	1			T115	1		T107	1		T275	4
index[0x0]	lens_less_than_1000[7]	7	1			T142	3		T266	1		T136	1
index[0x0]	lens_less_than_1000[8]	1	1			T268	1		-	-		-	-
index[0x0]	len_2	6	1			T56	1		T115	1		T276	3
index[0x1]	lens_less_than_1000[0]	53	1			T277	1		T54	1		T278	1
index[0x1]	lens_less_than_1000[1]	31	1			T13	1		T45	1		T36	1
index[0x1]	lens_less_than_1000[2]	17	1			T29	1		T235	1		T279	1
index[0x1]	lens_less_than_1000[3]	14	1			T26	1		T29	1		T93	1
index[0x1]	lens_less_than_1000[4]	12	1			T90	1		T265	1		T120	1
index[0x1]	lens_less_than_1000[5]	6	1			T280	1		T281	1		T251	1
index[0x1]	lens_less_than_1000[6]	3	1			T282	1		T262	1		T283	1
index[0x1]	lens_less_than_1000[7]	2	1			T258	1		T284	1		-	-
index[0x1]	lens_less_than_1000[8]	5	1			T285	1		T286	3		T287	1
index[0x1]	lens_less_than_1000[9]	2	1			T262	1		T269	1		-	-
index[0x2]	lens_less_than_1000[0]	32	1			T41	1		T133	1		T288	1
index[0x2]	lens_less_than_1000[1]	24	1			T38	1		T45	1		T289	1
index[0x2]	lens_less_than_1000[2]	24	1			T121	1		T84	1		T86	2
index[0x2]	lens_less_than_1000[3]	22	1			T290	1		T291	1		T274	1
index[0x2]	lens_less_than_1000[4]	18	1			T231	1		T92	1		T292	3
index[0x2]	lens_less_than_1000[5]	7	1			T137	1		T293	1		T261	2
index[0x2]	lens_less_than_1000[6]	9	1			T26	1		T275	3		T101	1
index[0x2]	lens_less_than_1000[7]	6	1			T286	3		T294	1		T295	1
index[0x2]	lens_less_than_1000[8]	2	1			T100	2		-	-		-	-
index[0x2]	len_2	2	1			T100	1		T132	1		-	-
index[0x3]	lens_less_than_1000[0]	54	1			T10	1		T45	1		T122	1
index[0x3]	lens_less_than_1000[1]	23	1			T39	1		T296	1		T57	1
index[0x3]	lens_less_than_1000[2]	31	1			T12	1		T50	2		T73	5
index[0x3]	lens_less_than_1000[3]	8	1			T271	1		T100	1		T297	1
index[0x3]	lens_less_than_1000[4]	3	1			T54	1		T77	1		T298	1
index[0x3]	lens_less_than_1000[5]	17	1			T54	1		T115	1		T274	1
index[0x3]	lens_less_than_1000[6]	12	1			T10	1		T265	1		T129	1
index[0x3]	lens_less_than_1000[7]	2	1			T91	1		T299	1		-	-
index[0x3]	lens_less_than_1000[8]	3	1			T59	1		T267	1		T300	1
index[0x3]	len_2	2	1			T215	2		-	-		-	-