Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	53	1			T13	1		T41	2		T53	1
class_index[0x1]	58	1			T36	3		T37	1		T40	1
class_index[0x2]	66	1			T79	1		T41	1		T28	1
class_index[0x3]	51	1			T13	1		T36	1		T79	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	87	1			T13	1		T37	1		T41	1
intr_timeout_cnt[1]	54	1			T41	1		T142	1		T85	1
intr_timeout_cnt[2]	22	1			T13	1		T41	1		T40	2
intr_timeout_cnt[3]	8	1			T79	1		T31	1		T239	2
intr_timeout_cnt[4]	8	1			T53	1		T40	1		T240	1
intr_timeout_cnt[5]	9	1			T88	1		T97	1		T109	2
intr_timeout_cnt[6]	5	1			T241	1		T215	1		T109	1
intr_timeout_cnt[7]	12	1			T36	1		T77	1		T31	1
intr_timeout_cnt[8]	11	1			T36	3		T77	1		T31	1
intr_timeout_cnt[9]	12	1			T79	1		T125	1		T240	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6]]	--	--	2

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	21	1			T85	1		T87	1		T61	1
class_index[0x0]	intr_timeout_cnt[1]	8	1			T41	1		T125	1		T242	1
class_index[0x0]	intr_timeout_cnt[2]	7	1			T13	1		T41	1		T86	2
class_index[0x0]	intr_timeout_cnt[3]	2	1			T239	1		T243	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T53	1		T244	1		T245	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T109	1		T246	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	4	1			T241	1		T215	1		T109	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T31	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T77	1		T247	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T125	1		T248	1		T249	1
class_index[0x1]	intr_timeout_cnt[0]	16	1			T37	1		T40	1		T84	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T85	1		T87	1		T90	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T92	2		T125	1		T250	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T245	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T251	3		-	-		-	-
class_index[0x1]	intr_timeout_cnt[5]	6	1			T88	1		T109	1		T252	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T253	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	3	1			T254	1		T125	1		T247	1
class_index[0x1]	intr_timeout_cnt[8]	4	1			T36	3		T31	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	29	1			T41	1		T28	1		T77	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T86	2		T120	1		T255	1
class_index[0x2]	intr_timeout_cnt[2]	6	1			T40	2		T31	1		T256	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T239	1		T118	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	1	1			T240	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T97	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	3	1			T257	1		T109	2		-	-
class_index[0x2]	intr_timeout_cnt[8]	4	1			T258	1		T109	1		T248	1
class_index[0x2]	intr_timeout_cnt[9]	4	1			T79	1		T252	1		T259	1
class_index[0x3]	intr_timeout_cnt[0]	21	1			T13	1		T40	1		T143	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T142	1		T87	2		T111	1
class_index[0x3]	intr_timeout_cnt[2]	2	1			T254	1		T260	1		-	-
class_index[0x3]	intr_timeout_cnt[3]	2	1			T79	1		T31	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T40	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	5	1			T36	1		T77	1		T125	3
class_index[0x3]	intr_timeout_cnt[8]	1	1			T261	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	5	1			T240	1		T109	1		T262	1