Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284846	1			T2	3		T10	5		T11	3
all_values[1]	284846	1			T2	3		T10	5		T11	3
all_values[2]	284846	1			T2	3		T10	5		T11	3
all_values[3]	284846	1			T2	3		T10	5		T11	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

566130

1

T2

9

T10

12

T11

3

auto[1]

573254

1

T2

3

T10

8

T11

9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

679780

1

T2

8

T10

4

T11

12

auto[1]

459604

1

T2

4

T10

16

T20

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82569	1			T10	1		T20	4		T15	5
all_values[0]	auto[0]	auto[1]	58674	1			T10	3		T20	3		T15	3
all_values[0]	auto[1]	auto[0]	84498	1			T2	2		T11	3		T20	1
all_values[0]	auto[1]	auto[1]	59105	1			T2	1		T10	1		T20	1
all_values[1]	auto[0]	auto[0]	83899	1			T2	2		T10	1		T11	3
all_values[1]	auto[0]	auto[1]	57728	1			T2	1		T10	4		T13	4
all_values[1]	auto[1]	auto[0]	85377	1			T20	5		T15	14		T13	2
all_values[1]	auto[1]	auto[1]	57842	1			T13	4		T12	1		T26	6
all_values[2]	auto[0]	auto[0]	84585	1			T2	2		T20	7		T15	8
all_values[2]	auto[0]	auto[1]	56738	1			T2	1		T10	2		T13	4
all_values[2]	auto[1]	auto[0]	86304	1			T10	1		T11	3		T20	2
all_values[2]	auto[1]	auto[1]	57219	1			T10	2		T13	2		T12	3
all_values[3]	auto[0]	auto[0]	85711	1			T2	2		T20	7		T15	13
all_values[3]	auto[0]	auto[1]	56226	1			T2	1		T10	1		T13	6
all_values[3]	auto[1]	auto[0]	86837	1			T10	1		T11	3		T20	2
all_values[3]	auto[1]	auto[1]	56072	1			T10	3		T13	4		T12	1