Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	284846	1			T2	3		T10	5		T11	3
all_pins[1]	284846	1			T2	3		T10	5		T11	3
all_pins[2]	284846	1			T2	3		T10	5		T11	3
all_pins[3]	284846	1			T2	3		T10	5		T11	3

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	909146	1			T2	11		T10	14		T11	12
values[0x1]	230238	1			T2	1		T10	6		T20	1
transitions[0x0=>0x1]	152468	1			T10	3		T20	1		T15	4
transitions[0x1=>0x0]	152714	1			T2	1		T10	3		T20	1

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	225741	1			T2	2		T10	4		T11	3
all_pins[0]	values[0x1]	59105	1			T2	1		T10	1		T20	1
all_pins[0]	transitions[0x0=>0x1]	58587	1			T20	1		T15	4		T13	2
all_pins[0]	transitions[0x1=>0x0]	55800	1			T10	2		T13	2		T12	1
all_pins[1]	values[0x0]	227004	1			T2	3		T10	5		T11	3
all_pins[1]	values[0x1]	57842	1			T13	4		T12	1		T26	6
all_pins[1]	transitions[0x0=>0x1]	31999	1			T13	1		T12	1		T26	3
all_pins[1]	transitions[0x1=>0x0]	33262	1			T2	1		T10	1		T20	1
all_pins[2]	values[0x0]	227627	1			T2	3		T10	3		T11	3
all_pins[2]	values[0x1]	57219	1			T10	2		T13	2		T12	3
all_pins[2]	transitions[0x0=>0x1]	31242	1			T10	2		T13	1		T12	2
all_pins[2]	transitions[0x1=>0x0]	31865	1			T13	3		T26	5		T38	3
all_pins[3]	values[0x0]	228774	1			T2	3		T10	2		T11	3
all_pins[3]	values[0x1]	56072	1			T10	3		T13	4		T12	1
all_pins[3]	transitions[0x0=>0x1]	30640	1			T10	1		T13	4		T12	1
all_pins[3]	transitions[0x1=>0x0]	31787	1			T13	2		T12	3		T26	2