Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1			T197	4		T198	4		T229	7
all_values[1]	281	1			T197	4		T198	4		T229	7
all_values[2]	281	1			T197	4		T198	4		T229	7
all_values[3]	281	1			T197	4		T198	4		T229	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

615

1

T197

6

T198

16

T229

14

auto[1]

509

1

T197

10

T229

14

T367

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

426

1

T197

8

T198

8

T229

9

auto[1]

698

1

T197

8

T198

8

T229

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668

1

T197

11

T198

11

T229

15

auto[1]

456

1

T197

5

T198

5

T229

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

59

1

T197

3

T198

2

T229

1

all_values[0]

auto[0]

auto[0]

auto[1]

34

1

T198

1

T229

1

T367

1

all_values[0]

auto[0]

auto[1]

auto[0]

57

1

T197

1

T229

2

T367

1

all_values[0]

auto[0]

auto[1]

auto[1]

23

1

T368

1

T369

1

T370

1

all_values[0]

auto[1]

auto[0]

auto[1]

63

1

T198

1

T229

3

T367

2

all_values[0]

auto[1]

auto[1]

auto[1]

45

1

T367

1

T368

2

T370

4

all_values[1]

auto[0]

auto[0]

auto[0]

57

1

T197

1

T198

2

T229

2

all_values[1]

auto[0]

auto[0]

auto[1]

29

1

T198

1

T371

1

T372

2

all_values[1]

auto[0]

auto[1]

auto[0]

53

1

T229

1

T367

2

T373

2

all_values[1]

auto[0]

auto[1]

auto[1]

31

1

T197

1

T229

2

T373

1

all_values[1]

auto[1]

auto[0]

auto[1]

72

1

T198

1

T229

1

T367

4

all_values[1]

auto[1]

auto[1]

auto[1]

39

1

T197

2

T229

1

T374

1

all_values[2]

auto[0]

auto[0]

auto[0]

52

1

T198

2

T367

2

T374

1

all_values[2]

auto[0]

auto[0]

auto[1]

29

1

T229

1

T367

1

T373

1

all_values[2]

auto[0]

auto[1]

auto[0]

45

1

T197

1

T229

2

T367

1

all_values[2]

auto[0]

auto[1]

auto[1]

39

1

T197

1

T367

1

T374

1

all_values[2]

auto[1]

auto[0]

auto[1]

64

1

T197

1

T198

2

T229

2

all_values[2]

auto[1]

auto[1]

auto[1]

52

1

T197

1

T229

2

T367

1

all_values[3]

auto[0]

auto[0]

auto[0]

61

1

T197

1

T198

2

T229

1

all_values[3]

auto[0]

auto[0]

auto[1]

32

1

T198

1

T367

2

T374

1

all_values[3]

auto[0]

auto[1]

auto[0]

42

1

T197

1

T373

1

T375

1

all_values[3]

auto[0]

auto[1]

auto[1]

25

1

T197

1

T229

2

T367

1

all_values[3]

auto[1]

auto[0]

auto[1]

63

1

T198

1

T229

2

T367

1

all_values[3]

auto[1]

auto[1]

auto[1]

58

1

T197

1

T229

2

T367

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal