Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	71931	1			T231	18		T235	827		T308	227
accum_cnt_1000	165224	1			T10	1		T13	1		T35	86
accum_cnt_100	20504	1			T44	4		T68	2		T32	3
accum_cnt_50	55759	1			T20	5		T13	2		T25	17
accum_cnt_10	164531	1			T2	2		T10	13		T20	1
accum_cnt_0	336335	1			T2	6		T10	6		T11	4

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	211132	1			T2	2		T10	5		T11	1
class_index[0x1]	211132	1			T2	2		T10	5		T11	1
class_index[0x2]	211132	1			T2	2		T10	5		T11	1
class_index[0x3]	211132	1			T2	2		T10	5		T11	1

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20890	1			T231	18		T235	467		T31	100
class_index[0x0]	accum_cnt_1000	41279	1			T13	1		T35	36		T121	28
class_index[0x0]	accum_cnt_100	5577	1			T44	4		T32	3		T35	18
class_index[0x0]	accum_cnt_50	15510	1			T20	5		T13	1		T25	17
class_index[0x0]	accum_cnt_10	34101	1			T2	1		T10	2		T20	1
class_index[0x0]	accum_cnt_0	86616	1			T2	1		T10	3		T11	1
class_index[0x1]	accum_cnt_2000	16715	1			T308	227		T309	141		T62	6
class_index[0x1]	accum_cnt_1000	38638	1			T35	50		T113	5		T79	12
class_index[0x1]	accum_cnt_100	4304	1			T37	2		T35	13		T113	13
class_index[0x1]	accum_cnt_50	13242	1			T26	10		T38	7		T68	26
class_index[0x1]	accum_cnt_10	37558	1			T2	1		T10	5		T13	13
class_index[0x1]	accum_cnt_0	93704	1			T2	1		T11	1		T20	6
class_index[0x2]	accum_cnt_2000	21732	1			T235	360		T310	235		T311	546
class_index[0x2]	accum_cnt_1000	47937	1			T121	42		T54	2		T76	17
class_index[0x2]	accum_cnt_100	5383	1			T68	2		T112	12		T121	18
class_index[0x2]	accum_cnt_50	12097	1			T26	2		T68	24		T112	16
class_index[0x2]	accum_cnt_10	40799	1			T10	2		T13	3		T12	5
class_index[0x2]	accum_cnt_0	73519	1			T2	2		T10	3		T11	1
class_index[0x3]	accum_cnt_2000	12594	1			T128	18		T312	565		T310	242
class_index[0x3]	accum_cnt_1000	37370	1			T10	1		T113	1		T213	37
class_index[0x3]	accum_cnt_100	5240	1			T112	8		T113	18		T123	14
class_index[0x3]	accum_cnt_50	14910	1			T13	1		T26	10		T68	26
class_index[0x3]	accum_cnt_10	52073	1			T10	4		T13	10		T26	4
class_index[0x3]	accum_cnt_0	82496	1			T2	2		T11	1		T20	6