Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2014	1			T17	1		T19	1		T288	1
alert[0x1]	6963	1			T19	1		T314	1		T54	1
alert[0x2]	3600	1			T147	14		T54	7		T57	1
alert[0x3]	2080	1			T79	2		T124	1		T54	2
alert[0x4]	5766	1			T28	2		T233	14		T315	1
alert[0x5]	1130	1			T147	2		T18	1		T76	49
alert[0x6]	1735	1			T13	1		T18	1		T124	1
alert[0x7]	2153	1			T28	26		T316	1		T236	1
alert[0x8]	7827	1			T79	3		T76	13		T28	2
alert[0x9]	7666	1			T147	2		T28	2		T288	1
alert[0xa]	4904	1			T54	5		T317	1		T28	8
alert[0xb]	3429	1			T19	3		T54	1		T317	1
alert[0xc]	1895	1			T41	2		T314	1		T317	1
alert[0xd]	3119	1			T231	5		T317	2		T318	97
alert[0xe]	9702	1			T54	1		T28	1		T316	1
alert[0xf]	2871	1			T54	1		T29	30		T236	8
alert[0x10]	3662	1			T314	1		T317	1		T30	1
alert[0x11]	3015	1			T319	2		T57	1		T31	13
alert[0x12]	5621	1			T233	2		T58	1		T91	1
alert[0x13]	6251	1			T18	1		T236	2		T320	1
alert[0x14]	3057	1			T316	1		T321	1		T91	9
alert[0x15]	14133	1			T231	2		T76	3		T316	1
alert[0x16]	1330	1			T10	7		T79	1		T76	1
alert[0x17]	6589	1			T54	2		T76	3		T28	4
alert[0x18]	4307	1			T19	1		T41	2		T231	3
alert[0x19]	4901	1			T147	1		T322	1		T54	5
alert[0x1a]	3263	1			T231	3		T236	1		T233	1
alert[0x1b]	2966	1			T13	12		T18	1		T79	1
alert[0x1c]	9130	1			T119	1		T54	2		T29	2
alert[0x1d]	2441	1			T18	1		T124	1		T231	4
alert[0x1e]	1430	1			T319	1		T323	1		T61	9
alert[0x1f]	7536	1			T79	26		T28	56		T320	1
alert[0x20]	1058	1			T79	3		T76	1		T233	6
alert[0x21]	1296	1			T322	1		T288	1		T323	1
alert[0x22]	5550	1			T13	3		T45	5		T314	1
alert[0x23]	1343	1			T13	8		T17	1		T28	27
alert[0x24]	1886	1			T231	1		T89	2		T318	18
alert[0x25]	1549	1			T10	1		T28	42		T236	6
alert[0x26]	3280	1			T147	4		T54	7		T142	3
alert[0x27]	1838	1			T45	1		T19	1		T236	2
alert[0x28]	3261	1			T124	1		T314	1		T322	1
alert[0x29]	4853	1			T17	1		T236	2		T288	3
alert[0x2a]	4441	1			T17	1		T76	7		T28	1
alert[0x2b]	1688	1			T231	18		T316	1		T320	1
alert[0x2c]	1544	1			T13	1		T124	1		T320	1
alert[0x2d]	6715	1			T19	1		T317	1		T316	1
alert[0x2e]	1697	1			T45	1		T314	1		T322	2
alert[0x2f]	2846	1			T322	1		T317	1		T316	1
alert[0x30]	2895	1			T314	1		T316	1		T57	1
alert[0x31]	1815	1			T54	6		T28	2		T316	1
alert[0x32]	2879	1			T147	1		T124	2		T236	14
alert[0x33]	2916	1			T79	1		T54	37		T321	1
alert[0x34]	2699	1			T28	1		T319	1		T77	1
alert[0x35]	1711	1			T147	4		T319	1		T320	1
alert[0x36]	6028	1			T13	2		T28	2		T91	2
alert[0x37]	5165	1			T28	5		T320	1		T233	6
alert[0x38]	2069	1			T18	1		T231	11		T54	1
alert[0x39]	4726	1			T319	1		T323	1		T324	1
alert[0x3a]	4573	1			T19	2		T316	1		T288	1
alert[0x3b]	6930	1			T54	1		T76	1		T319	1
alert[0x3c]	4330	1			T54	8		T76	3		T28	46
alert[0x3d]	4564	1			T18	1		T124	1		T314	1
alert[0x3e]	2051	1			T45	4		T119	1		T28	3
alert[0x3f]	3223	1			T18	1		T79	1		T28	36
alert[0x40]	5941	1			T231	3		T31	17		T91	14

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	32794	1			T13	27		T45	4		T147	12
class_i[0x1]	101786	1			T45	6		T17	3		T147	1
class_i[0x2]	81760	1			T45	1		T17	1		T147	15
class_i[0x3]	39506	1			T10	8		T79	32		T19	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

255170

1

T10

8

T13

27

T45

11

alert_ping_fail

676

1

T17

4

T18

8

T19

10

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2002	1			T58	1		T34	77		T95	8
alert_integrity_fail	alert[0x1]	6945	1			T54	1		T28	1		T30	2
alert_integrity_fail	alert[0x2]	3593	1			T147	14		T54	7		T57	1
alert_integrity_fail	alert[0x3]	2070	1			T79	2		T54	2		T29	2
alert_integrity_fail	alert[0x4]	5762	1			T28	2		T233	14		T91	14
alert_integrity_fail	alert[0x5]	1117	1			T147	2		T76	49		T28	3
alert_integrity_fail	alert[0x6]	1720	1			T13	1		T119	1		T76	1
alert_integrity_fail	alert[0x7]	2133	1			T28	26		T236	1		T89	1
alert_integrity_fail	alert[0x8]	7818	1			T79	3		T76	13		T28	2
alert_integrity_fail	alert[0x9]	7660	1			T147	2		T28	2		T77	1
alert_integrity_fail	alert[0xa]	4888	1			T54	5		T28	8		T233	7
alert_integrity_fail	alert[0xb]	3416	1			T54	1		T233	7		T318	14
alert_integrity_fail	alert[0xc]	1883	1			T41	2		T274	4		T129	19
alert_integrity_fail	alert[0xd]	3111	1			T231	5		T318	97		T34	82
alert_integrity_fail	alert[0xe]	9695	1			T54	1		T28	1		T77	1
alert_integrity_fail	alert[0xf]	2864	1			T54	1		T29	30		T236	8
alert_integrity_fail	alert[0x10]	3655	1			T30	1		T235	1		T318	24
alert_integrity_fail	alert[0x11]	3001	1			T57	1		T31	13		T91	1
alert_integrity_fail	alert[0x12]	5615	1			T233	2		T58	1		T91	1
alert_integrity_fail	alert[0x13]	6240	1			T236	2		T235	12		T89	3
alert_integrity_fail	alert[0x14]	3049	1			T91	9		T34	7		T61	1
alert_integrity_fail	alert[0x15]	14120	1			T231	2		T76	3		T77	3
alert_integrity_fail	alert[0x16]	1314	1			T10	7		T79	1		T76	1
alert_integrity_fail	alert[0x17]	6574	1			T54	2		T76	3		T28	4
alert_integrity_fail	alert[0x18]	4302	1			T41	2		T231	3		T76	4
alert_integrity_fail	alert[0x19]	4890	1			T147	1		T54	5		T28	9
alert_integrity_fail	alert[0x1a]	3257	1			T231	3		T236	1		T233	1
alert_integrity_fail	alert[0x1b]	2960	1			T13	12		T79	1		T54	3
alert_integrity_fail	alert[0x1c]	9120	1			T119	1		T54	2		T29	2
alert_integrity_fail	alert[0x1d]	2431	1			T231	4		T30	52		T34	56
alert_integrity_fail	alert[0x1e]	1422	1			T61	9		T274	19		T258	41
alert_integrity_fail	alert[0x1f]	7525	1			T79	26		T28	56		T89	1
alert_integrity_fail	alert[0x20]	1044	1			T79	3		T76	1		T233	6
alert_integrity_fail	alert[0x21]	1287	1			T318	589		T61	2		T325	2
alert_integrity_fail	alert[0x22]	5534	1			T13	3		T45	5		T54	2
alert_integrity_fail	alert[0x23]	1334	1			T13	8		T28	27		T318	316
alert_integrity_fail	alert[0x24]	1881	1			T231	1		T89	2		T318	18
alert_integrity_fail	alert[0x25]	1543	1			T10	1		T28	42		T236	6
alert_integrity_fail	alert[0x26]	3269	1			T147	4		T54	7		T142	3
alert_integrity_fail	alert[0x27]	1833	1			T45	1		T236	2		T233	1
alert_integrity_fail	alert[0x28]	3249	1			T77	3		T89	26		T318	277
alert_integrity_fail	alert[0x29]	4839	1			T236	2		T235	3		T318	27
alert_integrity_fail	alert[0x2a]	4431	1			T76	7		T28	1		T30	7
alert_integrity_fail	alert[0x2b]	1672	1			T231	18		T235	3		T57	13
alert_integrity_fail	alert[0x2c]	1534	1			T13	1		T61	1		T95	6
alert_integrity_fail	alert[0x2d]	6698	1			T77	29		T34	318		T60	2
alert_integrity_fail	alert[0x2e]	1685	1			T45	1		T76	7		T31	1
alert_integrity_fail	alert[0x2f]	2832	1			T30	1		T34	29		T98	51
alert_integrity_fail	alert[0x30]	2885	1			T57	1		T31	2		T91	1
alert_integrity_fail	alert[0x31]	1804	1			T54	6		T28	2		T236	12
alert_integrity_fail	alert[0x32]	2871	1			T147	1		T236	14		T235	1
alert_integrity_fail	alert[0x33]	2904	1			T79	1		T54	37		T57	1
alert_integrity_fail	alert[0x34]	2689	1			T28	1		T77	1		T91	3
alert_integrity_fail	alert[0x35]	1706	1			T147	4		T89	2		T326	1
alert_integrity_fail	alert[0x36]	6017	1			T13	2		T28	2		T91	2
alert_integrity_fail	alert[0x37]	5158	1			T28	5		T233	6		T31	30
alert_integrity_fail	alert[0x38]	2060	1			T231	11		T54	1		T142	7
alert_integrity_fail	alert[0x39]	4715	1			T130	7		T268	1		T98	199
alert_integrity_fail	alert[0x3a]	4563	1			T30	2		T235	2		T318	60
alert_integrity_fail	alert[0x3b]	6916	1			T54	1		T76	1		T30	1
alert_integrity_fail	alert[0x3c]	4317	1			T54	8		T76	3		T28	46
alert_integrity_fail	alert[0x3d]	4551	1			T54	1		T30	3		T31	1
alert_integrity_fail	alert[0x3e]	2039	1			T45	4		T119	1		T28	3
alert_integrity_fail	alert[0x3f]	3219	1			T79	1		T28	36		T89	6
alert_integrity_fail	alert[0x40]	5939	1			T231	3		T31	17		T91	14
alert_ping_fail	alert[0x0]	12	1			T17	1		T19	1		T288	1
alert_ping_fail	alert[0x1]	18	1			T19	1		T314	1		T317	1
alert_ping_fail	alert[0x2]	7	1			T327	1		T328	1		T329	1
alert_ping_fail	alert[0x3]	10	1			T124	1		T330	1		T331	1
alert_ping_fail	alert[0x4]	4	1			T315	1		T323	1		T330	1
alert_ping_fail	alert[0x5]	13	1			T18	1		T288	1		T320	1
alert_ping_fail	alert[0x6]	15	1			T18	1		T124	1		T314	1
alert_ping_fail	alert[0x7]	20	1			T316	1		T288	1		T301	1
alert_ping_fail	alert[0x8]	9	1			T288	2		T315	1		T324	1
alert_ping_fail	alert[0x9]	6	1			T288	1		T321	1		T328	1
alert_ping_fail	alert[0xa]	16	1			T317	1		T319	1		T302	1
alert_ping_fail	alert[0xb]	13	1			T19	3		T317	1		T332	1
alert_ping_fail	alert[0xc]	12	1			T314	1		T317	1		T320	1
alert_ping_fail	alert[0xd]	8	1			T317	2		T333	1		T334	1
alert_ping_fail	alert[0xe]	7	1			T316	1		T321	1		T265	1
alert_ping_fail	alert[0xf]	7	1			T330	1		T328	1		T335	1
alert_ping_fail	alert[0x10]	7	1			T314	1		T317	1		T102	1
alert_ping_fail	alert[0x11]	14	1			T319	2		T315	1		T265	1
alert_ping_fail	alert[0x12]	6	1			T336	1		T265	1		T327	1
alert_ping_fail	alert[0x13]	11	1			T18	1		T320	1		T292	1
alert_ping_fail	alert[0x14]	8	1			T316	1		T321	1		T337	1
alert_ping_fail	alert[0x15]	13	1			T316	1		T319	1		T315	1
alert_ping_fail	alert[0x16]	16	1			T316	1		T319	1		T321	2
alert_ping_fail	alert[0x17]	15	1			T316	1		T330	2		T338	2
alert_ping_fail	alert[0x18]	5	1			T19	1		T314	1		T323	2
alert_ping_fail	alert[0x19]	11	1			T322	1		T317	1		T323	1
alert_ping_fail	alert[0x1a]	6	1			T315	1		T339	1		T335	1
alert_ping_fail	alert[0x1b]	6	1			T18	1		T319	1		T315	1
alert_ping_fail	alert[0x1c]	10	1			T319	1		T320	1		T323	1
alert_ping_fail	alert[0x1d]	10	1			T18	1		T124	1		T323	2
alert_ping_fail	alert[0x1e]	8	1			T319	1		T323	1		T330	1
alert_ping_fail	alert[0x1f]	11	1			T320	1		T332	1		T334	1
alert_ping_fail	alert[0x20]	14	1			T321	1		T315	1		T328	1
alert_ping_fail	alert[0x21]	9	1			T322	1		T288	1		T323	1
alert_ping_fail	alert[0x22]	16	1			T314	1		T319	2		T336	1
alert_ping_fail	alert[0x23]	9	1			T17	1		T324	1		T265	1
alert_ping_fail	alert[0x24]	5	1			T336	1		T340	1		T341	2
alert_ping_fail	alert[0x25]	6	1			T319	1		T327	1		T328	1
alert_ping_fail	alert[0x26]	11	1			T316	1		T332	1		T331	1
alert_ping_fail	alert[0x27]	5	1			T19	1		T334	1		T335	2
alert_ping_fail	alert[0x28]	12	1			T124	1		T314	1		T322	1
alert_ping_fail	alert[0x29]	14	1			T17	1		T288	3		T315	2
alert_ping_fail	alert[0x2a]	10	1			T17	1		T324	1		T330	1
alert_ping_fail	alert[0x2b]	16	1			T316	1		T320	1		T321	1
alert_ping_fail	alert[0x2c]	10	1			T124	1		T320	1		T323	1
alert_ping_fail	alert[0x2d]	17	1			T19	1		T317	1		T316	1
alert_ping_fail	alert[0x2e]	12	1			T314	1		T322	2		T315	1
alert_ping_fail	alert[0x2f]	14	1			T322	1		T317	1		T316	1
alert_ping_fail	alert[0x30]	10	1			T314	1		T316	1		T336	1
alert_ping_fail	alert[0x31]	11	1			T316	1		T336	1		T327	1
alert_ping_fail	alert[0x32]	8	1			T124	2		T288	1		T320	1
alert_ping_fail	alert[0x33]	12	1			T321	1		T315	1		T323	1
alert_ping_fail	alert[0x34]	10	1			T319	1		T336	1		T337	1
alert_ping_fail	alert[0x35]	5	1			T319	1		T320	1		T102	1
alert_ping_fail	alert[0x36]	11	1			T330	1		T338	1		T329	1
alert_ping_fail	alert[0x37]	7	1			T320	1		T321	1		T323	1
alert_ping_fail	alert[0x38]	9	1			T18	1		T316	1		T315	1
alert_ping_fail	alert[0x39]	11	1			T319	1		T323	1		T324	1
alert_ping_fail	alert[0x3a]	10	1			T19	2		T316	1		T288	1
alert_ping_fail	alert[0x3b]	14	1			T319	1		T320	1		T333	2
alert_ping_fail	alert[0x3c]	13	1			T323	2		T336	1		T338	1
alert_ping_fail	alert[0x3d]	13	1			T18	1		T124	1		T314	1
alert_ping_fail	alert[0x3e]	12	1			T319	1		T338	1		T334	1
alert_ping_fail	alert[0x3f]	4	1			T18	1		T323	1		T327	1
alert_ping_fail	alert[0x40]	2	1			T334	1		T329	1		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	32602	1			T13	27		T45	4		T147	12
alert_integrity_fail	class_i[0x1]	101634	1			T45	6		T147	1		T119	2
alert_integrity_fail	class_i[0x2]	81596	1			T45	1		T147	15		T41	4
alert_integrity_fail	class_i[0x3]	39338	1			T10	8		T79	32		T231	46
alert_ping_fail	class_i[0x0]	192	1			T18	1		T19	1		T314	1
alert_ping_fail	class_i[0x1]	152	1			T17	3		T19	5		T314	3
alert_ping_fail	class_i[0x2]	164	1			T17	1		T18	7		T19	2
alert_ping_fail	class_i[0x3]	168	1			T19	2		T124	8		T314	6