Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T14,T16
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	12744	0	0
DisabledNoTrigBkwd_A	2147483647	702847	0	0
DisabledNoTrigFwd_A	2147483647	1185127808	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	12744	0	0
T1	3466	481	0	0
T6	23610	0	0	0
T7	61075	0	0	0
T11	49557	0	0	0
T14	9198	1015	0	0
T15	33239	0	0	0
T16	3072	784	0	0
T17	95576	0	0	0
T22	13725	0	0	0
T25	112013	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T34	48674	0	0	0
T40	72117	0	0	0
T43	78983	0	0	0
T47	41589	0	0	0
T73	11559	0	0	0
T74	19103	0	0	0
T75	41354	0	0	0
T77	0	335	0	0
T81	0	670	0	0
T92	0	387	0	0
T152	0	1283	0	0
T166	0	526	0	0
T237	1345	546	0	0
T238	0	460	0	0
T239	0	696	0	0
T240	0	430	0	0
T241	0	590	0	0
T242	0	848	0	0
T243	0	326	0	0
T244	0	582	0	0
T245	0	159	0	0
T246	0	602	0	0
T247	0	746	0	0
T248	0	1278	0	0
T249	40716	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	702847	0	0
T1	3466	4	0	0
T2	82059	32	0	0
T3	165840	29	0	0
T4	111700	0	0	0
T5	137172	0	0	0
T10	161132	1	0	0
T11	49557	0	0	0
T12	236948	60	0	0
T13	304868	0	0	0
T14	18396	18	0	0
T15	99717	33	0	0
T17	191152	1	0	0
T26	0	5	0	0
T31	0	33	0	0
T32	0	23	0	0
T40	0	75	0	0
T43	0	49	0	0
T48	0	2	0	0
T49	0	9	0	0
T50	0	56	0	0
T51	0	19	0	0
T52	0	6	0	0
T53	0	15	0	0
T54	0	21	0	0
T73	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1185127808	0	0
T1	13864	11250	0	0
T2	109412	77707	0	0
T3	165840	91211	0	0
T4	111700	34599	0	0
T5	137172	33628	0	0
T10	161132	154778	0	0
T12	236948	179590	0	0
T13	304868	211599	0	0
T14	18396	12952	0	0
T17	191152	145802	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T4 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T2,T10,T5
1	1	Covered	T3,T10,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T237,T77,T241
1	1	Covered	T3,T10,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	550566037	2212	0	0
DisabledNoTrigBkwd_A	550566037	163064	0	0
DisabledNoTrigFwd_A	550566037	292503874	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	2212	0	0
T22	13725	0	0	0
T25	112013	0	0	0
T34	48674	0	0	0
T40	72117	0	0	0
T47	41589	0	0	0
T73	11559	0	0	0
T74	19103	0	0	0
T75	41354	0	0	0
T77	0	335	0	0
T237	1345	546	0	0
T241	0	590	0	0
T244	0	582	0	0
T245	0	159	0	0
T249	40716	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	163064	0	0
T3	41460	12	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	1	0	0
T11	49557	0	0	0
T12	59237	60	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	29	0	0
T17	47788	1	0	0
T31	0	33	0	0
T43	0	49	0	0
T48	0	2	0	0
T50	0	2	0	0
T51	0	19	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	292503874	0	0
T1	3466	2780	0	0
T2	27353	27263	0	0
T3	41460	2036	0	0
T4	27925	2253	0	0
T5	34293	8407	0	0
T10	40283	34163	0	0
T12	59237	2098	0	0
T13	76217	3228	0	0
T14	4599	3194	0	0
T17	47788	2660	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T4 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T2,T3,T13
1	1	Covered	T2,T4,T13

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T14,T166,T240
1	1	Covered	T2,T4,T13

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T14

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	550566037	3421	0	0
DisabledNoTrigBkwd_A	550566037	186369	0	0
DisabledNoTrigFwd_A	550566037	291945697	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	3421	0	0
T6	23610	0	0	0
T7	61075	0	0	0
T11	49557	0	0	0
T14	4599	1015	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T43	78983	0	0	0
T166	0	526	0	0
T240	0	430	0	0
T242	0	848	0	0
T246	0	602	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	186369	0	0
T2	27353	31	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	18	0	0
T15	33239	4	0	0
T17	47788	0	0	0
T26	0	2	0	0
T32	0	14	0	0
T40	0	74	0	0
T49	0	9	0	0
T52	0	6	0	0
T53	0	12	0	0
T54	0	21	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	291945697	0	0
T1	3466	2804	0	0
T2	27353	5477	0	0
T3	41460	41398	0	0
T4	27925	2268	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	62556	0	0
T14	4599	3230	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T1 T2 T3 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T13
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T152,T243
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	550566037	2090	0	0
DisabledNoTrigBkwd_A	550566037	167296	0	0
DisabledNoTrigFwd_A	550566037	308858761	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	2090	0	0
T1	3466	481	0	0
T2	27353	0	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T17	47788	0	0	0
T152	0	1283	0	0
T243	0	326	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	167296	0	0
T1	3466	4	0	0
T2	27353	1	0	0
T3	41460	17	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T17	47788	0	0	0
T26	0	3	0	0
T32	0	9	0	0
T34	0	16	0	0
T40	0	1	0	0
T50	0	54	0	0
T53	0	3	0	0
T73	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	308858761	0	0
T1	3466	2817	0	0
T2	27353	24535	0	0
T3	41460	6379	0	0
T4	27925	2289	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	3252	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

27                        logic trig_gated, accu_en;
28         1/1            assign trig_gated = class_trig_i & class_en_i;
           Tests:       T1 T2 T3 
29         1/1            assign accu_en = trig_gated && !(&accu_cnt_o);
           Tests:       T2 T3 T4 
30                      
31                        // SEC_CM: ACCU.CTR.REDUN
32                        // We employ two redundant counters to guard against FI attacks.
33                        // If any of the two is glitched and the two counter states do not agree,
34                        // the check_fail_o signal is asserted which will move the corresponding escalation
35                        // FSM into a terminal error state where all escalation actions will be permanently asserted.
36                        prim_count #(
37                          .Width(AccuCntDw),
38                          // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
39                          // an alert signal, this condition is handled internally in the alert handler.
40                          .EnableAlertTriggerSVA(0)
41                        ) u_prim_count (
42                          .clk_i,
43                          .rst_ni,
44                          .clr_i,
45                          .set_i(1'b0),
46                          .set_cnt_i('0),
47                          .incr_en_i(accu_en),
48                          .decr_en_i(1'b0),
49                          .step_i(AccuCntDw'(1)),
50                          .cnt_o(accu_cnt_o),
51                          .commit_i(1'b1),
52                          .cnt_after_commit_o(),
53                          .err_o(accu_fail_o)
54                        );
55                      
56         1/1            assign accu_trig_o = (accu_cnt_o >= thresh_i) & trig_gated;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T2,T3,T13
1	1	Covered	T2,T13,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T92,T81
1	1	Covered	T2,T13,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T15,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	550566037	5021	0	0
DisabledNoTrigBkwd_A	550566037	186118	0	0
DisabledNoTrigFwd_A	550566037	291819476	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	5021	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T16	3072	784	0	0
T27	31509	0	0	0
T31	56799	0	0	0
T43	78983	0	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T81	0	670	0	0
T92	1151	387	0	0
T238	0	460	0	0
T239	0	696	0	0
T247	0	746	0	0
T248	0	1278	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	186118	0	0
T2	27353	4	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	20	0	0
T16	0	14	0	0
T17	47788	0	0	0
T32	0	28	0	0
T40	0	31	0	0
T49	0	2	0	0
T52	0	5	0	0
T53	0	4	0	0
T92	0	12	0	0
T141	0	3	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	291819476	0	0
T1	3466	2849	0	0
T2	27353	20432	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	69693	0	0
T14	4599	3276	0	0
T17	47788	47714	0	0