Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T3 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T3 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T3 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T15 T11 
159        1/1                    state_d = TimeoutSt;
           Tests:       T13 T15 T11 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T13 T15 T11 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T13 T15 T11 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T26 T27 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T26 T27 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T26 T27 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T26 T27 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T13 T15 T11 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T15 T11 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T13 T15 T11 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T15 T11 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T30 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T30 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T29 T30 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T31 T32 T33 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T32 T33 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T32 T33 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T35 T36 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T34 T37 T38 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T37 T38 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T37 T38 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T3 T17 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T39
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T10
1	0	1	Covered	T1,T2,T14
1	1	0	Covered	T2,T3,T13
1	1	1	Covered	T13,T15,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T11
0	1	Covered	T13,T26,T27
1	0	Covered	T40,T41,T42

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T13,T15,T11
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T40,T41,T42

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T11
1	0	Not Covered
1	1	Covered	T13,T26,T27

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T10
1	Covered	T1,T12,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T13,T26

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T12
1	Covered	T2,T10,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T17,T43

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T13,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T3,T12

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T13,T15,T11

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T13,T15,T11
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T44,T28,T29
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T31,T32,T44
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T34,T44,T45
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T34,T37,T38
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T3,T17
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T13,T15,T11
TimeoutSt->Phase0St	172	Covered	T13,T26,T27

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T26,T27
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T11
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T29,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T10
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T32,T33
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T10
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T35,T36
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T10
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T37,T38
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T10
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	800	0	0
CheckAccumTrig0_A	2147483647	2252	0	0
CheckAccumTrig1_A	2147483647	109	0	0
CheckClr_A	2147483647	1108	0	0
CheckEn_A	2147483647	925967345	0	0
CheckPhase0_A	2147483647	2521	0	0
CheckPhase1_A	2147483647	2456	0	0
CheckPhase2_A	2147483647	2393	0	0
CheckPhase3_A	2147483647	2332	0	0
CheckTimeout0_A	2147483647	2178	0	0
CheckTimeoutSt1_A	2147483647	273264	0	0
CheckTimeoutSt2_A	2147483647	1848	0	0
CheckTimeoutStTrig_A	2147483647	208	0	0
ErrorStAllEscAsserted_A	2147483647	4533	0	0
ErrorStIsTerminal_A	2147483647	3693	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	800	0	0
T5	137172	220	0	0
T6	94440	86	0	0
T7	244300	0	0	0
T9	0	124	0	0
T11	198228	0	0	0
T14	18396	0	0	0
T15	132956	0	0	0
T16	12288	0	0	0
T17	191152	0	0	0
T26	139124	0	0	0
T27	126036	0	0	0
T46	0	105	0	0
T47	0	265	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2252	0	0
T1	3466	1	0	0
T2	82059	2	0	0
T3	165840	7	0	0
T4	111700	0	0	0
T5	137172	0	0	0
T10	161132	1	0	0
T11	49557	0	0	0
T12	236948	1	0	0
T13	304868	0	0	0
T14	18396	1	0	0
T15	99717	2	0	0
T17	191152	1	0	0
T26	0	2	0	0
T31	0	2	0	0
T32	0	4	0	0
T40	0	1	0	0
T43	0	3	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	1	0	0
T53	0	3	0	0
T54	0	1	0	0
T55	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109	0	0
T18	354763	0	0	0
T23	25226	0	0	0
T24	10839	0	0	0
T34	48674	0	0	0
T40	72117	1	0	0
T41	92008	1	0	0
T42	73577	1	0	0
T44	0	1	0	0
T47	41589	0	0	0
T53	14387	0	0	0
T54	56173	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	107968	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	11559	0	0	0
T74	19103	0	0	0
T75	41354	0	0	0
T76	36868	0	0	0
T77	2651	0	0	0
T78	27582	0	0	0
T79	42077	0	0	0
T80	19405	0	0	0
T81	4411	0	0	0
T82	48287	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1108	0	0
T2	27353	1	0	0
T3	82920	5	0	0
T4	55850	0	0	0
T5	68586	0	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T10	80566	0	0	0
T11	49557	0	0	0
T12	118474	0	0	0
T13	152434	0	0	0
T14	9198	0	0	0
T15	66478	0	0	0
T16	3072	0	0	0
T17	95576	1	0	0
T26	34781	1	0	0
T27	31509	1	0	0
T31	56799	1	0	0
T35	0	1	0	0
T41	0	4	0	0
T43	78983	2	0	0
T44	0	2	0	0
T48	8812	2	0	0
T49	17911	0	0	0
T51	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	925967345	0	0
T1	13864	11250	0	0
T2	109412	65614	0	0
T3	165840	91209	0	0
T4	111700	34594	0	0
T5	1372	988	0	0
T10	161132	122182	0	0
T12	236948	179587	0	0
T13	304868	163574	0	0
T14	18396	12952	0	0
T17	191152	145799	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2521	0	0
T1	3466	1	0	0
T2	82059	2	0	0
T3	165840	7	0	0
T4	111700	0	0	0
T5	137172	0	0	0
T10	161132	1	0	0
T11	49557	0	0	0
T12	236948	1	0	0
T13	304868	1	0	0
T14	18396	1	0	0
T15	99717	2	0	0
T17	191152	1	0	0
T26	0	3	0	0
T27	0	1	0	0
T31	0	2	0	0
T32	0	4	0	0
T40	0	2	0	0
T43	0	3	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T1	3466	1	0	0
T2	82059	2	0	0
T3	165840	7	0	0
T4	111700	0	0	0
T5	137172	0	0	0
T10	161132	1	0	0
T11	49557	0	0	0
T12	236948	1	0	0
T13	304868	1	0	0
T14	18396	1	0	0
T15	99717	2	0	0
T17	191152	1	0	0
T26	0	3	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T40	0	2	0	0
T43	0	3	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2393	0	0
T1	3466	1	0	0
T2	82059	2	0	0
T3	165840	7	0	0
T4	111700	0	0	0
T5	137172	0	0	0
T10	161132	1	0	0
T11	49557	0	0	0
T12	236948	1	0	0
T13	304868	1	0	0
T14	18396	1	0	0
T15	99717	2	0	0
T17	191152	1	0	0
T26	0	3	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T40	0	2	0	0
T43	0	3	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2332	0	0
T1	3466	1	0	0
T2	82059	2	0	0
T3	165840	7	0	0
T4	111700	0	0	0
T5	137172	0	0	0
T10	161132	1	0	0
T11	49557	0	0	0
T12	236948	1	0	0
T13	304868	1	0	0
T14	18396	1	0	0
T15	99717	2	0	0
T17	191152	1	0	0
T26	0	3	0	0
T27	0	1	0	0
T31	0	1	0	0
T32	0	3	0	0
T40	0	2	0	0
T43	0	3	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	1	0	0
T88	0	1	0	0
T89	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2178	0	0
T5	68586	0	0	0
T6	47220	0	0	0
T7	122150	0	0	0
T8	94130	0	0	0
T9	48050	0	0	0
T11	99114	6	0	0
T13	152434	8	0	0
T14	9198	0	0	0
T15	66478	1	0	0
T16	6144	0	0	0
T17	95576	0	0	0
T26	69562	1	0	0
T27	126036	7	0	0
T31	113598	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	157966	0	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	17624	1	0	0
T49	35822	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T76	0	4	0	0
T79	0	12	0	0
T88	29382	4	0	0
T89	0	3	0	0
T90	0	2	0	0
T91	0	2	0	0
T92	2302	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	273264	0	0
T5	68586	0	0	0
T6	47220	0	0	0
T7	122150	0	0	0
T8	94130	0	0	0
T9	48050	0	0	0
T11	99114	907	0	0
T13	152434	1513	0	0
T14	9198	0	0	0
T15	66478	42	0	0
T16	6144	0	0	0
T17	95576	0	0	0
T26	69562	317	0	0
T27	126036	1338	0	0
T31	113598	0	0	0
T34	0	179	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	157966	0	0	0
T44	0	44	0	0
T45	0	257	0	0
T48	17624	51	0	0
T49	35822	0	0	0
T52	0	20	0	0
T53	0	115	0	0
T54	0	548	0	0
T55	0	119	0	0
T76	0	455	0	0
T79	0	1365	0	0
T88	29382	287	0	0
T89	0	389	0	0
T90	0	221	0	0
T91	0	390	0	0
T92	2302	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1848	0	0
T5	34293	0	0	0
T6	47220	0	0	0
T7	122150	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T11	99114	6	0	0
T13	76217	7	0	0
T14	4599	0	0	0
T15	66478	1	0	0
T16	6144	0	0	0
T17	47788	0	0	0
T21	20548	0	0	0
T26	69562	0	0	0
T27	94527	6	0	0
T31	113598	0	0	0
T33	0	4	0	0
T34	0	1	0	0
T42	0	2	0	0
T43	157966	0	0	0
T44	0	2	0	0
T48	17624	1	0	0
T49	17911	0	0	0
T50	138148	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T76	0	3	0	0
T79	0	12	0	0
T88	29382	3	0	0
T89	0	1	0	0
T90	0	2	0	0
T91	0	5	0	0
T92	1151	0	0	0
T93	0	2	0	0
T94	0	26	0	0
T95	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	208	0	0
T5	34293	0	0	0
T6	23610	0	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T11	49557	0	0	0
T13	76217	1	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T21	20548	0	0	0
T26	34781	1	0	0
T27	63018	1	0	0
T30	0	2	0	0
T31	56799	0	0	0
T33	0	4	0	0
T36	0	2	0	0
T43	78983	0	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T50	138148	0	0	0
T54	0	2	0	0
T76	0	1	0	0
T83	0	1	0	0
T88	29382	1	0	0
T89	0	2	0	0
T92	1151	0	0	0
T95	0	2	0	0
T96	0	1	0	0
T97	0	3	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	4	0	0
T103	0	1	0	0
T104	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4533	0	0
T5	137172	1325	0	0
T6	94440	609	0	0
T7	244300	0	0	0
T9	0	663	0	0
T11	198228	0	0	0
T14	18396	0	0	0
T15	132956	0	0	0
T16	12288	0	0	0
T17	191152	0	0	0
T26	139124	0	0	0
T27	126036	0	0	0
T46	0	636	0	0
T47	0	1300	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3693	0	0
T5	137172	1085	0	0
T6	94440	489	0	0
T7	244300	0	0	0
T9	0	543	0	0
T11	198228	0	0	0
T14	18396	0	0	0
T15	132956	0	0	0
T16	12288	0	0	0
T17	191152	0	0	0
T26	139124	0	0	0
T27	126036	0	0	0
T46	0	516	0	0
T47	0	1060	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13864	13500	0	0
T2	109412	109052	0	0
T3	165840	165592	0	0
T4	111700	111156	0	0
T5	380	0	0	0
T10	161132	160820	0	0
T12	236948	236656	0	0
T13	304868	304488	0	0
T14	18396	18096	0	0
T15	0	132568	0	0
T17	191152	190856	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	13864	13500	0	0
T2	109412	109052	0	0
T3	165840	165592	0	0
T4	111700	111156	0	0
T5	137172	33628	0	0
T10	161132	160820	0	0
T12	236948	236656	0	0
T13	304868	304488	0	0
T14	18396	18096	0	0
T17	191152	190856	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T4 T14 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T4 T14 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T4 T14 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T15 T26 
159        1/1                    state_d = TimeoutSt;
           Tests:       T13 T15 T26 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T13 T15 T26 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T13 T15 T26 
172        1/1                    state_d    = Phase0St;
           Tests:       T13 T26 T89 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T13 T26 T89 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T13 T26 T89 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T13 T26 T89 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T13 T15 T26 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T15 T26 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T15 T27 T88 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T15 T27 T88 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T14 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T13 T14 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T13 T14 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T13 T14 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T13 T14 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T13 T14 
194        1/1                    state_d = IdleSt;
           Tests:       T62 T105 T106 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T62 T105 T106 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T62 T105 T106 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T14 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T13 T14 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T14 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T13 T14 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T14 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T13 T14 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T13 T14 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T13 T14 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T13 T14 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T13 T14 
211        1/1                    state_d = IdleSt;
           Tests:       T107 T108 T109 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T107 T108 T109 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T107 T108 T109 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T14 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T13 T14 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T14 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T13 T14 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T14 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T13 T14 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T13 T14 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T13 T14 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T13 T14 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T13 T14 
229        1/1                    state_d = IdleSt;
           Tests:       T110 T69 T111 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T110 T69 T111 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T110 T69 T111 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T14 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T13 T14 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T14 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T13 T14 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T13 T14 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T13 T14 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T13 T14 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T13 T14 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T13 T14 
245        1/1                    state_d = IdleSt;
           Tests:       T58 T68 T111 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T58 T68 T111 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T58 T68 T111 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T13 T14 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T13 T14 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T13 T14 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T13 T14 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T13 T14 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T13 T14 
260        1/1                  if (clr_i) begin
           Tests:       T2 T13 T14 
261        1/1                    state_d = IdleSt;
           Tests:       T26 T54 T55 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T4,T13
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T4,T13

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T4,T14

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T13,T15
1	0	1	Covered	T2,T14,T15
1	1	0	Covered	T2,T13,T11
1	1	1	Covered	T13,T15,T26

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T15,T26
0	1	Covered	T13,T26,T89
1	0	Covered	T40,T60,T64

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T15,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T40,T60,T64

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T15,T26
1	0	Not Covered
1	1	Covered	T13,T26,T89

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T15
1	Covered	T14,T89,T40

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T14,T15
1	Covered	T13,T26,T49

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T13,T14,T26
1	Covered	T2,T15,T26

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T14
1	Covered	T32,T55,T84

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T14,T15,T49

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T14,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T13,T14,T49

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T13,T14,T26

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T13,T14
Phase1St	198	Covered	T2,T13,T14
Phase2St	215	Covered	T2,T13,T14
Phase3St	233	Covered	T2,T13,T14
TerminalSt	249	Covered	T2,T13,T14
TimeoutSt	159	Covered	T13,T15,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T2,T14,T15
IdleSt->TimeoutSt	159	Covered	T13,T15,T26
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T62,T105,T112
Phase0St->Phase1St	198	Covered	T2,T13,T14
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T44,T107,T108
Phase1St->Phase2St	215	Covered	T2,T13,T14
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T110,T69,T111
Phase2St->Phase3St	233	Covered	T2,T13,T14
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T58,T68,T111
Phase3St->TerminalSt	249	Covered	T2,T13,T14
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T26,T54,T55
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T15,T27,T88
TimeoutSt->Phase0St	172	Covered	T13,T26,T89

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T4,T14
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T13,T26,T89
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T15,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T15,T27,T88
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T62,T105,T106
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T13,T14
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T13,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T107,T108,T109
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T13,T14
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T13,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T110,T69,T111
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T13,T14
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T13,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T58,T68,T111
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T13,T14
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T13,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T26,T54,T55
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T13,T14
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	550566037	148	0	0
CheckAccumTrig0_A	550566037	475	0	0
CheckAccumTrig1_A	550566037	24	0	0
CheckClr_A	550566037	223	0	0
CheckEn_A	550428711	228126846	0	0
CheckPhase0_A	550566037	547	0	0
CheckPhase1_A	550566037	537	0	0
CheckPhase2_A	550566037	528	0	0
CheckPhase3_A	550566037	514	0	0
CheckTimeout0_A	550566037	452	0	0
CheckTimeoutSt1_A	550566037	63875	0	0
CheckTimeoutSt2_A	550566037	369	0	0
CheckTimeoutStTrig_A	550566037	54	0	0
ErrorStAllEscAsserted_A	550566037	1104	0	0
ErrorStIsTerminal_A	550566037	894	0	0
EscStateOut_A	550427392	550357694	0	0
u_state_regs_A	550566037	550407217	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	148	0	0
T5	34293	35	0	0
T6	23610	12	0	0
T7	61075	0	0	0
T9	0	30	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	17	0	0
T47	0	54	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	475	0	0
T2	27353	1	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	1	0	0
T15	33239	1	0	0
T17	47788	0	0	0
T26	0	1	0	0
T32	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	24	0	0
T34	48674	0	0	0
T40	72117	1	0	0
T41	46004	0	0	0
T47	41589	0	0	0
T60	0	1	0	0
T64	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	11559	0	0	0
T74	19103	0	0	0
T75	41354	0	0	0
T76	36868	0	0	0
T77	2651	0	0	0
T78	27582	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	223	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T16	3072	0	0	0
T26	34781	1	0	0
T27	31509	0	0	0
T31	56799	0	0	0
T35	0	1	0	0
T43	78983	0	0	0
T44	0	2	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550428711	228126846	0	0
T1	3466	2804	0	0
T2	27353	5477	0	0
T3	41460	41397	0	0
T4	27925	2267	0	0
T5	343	247	0	0
T10	40283	40204	0	0
T12	59237	59163	0	0
T13	76217	14533	0	0
T14	4599	3230	0	0
T17	47788	47713	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	547	0	0
T2	27353	1	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	1	0	0
T14	4599	1	0	0
T15	33239	1	0	0
T17	47788	0	0	0
T26	0	2	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T89	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	537	0	0
T2	27353	1	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	1	0	0
T14	4599	1	0	0
T15	33239	1	0	0
T17	47788	0	0	0
T26	0	2	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T89	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	528	0	0
T2	27353	1	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	1	0	0
T14	4599	1	0	0
T15	33239	1	0	0
T17	47788	0	0	0
T26	0	2	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T89	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	514	0	0
T2	27353	1	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	1	0	0
T14	4599	1	0	0
T15	33239	1	0	0
T17	47788	0	0	0
T26	0	2	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T89	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	452	0	0
T5	34293	0	0	0
T6	23610	0	0	0
T11	49557	0	0	0
T13	76217	1	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	1	0	0
T27	31509	1	0	0
T40	0	1	0	0
T54	0	1	0	0
T76	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	63875	0	0
T5	34293	0	0	0
T6	23610	0	0	0
T11	49557	0	0	0
T13	76217	164	0	0
T14	4599	0	0	0
T15	33239	42	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	317	0	0
T27	31509	219	0	0
T40	0	1	0	0
T54	0	548	0	0
T76	0	159	0	0
T88	0	53	0	0
T89	0	111	0	0
T90	0	221	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	369	0	0
T6	23610	0	0	0
T7	61075	0	0	0
T11	49557	0	0	0
T15	33239	1	0	0
T16	3072	0	0	0
T26	34781	0	0	0
T27	31509	1	0	0
T31	56799	0	0	0
T33	0	1	0	0
T43	78983	0	0	0
T48	8812	0	0	0
T76	0	1	0	0
T88	0	1	0	0
T90	0	2	0	0
T91	0	3	0	0
T93	0	1	0	0
T94	0	26	0	0
T95	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	54	0	0
T5	34293	0	0	0
T6	23610	0	0	0
T11	49557	0	0	0
T13	76217	1	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	1	0	0
T27	31509	0	0	0
T33	0	1	0	0
T54	0	1	0	0
T83	0	1	0	0
T89	0	1	0	0
T95	0	1	0	0
T101	0	1	0	0
T102	0	1	0	0
T104	0	4	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	1104	0	0
T5	34293	306	0	0
T6	23610	147	0	0
T7	61075	0	0	0
T9	0	166	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	146	0	0
T47	0	339	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	894	0	0
T5	34293	246	0	0
T6	23610	117	0	0
T7	61075	0	0	0
T9	0	136	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	116	0	0
T47	0	279	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550427392	550357694	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	95	0	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T15	0	33142	0	0
T17	47788	47714	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	550407217	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T3 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T3 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T3 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T27 T88 T52 
159        1/1                    state_d = TimeoutSt;
           Tests:       T27 T88 T52 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T27 T88 T52 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T27 T88 T52 
172        1/1                    state_d    = Phase0St;
           Tests:       T88 T89 T95 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T88 T89 T95 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T88 T89 T95 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T88 T89 T95 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T27 T88 T52 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T27 T88 T52 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T27 T52 T53 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T52 T53 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T29 T30 T113 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T113 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T29 T30 T113 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T32 T114 T115 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T114 T115 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T32 T114 T115 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T34 T116 T117 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T116 T117 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T116 T117 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T34 T38 T116 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T38 T116 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T38 T116 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T3 T32 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T26
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T3,T27
1	0	1	Covered	T1,T2,T26
1	1	0	Covered	T2,T13,T15
1	1	1	Covered	T27,T88,T52

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T88,T52
0	1	Covered	T88,T89,T95
1	0	Covered	T118,T65,T119

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T27,T88,T52
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T118,T65,T119

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T88,T52
1	0	Not Covered
1	1	Covered	T88,T89,T95

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T88
1	Covered	T1,T26,T73

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T26
1	Covered	T3,T32,T53

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T26
1	Covered	T2,T50,T89

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T40,T44

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T88

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T26,T50

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T1,T3,T88

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T27,T88,T52

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T27,T88,T52
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T30,T113
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T32,T57,T114
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T34,T116,T117
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T34,T38,T116
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T3,T32
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T27,T52,T53
TimeoutSt->Phase0St	172	Covered	T88,T89,T95

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T88,T52
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T88,T89,T95
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T27,T88,T52
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T27,T52,T53
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T113
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T26
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T114,T115
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T26
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T34,T116,T117
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T34,T38,T116
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T26
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	550566037	245	0	0
CheckAccumTrig0_A	550566037	537	0	0
CheckAccumTrig1_A	550566037	16	0	0
CheckClr_A	550566037	274	0	0
CheckEn_A	550428711	220034436	0	0
CheckPhase0_A	550566037	588	0	0
CheckPhase1_A	550566037	569	0	0
CheckPhase2_A	550566037	551	0	0
CheckPhase3_A	550566037	533	0	0
CheckTimeout0_A	550566037	468	0	0
CheckTimeoutSt1_A	550566037	56246	0	0
CheckTimeoutSt2_A	550566037	406	0	0
CheckTimeoutStTrig_A	550566037	45	0	0
ErrorStAllEscAsserted_A	550566037	1082	0	0
ErrorStIsTerminal_A	550566037	872	0	0
EscStateOut_A	550427392	550357694	0	0
u_state_regs_A	550566037	550407217	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	245	0	0
T5	34293	48	0	0
T6	23610	27	0	0
T7	61075	0	0	0
T9	0	35	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	33	0	0
T47	0	102	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	537	0	0
T1	3466	1	0	0
T2	27353	1	0	0
T3	41460	5	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T17	47788	0	0	0
T26	0	1	0	0
T32	0	3	0	0
T34	0	5	0	0
T40	0	1	0	0
T50	0	1	0	0
T53	0	2	0	0
T73	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	16	0	0
T65	107968	1	0	0
T82	48287	0	0	0
T106	0	1	0	0
T119	0	2	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	300704	0	0	0
T128	323993	0	0	0
T129	132427	0	0	0
T130	51714	0	0	0
T131	387166	0	0	0
T132	9902	0	0	0
T133	22935	0	0	0
T134	279519	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	274	0	0
T2	27353	1	0	0
T3	41460	4	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T17	47788	0	0	0
T28	0	1	0	0
T32	0	2	0	0
T33	0	1	0	0
T34	0	4	0	0
T53	0	2	0	0
T94	0	3	0	0
T97	0	1	0	0
T135	0	3	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550428711	220034436	0	0
T1	3466	2817	0	0
T2	27353	24534	0	0
T3	41460	6379	0	0
T4	27925	2288	0	0
T5	343	247	0	0
T10	40283	40204	0	0
T12	59237	59163	0	0
T13	76217	76121	0	0
T14	4599	3252	0	0
T17	47788	47713	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	588	0	0
T1	3466	1	0	0
T2	27353	1	0	0
T3	41460	5	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T17	47788	0	0	0
T26	0	1	0	0
T32	0	3	0	0
T40	0	1	0	0
T50	0	1	0	0
T73	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	569	0	0
T1	3466	1	0	0
T2	27353	1	0	0
T3	41460	5	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T17	47788	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T40	0	1	0	0
T50	0	1	0	0
T73	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	551	0	0
T1	3466	1	0	0
T2	27353	1	0	0
T3	41460	5	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T17	47788	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T40	0	1	0	0
T50	0	1	0	0
T73	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	533	0	0
T1	3466	1	0	0
T2	27353	1	0	0
T3	41460	5	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T17	47788	0	0	0
T26	0	1	0	0
T32	0	2	0	0
T40	0	1	0	0
T50	0	1	0	0
T73	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	468	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T27	31509	3	0	0
T28	0	3	0	0
T31	56799	0	0	0
T43	78983	0	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T88	14691	1	0	0
T89	0	1	0	0
T91	0	2	0	0
T92	1151	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	56246	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T27	31509	612	0	0
T28	0	339	0	0
T31	56799	0	0	0
T43	78983	0	0	0
T44	0	44	0	0
T45	0	257	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T52	0	20	0	0
T53	0	115	0	0
T55	0	119	0	0
T88	14691	101	0	0
T89	0	138	0	0
T91	0	390	0	0
T92	1151	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	406	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T27	31509	3	0	0
T28	0	3	0	0
T31	56799	0	0	0
T33	0	3	0	0
T43	78983	0	0	0
T44	0	2	0	0
T45	0	1	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T88	14691	0	0	0
T91	0	2	0	0
T92	1151	0	0	0
T93	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	45	0	0
T21	20548	0	0	0
T30	0	1	0	0
T32	76307	0	0	0
T36	0	1	0	0
T46	15523	0	0	0
T50	138148	0	0	0
T51	23067	0	0	0
T52	35807	0	0	0
T88	14691	1	0	0
T89	48333	1	0	0
T95	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T136	0	1	0	0
T137	9306	0	0	0
T138	3860	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	1082	0	0
T5	34293	290	0	0
T6	23610	132	0	0
T7	61075	0	0	0
T9	0	164	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	163	0	0
T47	0	333	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	872	0	0
T5	34293	230	0	0
T6	23610	102	0	0
T7	61075	0	0	0
T9	0	134	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	133	0	0
T47	0	273	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550427392	550357694	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	95	0	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T15	0	33142	0	0
T17	47788	47714	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	550407217	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T15 T16 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T15 T16 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T15 T16 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T27 T88 T32 
159        1/1                    state_d = TimeoutSt;
           Tests:       T27 T88 T32 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T27 T88 T32 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T27 T88 T32 
172        1/1                    state_d    = Phase0St;
           Tests:       T27 T79 T44 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T27 T79 T44 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T27 T79 T44 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T27 T79 T44 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T27 T88 T32 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T27 T88 T32 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T88 T32 T89 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T88 T32 T89 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T15 T16 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T15 T16 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T15 T16 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T15 T16 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T15 T16 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T15 T16 
194        1/1                    state_d = IdleSt;
           Tests:       T139 T60 T140 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T139 T60 T140 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T139 T60 T140 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T15 T16 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T15 T16 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T16 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T15 T16 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T15 T16 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T15 T16 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T15 T16 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T15 T16 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T15 T16 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T15 T16 
211        1/1                    state_d = IdleSt;
           Tests:       T141 T36 T142 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T141 T36 T142 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T141 T36 T142 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T15 T16 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T15 T16 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T16 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T15 T16 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T15 T16 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T15 T16 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T15 T16 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T15 T16 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T15 T16 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T15 T16 
229        1/1                    state_d = IdleSt;
           Tests:       T143 T144 T117 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T143 T144 T117 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T143 T144 T117 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T15 T16 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T15 T16 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T16 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T15 T16 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T15 T16 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T15 T16 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T15 T16 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T15 T16 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T15 T16 
245        1/1                    state_d = IdleSt;
           Tests:       T110 T111 T71 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T110 T111 T71 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T110 T111 T71 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T15 T16 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T15 T16 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T16 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T15 T16 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T15 T16 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T15 T16 
260        1/1                  if (clr_i) begin
           Tests:       T2 T15 T16 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T52 T79 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T15,T16
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T15,T16

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T16

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T2,T13,T27
1	0	1	Covered	T2,T16,T92
1	1	0	Covered	T2,T3,T13
1	1	1	Covered	T27,T88,T32

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T27,T88,T32
0	1	Covered	T27,T79,T44
1	0	Covered	T83,T30,T140

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T27,T88,T32
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T83,T30,T140

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T88,T32
1	0	Not Covered
1	1	Covered	T27,T79,T44

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T27
1	Covered	T2,T16,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T16,T49
1	Covered	T15,T27,T40

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T44,T83,T91

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T16
1	Covered	T2,T52,T32

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T16,T49

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T15,T16,T27

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T2,T15,T16

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T15,T16,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T15,T16
Phase1St	198	Covered	T2,T15,T16
Phase2St	215	Covered	T2,T15,T16
Phase3St	233	Covered	T2,T15,T16
TerminalSt	249	Covered	T2,T15,T16
TimeoutSt	159	Covered	T27,T88,T32

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T2,T15,T16
IdleSt->TimeoutSt	159	Covered	T27,T88,T32
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T30,T139,T60
Phase0St->Phase1St	198	Covered	T2,T15,T16
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T141,T36,T142
Phase1St->Phase2St	215	Covered	T2,T15,T16
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T143,T144,T117
Phase2St->Phase3St	233	Covered	T2,T15,T16
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T110,T111,T71
Phase3St->TerminalSt	249	Covered	T2,T15,T16
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T52,T79
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T88,T32,T89
TimeoutSt->Phase0St	172	Covered	T27,T79,T44

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T27,T88,T32
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T27,T79,T44
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T27,T88,T32
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T88,T32,T89
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T139,T60,T140
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T15,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T15,T27
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T141,T36,T142
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T15,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T15,T27
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T143,T144,T117
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T15,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T15,T27
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T110,T111,T71
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T15,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T15,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T52,T79
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T15,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	550566037	220	0	0
CheckAccumTrig0_A	550566037	478	0	0
CheckAccumTrig1_A	550566037	28	0	0
CheckClr_A	550566037	231	0	0
CheckEn_A	550428711	238906740	0	0
CheckPhase0_A	550566037	531	0	0
CheckPhase1_A	550566037	524	0	0
CheckPhase2_A	550566037	517	0	0
CheckPhase3_A	550566037	503	0	0
CheckTimeout0_A	550566037	744	0	0
CheckTimeoutSt1_A	550566037	89531	0	0
CheckTimeoutSt2_A	550566037	670	0	0
CheckTimeoutStTrig_A	550566037	42	0	0
ErrorStAllEscAsserted_A	550566037	1194	0	0
ErrorStIsTerminal_A	550566037	984	0	0
EscStateOut_A	550427392	550357694	0	0
u_state_regs_A	550566037	550407217	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	220	0	0
T5	34293	84	0	0
T6	23610	27	0	0
T7	61075	0	0	0
T9	0	34	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	27	0	0
T47	0	48	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	478	0	0
T2	27353	2	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T16	0	1	0	0
T17	47788	0	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T92	0	1	0	0
T141	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	28	0	0
T28	66170	0	0	0
T30	0	1	0	0
T33	9348	0	0	0
T71	0	4	0	0
T83	28277	1	0	0
T84	18419	0	0	0
T91	42502	0	0	0
T93	55696	0	0	0
T106	0	2	0	0
T140	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	49221	0	0	0
T151	64441	0	0	0
T152	4872	0	0	0
T153	5776	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	231	0	0
T2	27353	1	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T17	47788	0	0	0
T29	0	1	0	0
T35	0	1	0	0
T44	0	1	0	0
T52	0	2	0	0
T79	0	1	0	0
T83	0	1	0	0
T94	0	1	0	0
T141	0	1	0	0
T154	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550428711	238906740	0	0
T1	3466	2849	0	0
T2	27353	8341	0	0
T3	41460	41397	0	0
T4	27925	27787	0	0
T5	343	247	0	0
T10	40283	40204	0	0
T12	59237	59163	0	0
T13	76217	69692	0	0
T14	4599	3276	0	0
T17	47788	47713	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	531	0	0
T2	27353	2	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T16	0	1	0	0
T17	47788	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T92	0	1	0	0
T141	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	524	0	0
T2	27353	2	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T16	0	1	0	0
T17	47788	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T92	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	517	0	0
T2	27353	2	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T16	0	1	0	0
T17	47788	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T92	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	503	0	0
T2	27353	2	0	0
T3	41460	0	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T16	0	1	0	0
T17	47788	0	0	0
T27	0	1	0	0
T32	0	1	0	0
T40	0	1	0	0
T49	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T92	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	744	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T27	31509	1	0	0
T31	56799	0	0	0
T32	0	1	0	0
T43	78983	0	0	0
T44	0	1	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T76	0	8	0	0
T79	0	1	0	0
T83	0	3	0	0
T88	14691	1	0	0
T89	0	3	0	0
T90	0	9	0	0
T91	0	2	0	0
T92	1151	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	89531	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T27	31509	72	0	0
T31	56799	0	0	0
T32	0	76	0	0
T43	78983	0	0	0
T44	0	24	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T76	0	911	0	0
T79	0	50	0	0
T83	0	181	0	0
T88	14691	53	0	0
T89	0	409	0	0
T90	0	1226	0	0
T91	0	264	0	0
T92	1151	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	670	0	0
T21	20548	0	0	0
T32	76307	1	0	0
T46	15523	0	0	0
T50	138148	0	0	0
T51	23067	0	0	0
T52	35807	0	0	0
T76	0	8	0	0
T83	0	1	0	0
T88	14691	1	0	0
T89	48333	3	0	0
T90	0	9	0	0
T91	0	1	0	0
T93	0	4	0	0
T95	0	9	0	0
T97	0	25	0	0
T137	9306	0	0	0
T138	3860	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	42	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T27	31509	1	0	0
T31	56799	0	0	0
T43	78983	0	0	0
T44	0	1	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T58	0	1	0	0
T60	0	1	0	0
T79	0	1	0	0
T83	0	1	0	0
T88	14691	0	0	0
T91	0	1	0	0
T92	1151	0	0	0
T94	0	1	0	0
T101	0	1	0	0
T155	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	1194	0	0
T5	34293	378	0	0
T6	23610	161	0	0
T7	61075	0	0	0
T9	0	191	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	175	0	0
T47	0	289	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	984	0	0
T5	34293	318	0	0
T6	23610	131	0	0
T7	61075	0	0	0
T9	0	161	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	145	0	0
T47	0	229	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550427392	550357694	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	95	0	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T15	0	33142	0	0
T17	47788	47714	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	550407217	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T3 T10 T12 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T3 T10 T12 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T3 T10 T12 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T11 T27 
159        1/1                    state_d = TimeoutSt;
           Tests:       T13 T11 T27 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T13 T11 T27 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T13 T11 T27 
172        1/1                    state_d    = Phase0St;
           Tests:       T27 T76 T41 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T27 T76 T41 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T27 T76 T41 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T27 T76 T41 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T13 T11 T27 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T13 T11 T27 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T13 T11 T27 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T11 T27 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T3 T10 T12 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T3 T10 T12 
190        1/1                  esc_state_o = Phase0;
           Tests:       T3 T10 T12 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T3 T10 T12 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
194        1/1                    state_d = IdleSt;
           Tests:       T28 T30 T107 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T30 T107 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T28 T30 T107 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
198        1/1                    state_d = Phase1St;
           Tests:       T3 T10 T12 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T3 T10 T12 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T3 T10 T12 
207        1/1                  esc_state_o = Phase1;
           Tests:       T3 T10 T12 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T3 T10 T12 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
211        1/1                    state_d = IdleSt;
           Tests:       T31 T33 T29 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T31 T33 T29 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T31 T33 T29 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
215        1/1                    state_d = Phase2St;
           Tests:       T3 T10 T12 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T3 T10 T12 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T3 T10 T12 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T3 T10 T12 
224        1/1                  esc_state_o = Phase2;
           Tests:       T3 T10 T12 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T3 T10 T12 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
229        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T156 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T156 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T36 T156 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
233        1/1                    state_d = Phase3St;
           Tests:       T3 T10 T12 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T3 T10 T12 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T3 T10 T12 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T3 T10 T12 
241        1/1                  esc_state_o = Phase3;
           Tests:       T3 T10 T12 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T3 T10 T12 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
245        1/1                    state_d = IdleSt;
           Tests:       T37 T157 T134 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T157 T134 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T157 T134 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T3 T10 T12 
249        1/1                    state_d = TerminalSt;
           Tests:       T3 T10 T12 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T3 T10 T12 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T3 T10 T12 
259        1/1                  esc_state_o = Terminal;
           Tests:       T3 T10 T12 
260        1/1                  if (clr_i) begin
           Tests:       T3 T10 T12 
261        1/1                    state_d = IdleSt;
           Tests:       T3 T17 T27 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T5 T6 T9 
269        1/1                  fsm_error = 1'b1;
           Tests:       T5 T6 T9 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T5 T6 T9 
285        1/1                fsm_error = 1'b1;
           Tests:       T5 T6 T9 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T9
1	0	Covered	T3,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T39
1	1	1	Covered	T3,T10,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T13
1	0	1	Covered	T138,T141,T158
1	1	0	Covered	T2,T11,T27
1	1	1	Covered	T13,T11,T27

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T11,T27
0	1	Covered	T27,T76,T54
1	0	Covered	T41,T42,T44

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T11,T27
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T41,T42,T44

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T11,T27
1	0	Not Covered
1	1	Covered	T27,T76,T54

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T17
1	Covered	T12,T15,T43

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T10,T12
1	Covered	T27,T48,T141

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T12,T17
1	Covered	T10,T48,T138

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T10,T12,T15
1	Covered	T3,T17,T43

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T5,T6,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T3,T10,T15

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T12,T43,T48

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T17,T27,T43

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T6,T9
1	0	Covered	T3,T12,T17

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T5,T6,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T10,T12
Phase1St	198	Covered	T3,T10,T12
Phase2St	215	Covered	T3,T10,T12
Phase3St	233	Covered	T3,T10,T12
TerminalSt	249	Covered	T3,T10,T12
TimeoutSt	159	Covered	T13,T11,T27

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T5,T6,T9
IdleSt->Phase0St	152	Covered	T3,T10,T12
IdleSt->TimeoutSt	159	Covered	T13,T11,T27
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T44,T28,T30
Phase0St->Phase1St	198	Covered	T3,T10,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T33,T29
Phase1St->Phase2St	215	Covered	T3,T10,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T44,T45,T35
Phase2St->Phase3St	233	Covered	T3,T10,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T37,T157,T134
Phase3St->TerminalSt	249	Covered	T3,T10,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T17,T27
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T11,T27
TimeoutSt->Phase0St	172	Covered	T27,T76,T41

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T11,T27
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T27,T76,T41
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T11,T27
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T11,T27
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T30,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T33,T29
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T10,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T36,T156
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T10,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T37,T157,T134
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T10,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T10,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T17,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T5,T6,T9

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T9
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	550566037	187	0	0
CheckAccumTrig0_A	550566037	762	0	0
CheckAccumTrig1_A	550566037	41	0	0
CheckClr_A	550566037	380	0	0
CheckEn_A	550428711	238899323	0	0
CheckPhase0_A	550566037	855	0	0
CheckPhase1_A	550566037	826	0	0
CheckPhase2_A	550566037	797	0	0
CheckPhase3_A	550566037	782	0	0
CheckTimeout0_A	550566037	514	0	0
CheckTimeoutSt1_A	550566037	63612	0	0
CheckTimeoutSt2_A	550566037	403	0	0
CheckTimeoutStTrig_A	550566037	67	0	0
ErrorStAllEscAsserted_A	550566037	1153	0	0
ErrorStIsTerminal_A	550566037	943	0	0
EscStateOut_A	550427392	550357694	0	0
u_state_regs_A	550566037	550407217	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	187	0	0
T5	34293	53	0	0
T6	23610	20	0	0
T7	61075	0	0	0
T9	0	25	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	28	0	0
T47	0	61	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	762	0	0
T3	41460	2	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	1	0	0
T11	49557	0	0	0
T12	59237	1	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T17	47788	1	0	0
T31	0	2	0	0
T43	0	3	0	0
T48	0	2	0	0
T50	0	1	0	0
T51	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	41	0	0
T18	354763	0	0	0
T23	25226	0	0	0
T24	10839	0	0	0
T41	46004	1	0	0
T42	73577	1	0	0
T44	0	1	0	0
T53	14387	0	0	0
T54	56173	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T79	42077	0	0	0
T80	19405	0	0	0
T81	4411	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	380	0	0
T3	41460	1	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	0	0	0
T11	49557	0	0	0
T12	59237	0	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T17	47788	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T41	0	4	0	0
T43	0	2	0	0
T48	0	2	0	0
T51	0	1	0	0
T74	0	1	0	0
T76	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550428711	238899323	0	0
T1	3466	2780	0	0
T2	27353	27262	0	0
T3	41460	2036	0	0
T4	27925	2252	0	0
T5	343	247	0	0
T10	40283	1570	0	0
T12	59237	2098	0	0
T13	76217	3228	0	0
T14	4599	3194	0	0
T17	47788	2660	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	855	0	0
T3	41460	2	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	1	0	0
T11	49557	0	0	0
T12	59237	1	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T17	47788	1	0	0
T27	0	1	0	0
T31	0	2	0	0
T43	0	3	0	0
T48	0	2	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	826	0	0
T3	41460	2	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	1	0	0
T11	49557	0	0	0
T12	59237	1	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T17	47788	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T43	0	3	0	0
T48	0	2	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	797	0	0
T3	41460	2	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	1	0	0
T11	49557	0	0	0
T12	59237	1	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T17	47788	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T43	0	3	0	0
T48	0	2	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	782	0	0
T3	41460	2	0	0
T4	27925	0	0	0
T5	34293	0	0	0
T10	40283	1	0	0
T11	49557	0	0	0
T12	59237	1	0	0
T13	76217	0	0	0
T14	4599	0	0	0
T15	33239	1	0	0
T17	47788	1	0	0
T27	0	1	0	0
T31	0	1	0	0
T43	0	3	0	0
T48	0	2	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	514	0	0
T5	34293	0	0	0
T6	23610	0	0	0
T11	49557	6	0	0
T13	76217	7	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	3	0	0
T34	0	1	0	0
T41	0	1	0	0
T48	0	1	0	0
T76	0	3	0	0
T79	0	12	0	0
T88	0	2	0	0
T89	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	63612	0	0
T5	34293	0	0	0
T6	23610	0	0	0
T11	49557	907	0	0
T13	76217	1349	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	507	0	0
T34	0	179	0	0
T41	0	1	0	0
T48	0	51	0	0
T76	0	296	0	0
T79	0	1365	0	0
T88	0	133	0	0
T89	0	140	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	403	0	0
T5	34293	0	0	0
T6	23610	0	0	0
T11	49557	6	0	0
T13	76217	7	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	2	0	0
T34	0	1	0	0
T42	0	2	0	0
T48	0	1	0	0
T76	0	2	0	0
T79	0	12	0	0
T88	0	2	0	0
T89	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	67	0	0
T7	61075	0	0	0
T8	47065	0	0	0
T9	24025	0	0	0
T27	31509	1	0	0
T30	0	1	0	0
T31	56799	0	0	0
T33	0	3	0	0
T36	0	1	0	0
T43	78983	0	0	0
T48	8812	0	0	0
T49	17911	0	0	0
T54	0	1	0	0
T76	0	1	0	0
T88	14691	0	0	0
T92	1151	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T102	0	3	0	0
T103	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	1153	0	0
T5	34293	351	0	0
T6	23610	169	0	0
T7	61075	0	0	0
T9	0	142	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	152	0	0
T47	0	339	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	943	0	0
T5	34293	291	0	0
T6	23610	139	0	0
T7	61075	0	0	0
T9	0	112	0	0
T11	49557	0	0	0
T14	4599	0	0	0
T15	33239	0	0	0
T16	3072	0	0	0
T17	47788	0	0	0
T26	34781	0	0	0
T27	31509	0	0	0
T46	0	122	0	0
T47	0	279	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550427392	550357694	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	95	0	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T15	0	33142	0	0
T17	47788	47714	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	550566037	550407217	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0