Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	666366	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4054106

1

T4

374

T6

73

T7

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1157686	1			T4	408		T6	7		T7	2
values[0x0]	1634939	1			T4	184		T6	76		T7	3
values[0x1]	1927847	1			T4	207		T6	72		T7	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	357591	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4362881

1

T4

482

T6

96

T7

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17139	1			T4	10		T32	2		T33	10
valid_sources[0x01]	18583	1			T4	4		T27	3		T32	2
valid_sources[0x02]	19402	1			T4	4		T31	18		T73	2
valid_sources[0x03]	20254	1			T4	2		T27	3		T73	9
valid_sources[0x04]	17203	1			T4	9		T27	1		T33	2
valid_sources[0x05]	19078	1			T4	1		T73	3		T75	4
valid_sources[0x06]	17951	1			T4	3		T6	4		T27	2
valid_sources[0x07]	17932	1			T4	4		T27	2		T28	2
valid_sources[0x08]	18994	1			T4	1		T73	5		T75	1
valid_sources[0x09]	17488	1			T4	1		T7	7		T27	1
valid_sources[0x0a]	18731	1			T4	1		T27	1		T73	4
valid_sources[0x0b]	19770	1			T4	5		T27	2		T75	5
valid_sources[0x0c]	19068	1			T4	3		T27	2		T28	12
valid_sources[0x0d]	18551	1			T4	2		T27	1		T28	17
valid_sources[0x0e]	20643	1			T4	2		T28	2		T73	3
valid_sources[0x0f]	17168	1			T4	3		T27	1		T28	8
valid_sources[0x10]	17387	1			T4	5		T27	4		T73	9
valid_sources[0x11]	19655	1			T4	4		T33	1		T73	1
valid_sources[0x12]	19001	1			T27	5		T32	1		T73	6
valid_sources[0x13]	19898	1			T4	1		T27	1		T73	5
valid_sources[0x14]	17726	1			T4	5		T28	8		T32	3
valid_sources[0x15]	17735	1			T4	2		T27	1		T33	6
valid_sources[0x16]	18929	1			T6	13		T73	6		T41	1
valid_sources[0x17]	18300	1			T4	3		T27	2		T28	6
valid_sources[0x18]	20739	1			T4	1		T27	2		T31	2
valid_sources[0x19]	18376	1			T4	2		T27	1		T28	2
valid_sources[0x1a]	18971	1			T4	4		T27	1		T33	4
valid_sources[0x1b]	17636	1			T4	3		T28	7		T33	3
valid_sources[0x1c]	17780	1			T4	4		T27	2		T32	7
valid_sources[0x1d]	17773	1			T4	5		T27	1		T28	21
valid_sources[0x1e]	18390	1			T4	4		T73	5		T75	7
valid_sources[0x1f]	18288	1			T4	4		T6	3		T27	2
valid_sources[0x20]	18126	1			T4	5		T27	2		T28	3
valid_sources[0x21]	20909	1			T4	1		T27	2		T33	3
valid_sources[0x22]	18313	1			T4	2		T28	8		T73	7
valid_sources[0x23]	18861	1			T4	5		T28	5		T73	3
valid_sources[0x24]	17764	1			T4	4		T33	2		T73	2
valid_sources[0x25]	19198	1			T4	6		T27	1		T28	36
valid_sources[0x26]	19655	1			T4	3		T27	2		T73	7
valid_sources[0x27]	18500	1			T6	4		T33	9		T73	2
valid_sources[0x28]	18649	1			T27	1		T73	7		T75	6
valid_sources[0x29]	18995	1			T4	5		T27	3		T33	2
valid_sources[0x2a]	18192	1			T4	2		T27	3		T33	1
valid_sources[0x2b]	18402	1			T4	6		T73	7		T75	6
valid_sources[0x2c]	18694	1			T4	4		T33	2		T73	1
valid_sources[0x2d]	18279	1			T4	4		T6	3		T27	1
valid_sources[0x2e]	18239	1			T4	7		T27	1		T33	5
valid_sources[0x2f]	19151	1			T4	3		T73	5		T76	3
valid_sources[0x30]	17424	1			T4	5		T27	2		T75	8
valid_sources[0x31]	19905	1			T4	4		T27	1		T73	4
valid_sources[0x32]	17390	1			T4	2		T32	1		T75	2
valid_sources[0x33]	18187	1			T4	3		T6	3		T27	1
valid_sources[0x34]	16839	1			T27	1		T73	1		T41	1
valid_sources[0x35]	19205	1			T4	1		T27	4		T33	2
valid_sources[0x36]	17588	1			T4	1		T27	1		T28	14
valid_sources[0x37]	19475	1			T4	3		T27	2		T33	5
valid_sources[0x38]	18149	1			T4	3		T27	1		T31	5
valid_sources[0x39]	18624	1			T4	4		T27	2		T33	1
valid_sources[0x3a]	17807	1			T4	1		T27	1		T73	1
valid_sources[0x3b]	19261	1			T4	2		T27	1		T32	1
valid_sources[0x3c]	18107	1			T4	4		T27	1		T73	10
valid_sources[0x3d]	19798	1			T4	2		T27	1		T31	28
valid_sources[0x3e]	20421	1			T4	3		T27	1		T73	1
valid_sources[0x3f]	19526	1			T4	6		T27	2		T33	6
valid_sources[0x40]	18087	1			T4	5		T27	1		T28	5
valid_sources[0x41]	18527	1			T4	5		T33	5		T73	1
valid_sources[0x42]	19952	1			T4	2		T27	3		T73	7
valid_sources[0x43]	18857	1			T4	8		T27	2		T33	3
valid_sources[0x44]	17217	1			T4	5		T27	3		T73	6
valid_sources[0x45]	20291	1			T4	5		T27	3		T73	10
valid_sources[0x46]	17884	1			T4	2		T6	11		T73	2
valid_sources[0x47]	17459	1			T4	9		T33	1		T73	4
valid_sources[0x48]	18980	1			T33	2		T73	3		T75	1
valid_sources[0x49]	17613	1			T4	2		T6	2		T75	1
valid_sources[0x4a]	17241	1			T4	2		T6	11		T73	16
valid_sources[0x4b]	17448	1			T4	6		T27	1		T33	6
valid_sources[0x4c]	18137	1			T4	2		T30	27		T33	1
valid_sources[0x4d]	19769	1			T4	4		T27	1		T75	1
valid_sources[0x4e]	20174	1			T4	2		T73	1		T75	5
valid_sources[0x4f]	18528	1			T4	3		T73	11		T76	7
valid_sources[0x50]	17876	1			T4	3		T6	6		T27	4
valid_sources[0x51]	19367	1			T4	4		T27	1		T73	4
valid_sources[0x52]	18084	1			T4	4		T27	1		T28	1
valid_sources[0x53]	18606	1			T4	3		T27	3		T32	3
valid_sources[0x54]	17190	1			T4	1		T27	3		T32	6
valid_sources[0x55]	17167	1			T4	2		T27	1		T28	2
valid_sources[0x56]	21246	1			T4	3		T27	1		T32	8
valid_sources[0x57]	17189	1			T4	1		T27	1		T32	1
valid_sources[0x58]	19433	1			T4	7		T6	5		T73	7
valid_sources[0x59]	18903	1			T4	5		T6	1		T27	1
valid_sources[0x5a]	19521	1			T4	8		T75	1		T76	6
valid_sources[0x5b]	18529	1			T27	1		T73	1		T47	7
valid_sources[0x5c]	17885	1			T4	3		T28	2		T33	2
valid_sources[0x5d]	18718	1			T27	1		T33	1		T73	1
valid_sources[0x5e]	17813	1			T4	3		T33	7		T73	4
valid_sources[0x5f]	18161	1			T4	3		T33	3		T73	1
valid_sources[0x60]	18671	1			T4	2		T73	8		T75	4
valid_sources[0x61]	20413	1			T4	2		T27	1		T28	3
valid_sources[0x62]	18426	1			T4	3		T27	1		T28	5
valid_sources[0x63]	18693	1			T4	6		T27	3		T30	11
valid_sources[0x64]	19590	1			T27	1		T33	6		T73	11
valid_sources[0x65]	19102	1			T4	1		T27	1		T32	4
valid_sources[0x66]	19318	1			T4	1		T31	7		T32	1
valid_sources[0x67]	18327	1			T4	2		T27	1		T32	1
valid_sources[0x68]	17151	1			T4	2		T27	2		T33	2
valid_sources[0x69]	18357	1			T4	1		T27	1		T33	1
valid_sources[0x6a]	17551	1			T4	3		T27	1		T32	8
valid_sources[0x6b]	19329	1			T4	3		T75	3		T41	2
valid_sources[0x6c]	18139	1			T4	4		T33	3		T73	5
valid_sources[0x6d]	18185	1			T4	5		T27	2		T33	1
valid_sources[0x6e]	16755	1			T4	3		T27	2		T32	6
valid_sources[0x6f]	19005	1			T4	3		T6	1		T27	1
valid_sources[0x70]	17596	1			T4	3		T32	4		T33	3
valid_sources[0x71]	16664	1			T4	7		T73	1		T47	15
valid_sources[0x72]	17375	1			T73	10		T75	1		T41	4
valid_sources[0x73]	18463	1			T4	4		T27	3		T28	9
valid_sources[0x74]	17447	1			T4	2		T6	3		T28	15
valid_sources[0x75]	18661	1			T4	3		T27	1		T73	7
valid_sources[0x76]	18571	1			T4	4		T27	1		T33	6
valid_sources[0x77]	18244	1			T6	8		T28	10		T33	9
valid_sources[0x78]	19285	1			T4	3		T27	3		T32	1
valid_sources[0x79]	17373	1			T4	6		T6	2		T32	2
valid_sources[0x7a]	18661	1			T4	6		T6	6		T33	4
valid_sources[0x7b]	18441	1			T33	4		T76	1		T42	8
valid_sources[0x7c]	19841	1			T4	2		T33	2		T73	3
valid_sources[0x7d]	18114	1			T4	2		T27	2		T33	1
valid_sources[0x7e]	16303	1			T4	3		T27	2		T73	1
valid_sources[0x7f]	17185	1			T4	1		T27	1		T32	2
valid_sources[0x80]	18323	1			T4	1		T27	2		T32	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1022706

1

T4

203

T6

5

T7

1

values[0x0]

all_enables

biggest_size

1539401

1

T4

111

T6

42

T7

1

values[0x1]

all_enables

biggest_size

1491999

1

T4

60

T6

26

T7

1