Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	841482710	78589	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	841482710	78589	0	0
T1	397100	97	0	0
T2	4339485	337	0	0
T3	98445	44	0	0
T9	1971005	338	0	0
T10	0	2105	0	0
T11	0	811	0	0
T12	0	1059	0	0
T13	0	540	0	0
T14	0	195	0	0
T15	0	149	0	0
T16	7180	0	0	0
T17	4285	0	0	0
T18	7410	0	0	0
T19	10255	0	0	0
T20	8455	0	0	0
T21	8425	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168296542	11451	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	11451	0	0
T1	79420	16	0	0
T2	867897	53	0	0
T3	19689	7	0	0
T9	394201	43	0	0
T10	0	281	0	0
T11	0	107	0	0
T12	0	156	0	0
T13	0	80	0	0
T14	0	39	0	0
T15	0	20	0	0
T16	1436	0	0	0
T17	857	0	0	0
T18	1482	0	0	0
T19	2051	0	0	0
T20	1691	0	0	0
T21	1685	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168296542	15853	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	15853	0	0
T1	79420	19	0	0
T2	867897	68	0	0
T3	19689	9	0	0
T9	394201	68	0	0
T10	0	423	0	0
T11	0	162	0	0
T12	0	218	0	0
T13	0	107	0	0
T14	0	39	0	0
T15	0	30	0	0
T16	1436	0	0	0
T17	857	0	0	0
T18	1482	0	0	0
T19	2051	0	0	0
T20	1691	0	0	0
T21	1685	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168296542	24162	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	24162	0	0
T1	79420	27	0	0
T2	867897	95	0	0
T3	19689	12	0	0
T9	394201	112	0	0
T10	0	700	0	0
T11	0	273	0	0
T12	0	347	0	0
T13	0	178	0	0
T14	0	39	0	0
T15	0	49	0	0
T16	1436	0	0	0
T17	857	0	0	0
T18	1482	0	0	0
T19	2051	0	0	0
T20	1691	0	0	0
T21	1685	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168296542	11232	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	11232	0	0
T1	79420	16	0	0
T2	867897	53	0	0
T3	19689	7	0	0
T9	394201	49	0	0
T10	0	274	0	0
T11	0	102	0	0
T12	0	132	0	0
T13	0	69	0	0
T14	0	39	0	0
T15	0	20	0	0
T16	1436	0	0	0
T17	857	0	0	0
T18	1482	0	0	0
T19	2051	0	0	0
T20	1691	0	0	0
T21	1685	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	168296542	15891	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	15891	0	0
T1	79420	19	0	0
T2	867897	68	0	0
T3	19689	9	0	0
T9	394201	66	0	0
T10	0	427	0	0
T11	0	167	0	0
T12	0	206	0	0
T13	0	106	0	0
T14	0	39	0	0
T15	0	30	0	0
T16	1436	0	0	0
T17	857	0	0	0
T18	1482	0	0	0
T19	2051	0	0	0
T20	1691	0	0	0
T21	1685	0	0	0