Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Unreachable
1	0	Covered	T4,T5,T1

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	168296542	165567925	0	0
AllClkBypReqTrue_A	168296542	129313	0	0
IoClkBypReqFalse_A	168296542	165486043	0	2409
IoClkBypReqTrue_A	168296542	206627	0	0
LcClkBypAckFalse_A	168296542	165576068	0	0
LcClkBypAckTrue_A	168296542	121170	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	165567925	0	0
T1	79420	79011	0	0
T2	867897	862453	0	0
T4	110138	7954	0	0
T5	26608	3088	0	0
T6	24359	24336	0	0
T7	1046	931	0	0
T16	1436	1224	0	0
T22	1614	1455	0	0
T23	1587	1391	0	0
T24	1407	1345	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	129313	0	0
T1	79420	280	0	0
T2	867897	728	0	0
T3	19689	0	0	0
T7	1046	44	0	0
T9	0	333	0	0
T16	1436	188	0	0
T17	857	0	0	0
T18	1482	0	0	0
T22	1614	36	0	0
T23	1587	104	0	0
T24	1407	0	0	0
T110	0	29	0	0
T111	0	122	0	0
T112	0	317	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	165486043	0	2409
T1	79420	78801	0	3
T2	867897	861992	0	3
T4	110138	7918	0	3
T5	26608	3052	0	3
T6	24359	24334	0	3
T7	1046	902	0	3
T16	1436	1190	0	3
T22	1614	1489	0	3
T23	1587	1338	0	3
T24	1407	1343	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	206627	0	0
T1	79420	484	0	0
T2	867897	1177	0	0
T3	19689	0	0	0
T7	1046	71	0	0
T9	0	561	0	0
T10	0	186	0	0
T16	1436	220	0	0
T17	857	0	0	0
T18	1482	0	0	0
T19	2051	0	0	0
T23	1587	155	0	0
T24	1407	0	0	0
T111	0	214	0	0
T112	0	402	0	0
T113	0	258	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	165576068	0	0
T1	79420	78952	0	0
T2	867897	862439	0	0
T4	110138	7954	0	0
T5	26608	3088	0	0
T6	24359	24336	0	0
T7	1046	923	0	0
T16	1436	1259	0	0
T22	1614	1491	0	0
T23	1587	1381	0	0
T24	1407	1345	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168296542	121170	0	0
T1	79420	339	0	0
T2	867897	742	0	0
T3	19689	0	0	0
T7	1046	52	0	0
T9	0	332	0	0
T10	0	138	0	0
T16	1436	153	0	0
T17	857	0	0	0
T18	1482	0	0	0
T19	2051	0	0	0
T23	1587	114	0	0
T24	1407	0	0	0
T111	0	81	0	0
T112	0	203	0	0
T113	0	197	0	0