Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1730664404	16344	0	0
TransStop_A	1730664404	8364	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730664404	16344	0	0
T1	1516424	4	0	0
T2	1364644	105	0	0
T3	463288	0	0	0
T9	1552808	11	0	0
T10	0	141	0	0
T11	0	191	0	0
T12	0	53	0	0
T13	0	35	0	0
T14	0	42	0	0
T16	30260	0	0	0
T17	13732	0	0	0
T18	98868	0	0	0
T19	51296	0	0	0
T20	6096	0	0	0
T21	6880	0	0	0
T114	0	35	0	0
T115	0	40	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1730664404	8364	0	0
T2	1364644	68	0	0
T3	463288	0	0	0
T9	1552808	6	0	0
T10	0	83	0	0
T11	0	117	0	0
T12	0	28	0	0
T13	0	27	0	0
T14	0	22	0	0
T16	30260	0	0	0
T17	13732	0	0	0
T18	98868	0	0	0
T19	51296	0	0	0
T20	6096	0	0	0
T21	6880	0	0	0
T110	17268	0	0	0
T114	0	16	0	0
T115	0	14	0	0
T116	0	5	0	0
T117	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	432666101	4043	0	0
TransStop_A	432666101	2086	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	4043	0	0
T1	379106	1	0	0
T2	341161	25	0	0
T3	115822	0	0	0
T9	388202	2	0	0
T10	0	37	0	0
T11	0	46	0	0
T12	0	14	0	0
T13	0	8	0	0
T14	0	12	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T114	0	9	0	0
T115	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	2086	0	0
T2	341161	17	0	0
T3	115822	0	0	0
T9	388202	1	0	0
T10	0	22	0	0
T11	0	25	0	0
T12	0	7	0	0
T13	0	6	0	0
T14	0	7	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T110	4317	0	0	0
T114	0	4	0	0
T115	0	3	0	0
T116	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	432666101	4110	0	0
TransStop_A	432666101	2080	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	4110	0	0
T1	379106	1	0	0
T2	341161	30	0	0
T3	115822	0	0	0
T9	388202	3	0	0
T10	0	32	0	0
T11	0	47	0	0
T12	0	14	0	0
T13	0	9	0	0
T14	0	11	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T114	0	9	0	0
T115	0	12	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	2080	0	0
T2	341161	17	0	0
T3	115822	0	0	0
T9	388202	2	0	0
T10	0	17	0	0
T11	0	31	0	0
T12	0	7	0	0
T13	0	6	0	0
T14	0	7	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T110	4317	0	0	0
T114	0	6	0	0
T115	0	4	0	0
T116	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	432666101	4104	0	0
TransStop_A	432666101	2112	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	4104	0	0
T1	379106	1	0	0
T2	341161	21	0	0
T3	115822	0	0	0
T9	388202	3	0	0
T10	0	35	0	0
T11	0	50	0	0
T12	0	12	0	0
T13	0	8	0	0
T14	0	8	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T114	0	9	0	0
T115	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	2112	0	0
T2	341161	16	0	0
T3	115822	0	0	0
T9	388202	2	0	0
T10	0	23	0	0
T11	0	31	0	0
T12	0	5	0	0
T13	0	7	0	0
T14	0	3	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T110	4317	0	0	0
T114	0	3	0	0
T115	0	3	0	0
T117	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	432666101	4087	0	0
TransStop_A	432666101	2086	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	4087	0	0
T1	379106	1	0	0
T2	341161	29	0	0
T3	115822	0	0	0
T9	388202	3	0	0
T10	0	37	0	0
T11	0	48	0	0
T12	0	13	0	0
T13	0	10	0	0
T14	0	11	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T114	0	8	0	0
T115	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432666101	2086	0	0
T2	341161	18	0	0
T3	115822	0	0	0
T9	388202	1	0	0
T10	0	21	0	0
T11	0	30	0	0
T12	0	9	0	0
T13	0	8	0	0
T14	0	5	0	0
T16	7565	0	0	0
T17	3433	0	0	0
T18	24717	0	0	0
T19	12824	0	0	0
T20	1524	0	0	0
T21	1720	0	0	0
T110	4317	0	0	0
T114	0	3	0	0
T115	0	4	0	0
T116	0	2	0	0