Module Definition
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Module : clkmgr_extclk_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_extclk_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_extclk_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.63 100.00 93.15 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : clkmgr_extclk_sva_if
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS3411100.00
ALWAYS4911100.00
ALWAYS6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
49 1 1
66 1 1


Cond Coverage for Module : clkmgr_extclk_sva_if
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (lc_clk_byp_req_i == On)
            ------------1-----------
-1-StatusTests
0CoveredT7,T22,T23
1CoveredT7,T23,T1

 LINE       49
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    ------------2-----------
-1--2-StatusTests
01CoveredT7,T22,T23
10CoveredT5,T22,T23
11CoveredT7,T22,T23

 LINE       49
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------
-1-StatusTests
0CoveredT7,T5,T22
1CoveredT7,T5,T22

 LINE       49
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------
-1-StatusTests
0CoveredT5,T22,T23
1CoveredT7,T22,T23

 LINE       66
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    -------------------2-------------------    ------------3-----------
-1--2--3-StatusTests
011CoveredT7,T22,T1
101CoveredT22,T23,T1
110CoveredT5,T22,T23
111CoveredT7,T23,T1

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------
-1-StatusTests
0CoveredT4,T7,T5
1CoveredT7,T5,T22

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
                -------------------1-------------------
-1-StatusTests
0CoveredT4,T7,T5
1CoveredT4,T7,T5

 LINE       66
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------
-1-StatusTests
0CoveredT4,T5,T22
1CoveredT7,T22,T23

Assert Coverage for Module : clkmgr_extclk_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllClkBypReqFall_A 168296542 4055 0 0
AllClkBypReqRise_A 168296542 4055 0 0
HiSpeedSelFall_A 168296542 2422 0 0
HiSpeedSelRise_A 168296542 2422 0 0
IoClkBypReqFall_A 168296542 5219 0 0
IoClkBypReqRise_A 168296542 5217 0 0


AllClkBypReqFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168296542 4055 0 0
T1 79420 8 0 0
T2 867897 31 0 0
T3 19689 0 0 0
T7 1046 1 0 0
T9 0 17 0 0
T16 1436 4 0 0
T17 857 0 0 0
T18 1482 0 0 0
T22 1614 2 0 0
T23 1587 4 0 0
T24 1407 0 0 0
T110 0 2 0 0
T111 0 6 0 0
T112 0 9 0 0

AllClkBypReqRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168296542 4055 0 0
T1 79420 8 0 0
T2 867897 31 0 0
T3 19689 0 0 0
T7 1046 1 0 0
T9 0 17 0 0
T16 1436 4 0 0
T17 857 0 0 0
T18 1482 0 0 0
T22 1614 2 0 0
T23 1587 4 0 0
T24 1407 0 0 0
T110 0 2 0 0
T111 0 6 0 0
T112 0 9 0 0

HiSpeedSelFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168296542 2422 0 0
T1 79420 6 0 0
T2 867897 21 0 0
T3 19689 0 0 0
T7 1046 1 0 0
T9 0 10 0 0
T10 0 2 0 0
T16 1436 2 0 0
T17 857 0 0 0
T18 1482 0 0 0
T19 2051 0 0 0
T23 1587 3 0 0
T24 1407 0 0 0
T110 0 2 0 0
T111 0 3 0 0
T112 0 6 0 0

HiSpeedSelRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168296542 2422 0 0
T1 79420 6 0 0
T2 867897 21 0 0
T3 19689 0 0 0
T7 1046 1 0 0
T9 0 10 0 0
T10 0 2 0 0
T16 1436 2 0 0
T17 857 0 0 0
T18 1482 0 0 0
T19 2051 0 0 0
T23 1587 3 0 0
T24 1407 0 0 0
T110 0 2 0 0
T111 0 3 0 0
T112 0 6 0 0

IoClkBypReqFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168296542 5219 0 0
T1 79420 10 0 0
T2 867897 39 0 0
T3 19689 0 0 0
T7 1046 2 0 0
T9 0 20 0 0
T10 0 6 0 0
T16 1436 5 0 0
T17 857 0 0 0
T18 1482 0 0 0
T19 2051 0 0 0
T23 1587 5 0 0
T24 1407 0 0 0
T111 0 7 0 0
T112 0 10 0 0
T113 0 6 0 0

IoClkBypReqRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 168296542 5217 0 0
T1 79420 10 0 0
T2 867897 39 0 0
T3 19689 0 0 0
T7 1046 2 0 0
T9 0 20 0 0
T10 0 6 0 0
T16 1436 5 0 0
T17 857 0 0 0
T18 1482 0 0 0
T19 2051 0 0 0
T23 1587 5 0 0
T24 1407 0 0 0
T111 0 7 0 0
T112 0 10 0 0
T113 0 6 0 0

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