Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	169195836	6007249	0	0
clk_enables_rd_A	169195836	30192	0	0
clk_hints_rd_A	169195836	26981	0	0
extclk_ctrl_rd_A	169195836	33619	0	0
extclk_ctrl_regwen_rd_A	169195836	25663	0	0
jitter_enable_rd_A	169195836	37793	0	0
jitter_regwen_rd_A	169195836	28251	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169195836	6007249	0	0
T28	4172	1	0	0
T32	3044	431	0	0
T41	4442	2	0	0
T42	9489	9	0	0
T43	3885	320	0	0
T44	2321	47	0	0
T45	1798	4	0	0
T80	0	719	0	0
T81	0	5	0	0
T89	5745	3	0	0
T93	4082	0	0	0
T133	691	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169195836	30192	0	0
T27	7422	28	0	0
T30	5500	21	0	0
T42	9489	186	0	0
T44	2321	17	0	0
T45	1798	0	0	0
T79	6694	0	0	0
T80	12604	39	0	0
T87	0	45	0	0
T89	5745	78	0	0
T93	4082	22	0	0
T94	0	184	0	0
T129	0	71	0	0
T133	691	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169195836	26981	0	0
T27	7422	25	0	0
T30	5500	19	0	0
T42	9489	82	0	0
T44	2321	11	0	0
T45	1798	0	0	0
T79	6694	0	0	0
T80	12604	44	0	0
T87	0	45	0	0
T89	5745	147	0	0
T93	4082	18	0	0
T94	0	233	0	0
T129	0	72	0	0
T133	691	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169195836	33619	0	0
T27	7422	27	0	0
T30	5500	24	0	0
T44	2321	4	0	0
T45	1798	0	0	0
T79	6694	0	0	0
T80	12604	10	0	0
T81	11636	0	0	0
T87	0	36	0	0
T89	5745	1	0	0
T93	4082	5	0	0
T94	0	20	0	0
T129	0	47	0	0
T133	691	0	0	0
T151	0	46	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169195836	25663	0	0
T27	7422	5	0	0
T30	5500	33	0	0
T42	9489	50	0	0
T44	2321	14	0	0
T45	1798	0	0	0
T79	6694	0	0	0
T80	12604	23	0	0
T87	0	23	0	0
T89	5745	42	0	0
T93	4082	22	0	0
T94	0	86	0	0
T129	0	113	0	0
T133	691	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169195836	37793	0	0
T27	7422	25	0	0
T30	5500	21	0	0
T42	9489	36	0	0
T44	2321	9	0	0
T45	1798	0	0	0
T79	6694	0	0	0
T80	12604	56	0	0
T87	0	28	0	0
T89	5745	44	0	0
T93	4082	24	0	0
T94	0	92	0	0
T129	0	57	0	0
T133	691	0	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	169195836	28251	0	0
T27	7422	17	0	0
T30	5500	6	0	0
T42	9489	42	0	0
T44	2321	5	0	0
T45	1798	0	0	0
T79	6694	0	0	0
T80	12604	28	0	0
T87	0	23	0	0
T89	5745	27	0	0
T93	4082	14	0	0
T94	0	132	0	0
T129	0	78	0	0
T133	691	0	0	0