Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48141	0	0
CgEnOn_A	2147483647	39002	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48141	0	0
T1	986999	59	0	0
T2	1623957	147	0	0
T4	147177	54	0	0
T5	158650	54	0	0
T6	121285	3	0	0
T7	3556	3	0	0
T9	0	2	0	0
T10	3291312	47	0	0
T12	2639866	24	0	0
T16	20896	3	0	0
T17	3433	0	0	0
T20	4900	33	0	0
T21	5368	0	0	0
T22	3350	3	0	0
T23	3356	3	0	0
T24	4795	41	0	0
T26	31500	0	0	0
T39	2435	7	0	0
T40	0	10	0	0
T110	9444	0	0	0
T111	18118	0	0	0
T112	19244	0	0	0
T152	0	5	0	0
T153	0	20	0	0
T154	0	25	0	0
T155	0	20	0	0
T156	0	10	0	0
T159	9138	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39002	0	0
T1	261243	51	0	0
T2	961630	158	0	0
T3	83299	0	0	0
T9	253595	39	0	0
T10	3291312	219	0	0
T11	0	315	0	0
T12	2345690	205	0	0
T13	0	17	0	0
T16	6071	0	0	0
T17	2391	0	0	0
T18	14835	0	0	0
T19	7775	0	0	0
T20	4484	57	0	0
T21	3649	0	0	0
T24	2039	38	0	0
T26	31500	0	0	0
T39	2435	14	0	0
T40	1523	12	0	0
T110	9444	0	0	0
T111	18118	0	0	0
T112	19244	0	0	0
T114	0	18	0	0
T152	4854	6	0	0
T153	0	25	0	0
T154	0	28	0	0
T155	0	23	0	0
T156	0	12	0	0
T157	0	9	0	0
T158	0	4	0	0
T159	5025	8	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	202928178	149	0	0
CgEnOn_A	202928178	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202928178	149	0	0
T10	182754	2	0	0
T12	146606	2	0	0
T20	739	6	0	0
T21	799	0	0	0
T26	5709	0	0	0
T39	523	1	0	0
T40	0	2	0	0
T110	2120	0	0	0
T111	4843	0	0	0
T112	4513	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	2010	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202928178	149	0	0
T10	182754	2	0	0
T12	146606	2	0	0
T20	739	6	0	0
T21	799	0	0	0
T26	5709	0	0	0
T39	523	1	0	0
T40	0	2	0	0
T110	2120	0	0	0
T111	4843	0	0	0
T112	4513	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	2010	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101463489	149	0	0
CgEnOn_A	101463489	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	149	0	0
T10	913772	2	0	0
T12	733028	2	0	0
T20	369	6	0	0
T21	400	0	0	0
T26	2854	0	0	0
T39	262	1	0	0
T40	0	2	0	0
T110	1060	0	0	0
T111	2421	0	0	0
T112	2255	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	1005	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	149	0	0
T10	913772	2	0	0
T12	733028	2	0	0
T20	369	6	0	0
T21	400	0	0	0
T26	2854	0	0	0
T39	262	1	0	0
T40	0	2	0	0
T110	1060	0	0	0
T111	2421	0	0	0
T112	2255	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	1005	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	405813822	149	0	0
CgEnOn_A	405813822	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405813822	149	0	0
T10	367242	2	0	0
T12	294176	2	0	0
T20	1530	6	0	0
T21	1650	0	0	0
T26	17229	0	0	0
T39	1126	1	0	0
T40	0	2	0	0
T110	4144	0	0	0
T111	6012	0	0	0
T112	7966	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	4113	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405813822	138	0	0
T10	367242	0	0	0
T20	1530	6	0	0
T21	1650	0	0	0
T26	17229	0	0	0
T39	1126	1	0	0
T40	1523	2	0	0
T110	4144	0	0	0
T111	6012	0	0	0
T112	7966	0	0	0
T152	4854	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T157	0	3	0	0
T158	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	432665647	154	0	0
CgEnOn_A	432665647	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	154	0	0
T2	341161	1	0	0
T3	115822	0	0	0
T9	388201	0	0	0
T11	0	1	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T110	4317	0	0	0
T152	0	1	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	3	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	151	0	0
T10	395444	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T26	17947	0	0	0
T39	1161	2	0	0
T40	1552	2	0	0
T110	4317	0	0	0
T111	6262	0	0	0
T112	8297	0	0	0
T152	5045	1	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	6	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101463489	149	0	0
CgEnOn_A	101463489	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	149	0	0
T10	913772	2	0	0
T12	733028	2	0	0
T20	369	6	0	0
T21	400	0	0	0
T26	2854	0	0	0
T39	262	1	0	0
T40	0	2	0	0
T110	1060	0	0	0
T111	2421	0	0	0
T112	2255	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	1005	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	149	0	0
T10	913772	2	0	0
T12	733028	2	0	0
T20	369	6	0	0
T21	400	0	0	0
T26	2854	0	0	0
T39	262	1	0	0
T40	0	2	0	0
T110	1060	0	0	0
T111	2421	0	0	0
T112	2255	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	1005	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	432665647	154	0	0
CgEnOn_A	432665647	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	154	0	0
T2	341161	1	0	0
T3	115822	0	0	0
T9	388201	0	0	0
T11	0	1	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T110	4317	0	0	0
T152	0	1	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	3	0	0
T160	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	151	0	0
T10	395444	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T26	17947	0	0	0
T39	1161	2	0	0
T40	1552	2	0	0
T110	4317	0	0	0
T111	6262	0	0	0
T112	8297	0	0	0
T152	5045	1	0	0
T153	0	5	0	0
T154	0	3	0	0
T155	0	3	0	0
T156	0	2	0	0
T157	0	6	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Unreachable
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101463489	149	0	0
CgEnOn_A	101463489	149	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	149	0	0
T10	913772	2	0	0
T12	733028	2	0	0
T20	369	6	0	0
T21	400	0	0	0
T26	2854	0	0	0
T39	262	1	0	0
T40	0	2	0	0
T110	1060	0	0	0
T111	2421	0	0	0
T112	2255	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	1005	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	149	0	0
T10	913772	2	0	0
T12	733028	2	0	0
T20	369	6	0	0
T21	400	0	0	0
T26	2854	0	0	0
T39	262	1	0	0
T40	0	2	0	0
T110	1060	0	0	0
T111	2421	0	0	0
T112	2255	0	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	0	5	0	0
T155	0	4	0	0
T156	0	2	0	0
T159	1005	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T39,T40
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	202928178	7581	0	0
CgEnOn_A	202928178	5308	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202928178	7581	0	0
T1	174163	19	0	0
T2	160272	40	0	0
T4	27631	18	0	0
T5	31731	18	0	0
T6	34638	1	0	0
T7	1032	1	0	0
T16	4048	1	0	0
T22	927	1	0	0
T23	999	1	0	0
T24	1359	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202928178	5308	0	0
T1	174163	16	0	0
T2	160272	34	0	0
T3	55533	0	0	0
T9	169065	11	0	0
T10	0	50	0	0
T11	0	79	0	0
T12	0	57	0	0
T16	4048	0	0	0
T17	1594	0	0	0
T18	9890	0	0	0
T19	5183	0	0	0
T20	739	6	0	0
T24	1359	14	0	0
T39	0	1	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T39,T40
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	101463489	7155	0	0
CgEnOn_A	101463489	4882	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	7155	0	0
T1	87080	19	0	0
T2	801358	41	0	0
T4	13817	18	0	0
T5	15866	18	0	0
T6	17319	1	0	0
T7	515	1	0	0
T16	2023	1	0	0
T22	463	1	0	0
T23	499	1	0	0
T24	680	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463489	4882	0	0
T1	87080	16	0	0
T2	801358	35	0	0
T3	27766	0	0	0
T9	84530	7	0	0
T10	0	34	0	0
T11	0	45	0	0
T12	0	39	0	0
T16	2023	0	0	0
T17	797	0	0	0
T18	4945	0	0	0
T19	2592	0	0	0
T20	369	6	0	0
T24	680	12	0	0
T39	0	1	0	0
T159	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T39,T40
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	405813822	7830	0	0
CgEnOn_A	405813822	5547	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405813822	7830	0	0
T1	346650	20	0	0
T2	321166	40	0	0
T4	105729	18	0	0
T5	111053	18	0	0
T6	69328	1	0	0
T7	2009	1	0	0
T16	7261	1	0	0
T22	1960	1	0	0
T23	1858	1	0	0
T24	2756	13	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405813822	5547	0	0
T1	346650	17	0	0
T2	321166	34	0	0
T3	111186	0	0	0
T9	338103	16	0	0
T10	0	58	0	0
T11	0	98	0	0
T12	0	73	0	0
T16	7261	0	0	0
T17	3295	0	0	0
T18	23727	0	0	0
T19	12310	0	0	0
T20	1530	6	0	0
T24	2756	12	0	0
T39	0	1	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T39,T40
1	0	Covered	T4,T6,T7
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	207772112	7562	0	0
CgEnOn_A	207772112	5279	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207772112	7562	0	0
T1	184853	21	0	0
T2	164911	38	0	0
T4	52867	18	0	0
T5	55529	18	0	0
T6	40425	1	0	0
T7	1005	1	0	0
T16	3631	1	0	0
T22	980	1	0	0
T23	929	1	0	0
T24	1378	15	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207772112	5279	0	0
T1	184853	18	0	0
T2	164911	32	0	0
T3	55595	0	0	0
T9	186339	11	0	0
T10	0	49	0	0
T11	0	81	0	0
T12	0	53	0	0
T16	3631	0	0	0
T17	1648	0	0	0
T18	11864	0	0	0
T19	6154	0	0	0
T20	744	3	0	0
T24	1378	14	0	0
T39	0	1	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	432665647	4197	0	0
CgEnOn_A	432665647	4195	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4197	0	0
T1	379106	1	0	0
T2	341161	26	0	0
T3	115822	0	0	0
T9	388201	2	0	0
T10	0	37	0	0
T11	0	47	0	0
T12	0	14	0	0
T13	0	8	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4195	0	0
T1	379106	1	0	0
T2	341161	25	0	0
T3	115822	0	0	0
T9	388201	2	0	0
T10	0	37	0	0
T11	0	46	0	0
T12	0	14	0	0
T13	0	8	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	432665647	4264	0	0
CgEnOn_A	432665647	4262	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4264	0	0
T1	379106	1	0	0
T2	341161	31	0	0
T3	115822	0	0	0
T9	388201	3	0	0
T10	0	32	0	0
T11	0	48	0	0
T12	0	14	0	0
T13	0	9	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4262	0	0
T1	379106	1	0	0
T2	341161	30	0	0
T3	115822	0	0	0
T9	388201	3	0	0
T10	0	32	0	0
T11	0	47	0	0
T12	0	14	0	0
T13	0	9	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	432665647	4258	0	0
CgEnOn_A	432665647	4255	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4258	0	0
T1	379106	1	0	0
T2	341161	22	0	0
T3	115822	0	0	0
T9	388201	3	0	0
T10	0	35	0	0
T11	0	51	0	0
T12	0	12	0	0
T13	0	8	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	9	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4255	0	0
T1	379106	1	0	0
T2	341161	21	0	0
T3	115822	0	0	0
T9	388201	3	0	0
T10	0	35	0	0
T11	0	50	0	0
T12	0	12	0	0
T13	0	8	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T1,T2,T9
1	1	Covered	T4,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	432665647	4241	0	0
CgEnOn_A	432665647	4238	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4241	0	0
T1	379106	1	0	0
T2	341161	30	0	0
T3	115822	0	0	0
T9	388201	3	0	0
T10	0	37	0	0
T11	0	49	0	0
T12	0	13	0	0
T13	0	10	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	8	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	432665647	4238	0	0
T1	379106	1	0	0
T2	341161	29	0	0
T3	115822	0	0	0
T9	388201	3	0	0
T10	0	37	0	0
T11	0	48	0	0
T12	0	13	0	0
T13	0	10	0	0
T16	7564	0	0	0
T17	3433	0	0	0
T18	24716	0	0	0
T19	12823	0	0	0
T20	1524	3	0	0
T21	1719	0	0	0
T39	0	2	0	0
T114	0	8	0	0