Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T2
0	1	Covered	T24,T1,T2
1	0	Covered	T7,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T20,T39,T40
1	1	Covered	T7,T22,T23

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	917979269	14333	0	0
GateOpen_A	917979269	14333	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	917979269	14333	0	0
T1	792749	49	0	0
T2	1447708	90	0	0
T3	250081	0	0	0
T9	778040	30	0	0
T10	0	114	0	0
T11	0	262	0	0
T12	0	175	0	0
T16	16965	0	0	0
T17	7336	0	0	0
T18	50428	0	0	0
T19	26241	0	0	0
T20	3384	21	0	0
T24	6176	29	0	0
T39	0	4	0	0
T159	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	917979269	14333	0	0
T1	792749	49	0	0
T2	1447708	90	0	0
T3	250081	0	0	0
T9	778040	30	0	0
T10	0	114	0	0
T11	0	262	0	0
T12	0	175	0	0
T16	16965	0	0	0
T17	7336	0	0	0
T18	50428	0	0	0
T19	26241	0	0	0
T20	3384	21	0	0
T24	6176	29	0	0
T39	0	4	0	0
T159	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T2
0	1	Covered	T24,T1,T2
1	0	Covered	T7,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T20,T39,T40
1	1	Covered	T7,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	101463905	3469	0	0
GateOpen_A	101463905	3469	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463905	3469	0	0
T1	87081	11	0	0
T2	801359	23	0	0
T3	27767	0	0	0
T9	84531	5	0	0
T10	0	24	0	0
T11	0	57	0	0
T12	0	34	0	0
T16	2024	0	0	0
T17	798	0	0	0
T18	4945	0	0	0
T19	2592	0	0	0
T20	370	6	0	0
T24	680	6	0	0
T39	0	1	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	101463905	3469	0	0
T1	87081	11	0	0
T2	801359	23	0	0
T3	27767	0	0	0
T9	84531	5	0	0
T10	0	24	0	0
T11	0	57	0	0
T12	0	34	0	0
T16	2024	0	0	0
T17	798	0	0	0
T18	4945	0	0	0
T19	2592	0	0	0
T20	370	6	0	0
T24	680	6	0	0
T39	0	1	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T2
0	1	Covered	T24,T1,T2
1	0	Covered	T7,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T20,T39,T40
1	1	Covered	T7,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	202928580	3608	0	0
GateOpen_A	202928580	3608	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202928580	3608	0	0
T1	174163	12	0	0
T2	160272	21	0	0
T3	55533	0	0	0
T9	169066	9	0	0
T10	0	32	0	0
T11	0	67	0	0
T12	0	47	0	0
T16	4048	0	0	0
T17	1595	0	0	0
T18	9890	0	0	0
T19	5184	0	0	0
T20	739	6	0	0
T24	1360	10	0	0
T39	0	1	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	202928580	3608	0	0
T1	174163	12	0	0
T2	160272	21	0	0
T3	55533	0	0	0
T9	169066	9	0	0
T10	0	32	0	0
T11	0	67	0	0
T12	0	47	0	0
T16	4048	0	0	0
T17	1595	0	0	0
T18	9890	0	0	0
T19	5184	0	0	0
T20	739	6	0	0
T24	1360	10	0	0
T39	0	1	0	0
T159	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T2
0	1	Covered	T24,T1,T2
1	0	Covered	T7,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T20,T39,T40
1	1	Covered	T7,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	405814263	3643	0	0
GateOpen_A	405814263	3643	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405814263	3643	0	0
T1	346651	13	0	0
T2	321166	24	0	0
T3	111186	0	0	0
T9	338103	8	0	0
T10	0	30	0	0
T11	0	67	0	0
T12	0	49	0	0
T16	7262	0	0	0
T17	3295	0	0	0
T18	23728	0	0	0
T19	12310	0	0	0
T20	1531	6	0	0
T24	2757	5	0	0
T39	0	1	0	0
T159	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405814263	3643	0	0
T1	346651	13	0	0
T2	321166	24	0	0
T3	111186	0	0	0
T9	338103	8	0	0
T10	0	30	0	0
T11	0	67	0	0
T12	0	49	0	0
T16	7262	0	0	0
T17	3295	0	0	0
T18	23728	0	0	0
T19	12310	0	0	0
T20	1531	6	0	0
T24	2757	5	0	0
T39	0	1	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T24,T1,T2
0	1	Covered	T24,T1,T2
1	0	Covered	T7,T22,T23

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T1,T2
1	0	Covered	T20,T39,T40
1	1	Covered	T7,T22,T23

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	207772521	3613	0	0
GateOpen_A	207772521	3613	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207772521	3613	0	0
T1	184854	13	0	0
T2	164911	22	0	0
T3	55595	0	0	0
T9	186340	8	0	0
T10	0	28	0	0
T11	0	71	0	0
T12	0	45	0	0
T16	3631	0	0	0
T17	1648	0	0	0
T18	11865	0	0	0
T19	6155	0	0	0
T20	744	3	0	0
T24	1379	8	0	0
T39	0	1	0	0
T159	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207772521	3613	0	0
T1	184854	13	0	0
T2	164911	22	0	0
T3	55595	0	0	0
T9	186340	8	0	0
T10	0	28	0	0
T11	0	71	0	0
T12	0	45	0	0
T16	3631	0	0	0
T17	1648	0	0	0
T18	11865	0	0	0
T19	6155	0	0	0
T20	744	3	0	0
T24	1379	8	0	0
T39	0	1	0	0
T159	0	2	0	0