Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1677401752	15182	0	0
TransStop_A	1677401752	7733	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1677401752	15182	0	0
T1	0	176	0	0
T2	0	554	0	0
T4	227940	0	0	0
T5	186908	0	0	0
T7	128616	0	0	0
T8	8156	18	0	0
T9	9712	0	0	0
T19	0	4	0	0
T23	0	25	0	0
T24	0	4	0	0
T26	0	41	0	0
T28	7348	0	0	0
T29	16252	0	0	0
T30	8652	0	0	0
T31	7040	0	0	0
T32	8336	2	0	0
T37	0	41	0	0
T112	0	43	0	0
T113	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1677401752	7733	0	0
T1	175941	108	0	0
T2	0	289	0	0
T4	170955	0	0	0
T5	140181	0	0	0
T7	96462	0	0	0
T8	6117	7	0	0
T9	7284	0	0	0
T19	2283	4	0	0
T20	9268	0	0	0
T21	2573	0	0	0
T22	2837	0	0	0
T23	3211	13	0	0
T24	0	4	0	0
T26	0	22	0	0
T28	5511	0	0	0
T29	12189	0	0	0
T30	6489	0	0	0
T31	5280	0	0	0
T32	6252	0	0	0
T37	9984	28	0	0
T38	7420	0	0	0
T39	11650	0	0	0
T40	1488	0	0	0
T112	0	23	0	0
T113	0	4	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419350438	3785	0	0
TransStop_A	419350438	1959	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	3785	0	0
T1	0	42	0	0
T2	0	142	0	0
T4	56985	0	0	0
T5	46727	0	0	0
T7	32154	0	0	0
T8	2039	8	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	6	0	0
T24	0	1	0	0
T26	0	9	0	0
T28	1837	0	0	0
T29	4063	0	0	0
T30	2163	0	0	0
T31	1760	0	0	0
T32	2084	0	0	0
T37	0	7	0	0
T112	0	10	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	1959	0	0
T1	0	25	0	0
T2	0	75	0	0
T4	56985	0	0	0
T5	46727	0	0	0
T7	32154	0	0	0
T8	2039	4	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	0	5	0	0
T28	1837	0	0	0
T29	4063	0	0	0
T30	2163	0	0	0
T31	1760	0	0	0
T32	2084	0	0	0
T37	0	5	0	0
T112	0	6	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419350438	3811	0	0
TransStop_A	419350438	1917	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	3811	0	0
T1	0	51	0	0
T2	0	137	0	0
T4	56985	0	0	0
T5	46727	0	0	0
T7	32154	0	0	0
T8	2039	4	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	0	9	0	0
T28	1837	0	0	0
T29	4063	0	0	0
T30	2163	0	0	0
T31	1760	0	0	0
T32	2084	1	0	0
T37	0	12	0	0
T112	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	1917	0	0
T1	0	34	0	0
T2	0	70	0	0
T4	56985	0	0	0
T5	46727	0	0	0
T7	32154	0	0	0
T8	2039	1	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T26	0	5	0	0
T28	1837	0	0	0
T29	4063	0	0	0
T30	2163	0	0	0
T31	1760	0	0	0
T32	2084	0	0	0
T37	0	8	0	0
T112	0	6	0	0
T113	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419350438	3755	0	0
TransStop_A	419350438	1908	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	3755	0	0
T1	0	38	0	0
T2	0	136	0	0
T4	56985	0	0	0
T5	46727	0	0	0
T7	32154	0	0	0
T8	2039	3	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	7	0	0
T24	0	1	0	0
T26	0	11	0	0
T28	1837	0	0	0
T29	4063	0	0	0
T30	2163	0	0	0
T31	1760	0	0	0
T32	2084	0	0	0
T37	0	11	0	0
T112	0	13	0	0
T113	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	1908	0	0
T1	175941	22	0	0
T2	0	75	0	0
T19	2283	1	0	0
T20	9268	0	0	0
T21	2573	0	0	0
T22	2837	0	0	0
T23	3211	3	0	0
T24	0	1	0	0
T26	0	6	0	0
T37	9984	6	0	0
T38	7420	0	0	0
T39	11650	0	0	0
T40	1488	0	0	0
T112	0	5	0	0
T113	0	1	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	419350438	3831	0	0
TransStop_A	419350438	1949	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	3831	0	0
T1	0	45	0	0
T2	0	139	0	0
T4	56985	0	0	0
T5	46727	0	0	0
T7	32154	0	0	0
T8	2039	3	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	8	0	0
T24	0	1	0	0
T26	0	12	0	0
T28	1837	0	0	0
T29	4063	0	0	0
T30	2163	0	0	0
T31	1760	0	0	0
T32	2084	1	0	0
T37	0	11	0	0
T112	0	9	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419350438	1949	0	0
T1	0	27	0	0
T2	0	69	0	0
T4	56985	0	0	0
T5	46727	0	0	0
T7	32154	0	0	0
T8	2039	2	0	0
T9	2428	0	0	0
T19	0	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	0	6	0	0
T28	1837	0	0	0
T29	4063	0	0	0
T30	2163	0	0	0
T31	1760	0	0	0
T32	2084	0	0	0
T37	0	9	0	0
T112	0	6	0	0
T113	0	1	0	0