Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	624419	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3607349

1

T1

113

T4

30

T2

103156

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1041642	1			T1	22		T4	42		T2	28103
values[0x0]	1469296	1			T1	96		T4	20		T2	42060
values[0x1]	1720830	1			T1	116		T4	19		T2	50417

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	343372	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3888396

1

T1

150

T4

36

T2

111521

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15174	1			T2	473		T3	334		T17	1
valid_sources[0x01]	16656	1			T2	431		T3	321		T17	1
valid_sources[0x02]	16511	1			T2	437		T3	344		T20	11
valid_sources[0x03]	15860	1			T2	482		T3	344		T20	7
valid_sources[0x04]	16932	1			T1	2		T2	494		T3	275
valid_sources[0x05]	17367	1			T1	1		T4	2		T2	451
valid_sources[0x06]	16496	1			T2	473		T3	339		T15	7
valid_sources[0x07]	16059	1			T4	2		T2	469		T3	294
valid_sources[0x08]	17038	1			T2	456		T3	344		T10	216
valid_sources[0x09]	15772	1			T2	483		T3	299		T20	7
valid_sources[0x0a]	17621	1			T2	543		T3	354		T20	7
valid_sources[0x0b]	17091	1			T2	461		T3	317		T8	2
valid_sources[0x0c]	15857	1			T1	2		T2	440		T3	358
valid_sources[0x0d]	16594	1			T2	456		T3	311		T21	3
valid_sources[0x0e]	15473	1			T1	3		T2	498		T3	307
valid_sources[0x0f]	16026	1			T2	463		T3	317		T20	1
valid_sources[0x10]	15396	1			T2	479		T3	299		T17	1
valid_sources[0x11]	14742	1			T1	4		T2	465		T3	307
valid_sources[0x12]	15974	1			T2	453		T3	349		T21	2
valid_sources[0x13]	17775	1			T2	495		T3	381		T21	1
valid_sources[0x14]	16048	1			T1	1		T2	475		T3	355
valid_sources[0x15]	16530	1			T1	2		T2	448		T3	292
valid_sources[0x16]	18244	1			T2	424		T3	313		T21	2
valid_sources[0x17]	16905	1			T2	478		T3	326		T20	6
valid_sources[0x18]	15679	1			T2	469		T3	305		T15	1
valid_sources[0x19]	17146	1			T2	491		T3	313		T21	1
valid_sources[0x1a]	17312	1			T2	491		T3	312		T16	50
valid_sources[0x1b]	16329	1			T1	3		T4	1		T2	476
valid_sources[0x1c]	15859	1			T2	450		T3	323		T21	1
valid_sources[0x1d]	17942	1			T1	3		T2	431		T3	285
valid_sources[0x1e]	16285	1			T2	484		T3	355		T20	1
valid_sources[0x1f]	15805	1			T2	459		T3	279		T20	3
valid_sources[0x20]	17301	1			T1	9		T2	476		T3	297
valid_sources[0x21]	16347	1			T1	2		T2	494		T3	394
valid_sources[0x22]	15986	1			T4	3		T2	445		T3	325
valid_sources[0x23]	16487	1			T2	416		T3	354		T20	9
valid_sources[0x24]	15821	1			T2	509		T3	294		T27	1
valid_sources[0x25]	15553	1			T2	445		T3	362		T21	1
valid_sources[0x26]	16135	1			T2	410		T3	324		T20	2
valid_sources[0x27]	16239	1			T1	9		T4	4		T2	448
valid_sources[0x28]	16271	1			T2	520		T3	312		T20	2
valid_sources[0x29]	15498	1			T1	12		T2	439		T3	316
valid_sources[0x2a]	16396	1			T2	456		T3	348		T20	3
valid_sources[0x2b]	16712	1			T2	479		T3	357		T92	2
valid_sources[0x2c]	16589	1			T2	502		T3	331		T21	3
valid_sources[0x2d]	16692	1			T2	480		T3	342		T10	236
valid_sources[0x2e]	15020	1			T2	505		T3	290		T20	1
valid_sources[0x2f]	17717	1			T4	1		T2	493		T3	329
valid_sources[0x30]	16879	1			T2	489		T3	276		T10	41
valid_sources[0x31]	16492	1			T2	477		T3	374		T20	1
valid_sources[0x32]	17311	1			T1	1		T2	479		T3	353
valid_sources[0x33]	15716	1			T1	1		T2	530		T3	359
valid_sources[0x34]	16760	1			T2	498		T3	367		T20	8
valid_sources[0x35]	17759	1			T1	2		T4	2		T2	524
valid_sources[0x36]	17105	1			T1	5		T2	444		T3	337
valid_sources[0x37]	16730	1			T2	460		T3	279		T20	4
valid_sources[0x38]	16191	1			T4	6		T2	449		T3	341
valid_sources[0x39]	17411	1			T2	470		T3	335		T20	11
valid_sources[0x3a]	16785	1			T1	7		T2	452		T3	322
valid_sources[0x3b]	17294	1			T1	3		T2	449		T3	305
valid_sources[0x3c]	15965	1			T2	421		T3	300		T9	2
valid_sources[0x3d]	16664	1			T1	1		T2	468		T3	349
valid_sources[0x3e]	17386	1			T1	1		T2	482		T3	307
valid_sources[0x3f]	15667	1			T1	1		T4	5		T2	478
valid_sources[0x40]	14741	1			T1	2		T4	3		T2	469
valid_sources[0x41]	17096	1			T2	490		T3	361		T8	2
valid_sources[0x42]	16564	1			T1	5		T2	500		T3	290
valid_sources[0x43]	17359	1			T1	1		T2	438		T3	360
valid_sources[0x44]	18059	1			T1	1		T2	500		T3	307
valid_sources[0x45]	16057	1			T2	447		T3	288		T15	1
valid_sources[0x46]	17277	1			T2	463		T3	362		T17	1
valid_sources[0x47]	18555	1			T1	3		T2	418		T3	319
valid_sources[0x48]	16679	1			T2	435		T3	322		T17	1
valid_sources[0x49]	16937	1			T1	6		T2	392		T3	312
valid_sources[0x4a]	16089	1			T1	6		T2	474		T3	297
valid_sources[0x4b]	17781	1			T4	4		T2	494		T3	333
valid_sources[0x4c]	16435	1			T2	431		T3	328		T20	3
valid_sources[0x4d]	15419	1			T2	504		T3	318		T20	2
valid_sources[0x4e]	17513	1			T1	1		T2	515		T3	299
valid_sources[0x4f]	16263	1			T1	2		T2	474		T3	344
valid_sources[0x50]	15575	1			T1	6		T2	422		T3	378
valid_sources[0x51]	15860	1			T2	449		T3	322		T21	2
valid_sources[0x52]	15606	1			T2	433		T3	311		T15	6
valid_sources[0x53]	17245	1			T2	420		T3	365		T20	6
valid_sources[0x54]	18137	1			T2	522		T3	323		T17	1
valid_sources[0x55]	16801	1			T2	481		T3	339		T21	1
valid_sources[0x56]	16120	1			T1	2		T2	510		T3	312
valid_sources[0x57]	16254	1			T2	514		T3	338		T20	9
valid_sources[0x58]	18467	1			T2	501		T3	262		T26	2
valid_sources[0x59]	16527	1			T4	2		T2	488		T3	290
valid_sources[0x5a]	15832	1			T1	4		T2	485		T3	357
valid_sources[0x5b]	17506	1			T2	424		T3	299		T21	1
valid_sources[0x5c]	15266	1			T4	4		T2	404		T3	331
valid_sources[0x5d]	15762	1			T1	1		T2	481		T3	331
valid_sources[0x5e]	15169	1			T2	479		T3	326		T17	1
valid_sources[0x5f]	17760	1			T2	516		T3	281		T20	6
valid_sources[0x60]	17533	1			T2	458		T3	271		T17	1
valid_sources[0x61]	16886	1			T2	424		T3	352		T27	1
valid_sources[0x62]	15739	1			T2	431		T3	311		T15	2
valid_sources[0x63]	16993	1			T1	7		T4	5		T2	451
valid_sources[0x64]	16193	1			T1	1		T2	370		T3	321
valid_sources[0x65]	16366	1			T2	466		T3	302		T21	1
valid_sources[0x66]	17043	1			T2	519		T3	354		T21	1
valid_sources[0x67]	16439	1			T2	474		T3	324		T27	1
valid_sources[0x68]	16867	1			T2	488		T3	317		T87	1
valid_sources[0x69]	17580	1			T2	475		T3	346		T20	2
valid_sources[0x6a]	17955	1			T1	4		T2	531		T3	289
valid_sources[0x6b]	14870	1			T1	6		T2	452		T3	367
valid_sources[0x6c]	15407	1			T2	498		T3	343		T15	3
valid_sources[0x6d]	15637	1			T2	498		T3	358		T21	1
valid_sources[0x6e]	16900	1			T2	470		T3	349		T17	1
valid_sources[0x6f]	16603	1			T2	481		T3	334		T20	5
valid_sources[0x70]	16707	1			T2	508		T3	343		T92	1
valid_sources[0x71]	16456	1			T2	496		T3	295		T20	1
valid_sources[0x72]	16140	1			T2	439		T3	313		T10	231
valid_sources[0x73]	16464	1			T1	2		T2	513		T3	310
valid_sources[0x74]	17335	1			T2	480		T3	278		T21	1
valid_sources[0x75]	14904	1			T2	481		T3	316		T15	3
valid_sources[0x76]	18372	1			T2	458		T3	316		T20	23
valid_sources[0x77]	17054	1			T2	524		T3	303		T20	1
valid_sources[0x78]	15683	1			T1	2		T2	519		T3	343
valid_sources[0x79]	15200	1			T2	462		T3	304		T20	5
valid_sources[0x7a]	15882	1			T2	498		T3	348		T17	1
valid_sources[0x7b]	17604	1			T4	1		T2	476		T3	370
valid_sources[0x7c]	14664	1			T2	505		T3	317		T21	1
valid_sources[0x7d]	15503	1			T2	525		T3	319		T17	1
valid_sources[0x7e]	15710	1			T2	493		T3	299		T17	1
valid_sources[0x7f]	16472	1			T2	414		T3	324		T92	1
valid_sources[0x80]	16409	1			T1	3		T2	443		T3	350

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

910984

1

T1

12

T4

18

T2

25405

values[0x0]

all_enables

biggest_size

1374642

1

T1

65

T4

9

T2

39447

values[0x1]

all_enables

biggest_size

1321723

1

T1

36

T4

3

T2

38304