Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	828317555	75294	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	828317555	75294	0	0
T1	561320	91	0	0
T2	2377585	1904	0	0
T3	1790060	469	0	0
T4	10965	0	0	0
T8	0	53	0	0
T9	0	273	0	0
T10	0	595	0	0
T11	0	977	0	0
T12	0	99	0	0
T13	0	159	0	0
T14	0	2818	0	0
T15	9960	0	0	0
T16	38735	0	0	0
T17	5465	0	0	0
T18	6640	0	0	0
T19	20735	0	0	0
T20	237905	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165663511	11033	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	11033	0	0
T1	112264	12	0	0
T2	475517	302	0	0
T3	358012	70	0	0
T4	2193	0	0	0
T8	0	8	0	0
T9	0	35	0	0
T10	0	96	0	0
T11	0	131	0	0
T12	0	16	0	0
T13	0	24	0	0
T14	0	356	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165663511	15128	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	15128	0	0
T1	112264	18	0	0
T2	475517	385	0	0
T3	358012	96	0	0
T4	2193	0	0	0
T8	0	10	0	0
T9	0	53	0	0
T10	0	120	0	0
T11	0	204	0	0
T12	0	21	0	0
T13	0	31	0	0
T14	0	566	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165663511	22955	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	22955	0	0
T1	112264	31	0	0
T2	475517	534	0	0
T3	358012	139	0	0
T4	2193	0	0	0
T8	0	16	0	0
T9	0	92	0	0
T10	0	165	0	0
T11	0	325	0	0
T12	0	28	0	0
T13	0	46	0	0
T14	0	925	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165663511	10921	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	10921	0	0
T1	112264	12	0	0
T2	475517	298	0	0
T3	358012	70	0	0
T4	2193	0	0	0
T8	0	8	0	0
T9	0	39	0	0
T10	0	95	0	0
T11	0	125	0	0
T12	0	15	0	0
T13	0	25	0	0
T14	0	407	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165663511	15257	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	15257	0	0
T1	112264	18	0	0
T2	475517	385	0	0
T3	358012	94	0	0
T4	2193	0	0	0
T8	0	11	0	0
T9	0	54	0	0
T10	0	119	0	0
T11	0	192	0	0
T12	0	19	0	0
T13	0	33	0	0
T14	0	564	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0