Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Unreachable
1	0	Covered	T2,T3,T16

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	165663511	162980580	0	0
AllClkBypReqTrue_A	165663511	138313	0	0
IoClkBypReqFalse_A	165663511	162895545	0	2415
IoClkBypReqTrue_A	165663511	218554	0	0
LcClkBypAckFalse_A	165663511	162988502	0	0
LcClkBypAckTrue_A	165663511	130391	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	162980580	0	0
T1	112264	112071	0	0
T2	475517	474126	0	0
T3	358012	357105	0	0
T4	2193	2077	0	0
T15	1992	1481	0	0
T16	7747	5571	0	0
T17	1093	1078	0	0
T18	1328	1122	0	0
T19	4147	2544	0	0
T20	47581	7407	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	138313	0	0
T2	475517	3145	0	0
T3	358012	3117	0	0
T10	0	2849	0	0
T11	0	859	0	0
T14	0	1031	0	0
T15	1992	475	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T25	2556	309	0	0
T26	1859	0	0	0
T87	0	40	0	0
T88	0	94	0	0
T89	0	282	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	162895545	0	2415
T1	112264	112069	0	3
T2	475517	474024	0	3
T3	358012	356990	0	3
T4	2193	2075	0	3
T15	1992	1532	0	3
T16	7747	5469	0	3
T17	1093	1076	0	3
T18	1328	1120	0	3
T19	4147	2532	0	3
T20	47581	7379	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	218554	0	0
T2	475517	4144	0	0
T3	358012	4244	0	0
T10	0	3322	0	0
T11	0	1302	0	0
T14	0	1685	0	0
T15	1992	422	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T25	2556	0	0	0
T26	1859	0	0	0
T87	0	361	0	0
T88	0	31	0	0
T89	0	620	0	0
T90	0	119	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	162988502	0	0
T1	112264	112071	0	0
T2	475517	474182	0	0
T3	358012	357144	0	0
T4	2193	2077	0	0
T15	1992	1632	0	0
T16	7747	5571	0	0
T17	1093	1078	0	0
T18	1328	1122	0	0
T19	4147	2544	0	0
T20	47581	7407	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	130391	0	0
T2	475517	2580	0	0
T3	358012	2726	0	0
T10	0	2081	0	0
T11	0	827	0	0
T14	0	935	0	0
T15	1992	324	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T25	2556	0	0	0
T26	1859	0	0	0
T87	0	199	0	0
T89	0	319	0	0
T90	0	74	0	0
T91	0	100	0	0