Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1969906668	15647	0	0
TransStop_A	1969906668	8074	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1969906668	15647	0	0
T2	752668	310	0	0
T3	2893724	144	0	0
T4	18272	4	0	0
T10	0	164	0	0
T11	0	269	0	0
T13	0	27	0	0
T14	0	170	0	0
T15	31884	0	0	0
T16	123960	0	0	0
T17	29172	0	0	0
T18	5476	0	0	0
T19	276524	0	0	0
T20	396504	0	0	0
T25	12032	0	0	0
T26	0	4	0	0
T92	0	14	0	0
T93	0	13	0	0
T94	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1969906668	8074	0	0
T2	752668	150	0	0
T3	2893724	62	0	0
T4	18272	4	0	0
T10	0	80	0	0
T11	0	120	0	0
T13	0	12	0	0
T14	0	76	0	0
T15	31884	0	0	0
T16	123960	0	0	0
T17	29172	0	0	0
T18	5476	0	0	0
T19	276524	0	0	0
T20	396504	0	0	0
T25	12032	0	0	0
T26	0	3	0	0
T92	0	9	0	0
T93	0	7	0	0
T94	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492476667	3876	0	0
TransStop_A	492476667	1964	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	3876	0	0
T2	188167	80	0	0
T3	723431	37	0	0
T4	4568	1	0	0
T10	0	35	0	0
T11	0	67	0	0
T13	0	9	0	0
T14	0	40	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T92	0	3	0	0
T93	0	1	0	0
T94	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	1964	0	0
T2	188167	39	0	0
T3	723431	17	0	0
T4	4568	1	0	0
T10	0	15	0	0
T11	0	26	0	0
T13	0	3	0	0
T14	0	19	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492476667	3946	0	0
TransStop_A	492476667	2038	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	3946	0	0
T2	188167	70	0	0
T3	723431	34	0	0
T4	4568	1	0	0
T10	0	45	0	0
T11	0	65	0	0
T13	0	5	0	0
T14	0	42	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	4	0	0
T93	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	2038	0	0
T2	188167	34	0	0
T3	723431	13	0	0
T4	4568	1	0	0
T10	0	22	0	0
T11	0	27	0	0
T13	0	3	0	0
T14	0	19	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	2	0	0
T93	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492476667	3872	0	0
TransStop_A	492476667	2004	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	3872	0	0
T2	188167	83	0	0
T3	723431	36	0	0
T4	4568	1	0	0
T10	0	41	0	0
T11	0	66	0	0
T13	0	6	0	0
T14	0	41	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	2	0	0
T92	0	4	0	0
T93	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	2004	0	0
T2	188167	40	0	0
T3	723431	15	0	0
T4	4568	1	0	0
T10	0	18	0	0
T11	0	34	0	0
T13	0	3	0	0
T14	0	16	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	3	0	0
T93	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	492476667	3953	0	0
TransStop_A	492476667	2068	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	3953	0	0
T2	188167	77	0	0
T3	723431	37	0	0
T4	4568	1	0	0
T10	0	43	0	0
T11	0	71	0	0
T13	0	7	0	0
T14	0	47	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	3	0	0
T93	0	3	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476667	2068	0	0
T2	188167	37	0	0
T3	723431	17	0	0
T4	4568	1	0	0
T10	0	25	0	0
T11	0	33	0	0
T13	0	3	0	0
T14	0	22	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1369	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	3	0	0
T93	0	1	0	0