Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT2,T3,T15 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT2,T3,T15
11CoveredT2,T3,T15 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T15
10CoveredT1,T4,T2
11CoveredT1,T4,T2
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 575034475 575032060 0 0
selKnown1 1385402427 1385400012 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 575034475 575032060 0 0
T1 138758 138755 0 0
T2 2207779 2207779 0 0
T3 856947 856947 0 0
T4 5348 5345 0 0
T15 10795 10792 0 0
T16 32012 32009 0 0
T17 8722 8719 0 0
T18 1543 1540 0 0
T19 69605 69602 0 0
T20 70222 70219 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1385402427 1385400012 0 0
T1 333297 333294 0 0
T2 530154 530151 0 0
T3 2057496 2057496 0 0
T4 13155 13152 0 0
T15 22956 22953 0 0
T16 89247 89244 0 0
T17 21006 21003 0 0
T18 3939 3936 0 0
T19 199089 199086 0 0
T20 285474 285471 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T4,T2
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T4,T2
11CoveredT1,T4,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 230131982 230131177 0 0
selKnown1 461800809 461800004 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 230131982 230131177 0 0
T1 55503 55502 0 0
T2 883367 883367 0 0
T3 342920 342920 0 0
T4 2139 2138 0 0
T15 4675 4674 0 0
T16 12804 12803 0 0
T17 3489 3488 0 0
T18 617 616 0 0
T19 27842 27841 0 0
T20 28088 28087 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 461800809 461800004 0 0
T1 111099 111098 0 0
T2 176718 176717 0 0
T3 685832 685832 0 0
T4 4385 4384 0 0
T15 7652 7651 0 0
T16 29749 29748 0 0
T17 7002 7001 0 0
T18 1313 1312 0 0
T19 66363 66362 0 0
T20 95158 95157 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10CoveredT2,T3,T15 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T4,T2
10CoveredT2,T3,T15
11CoveredT2,T3,T15 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT2,T3,T15
10CoveredT1,T4,T2
11CoveredT1,T4,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 229837147 229836342 0 0
selKnown1 461800809 461800004 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 229837147 229836342 0 0
T1 55503 55502 0 0
T2 882729 882729 0 0
T3 342568 342568 0 0
T4 2139 2138 0 0
T15 3786 3785 0 0
T16 12804 12803 0 0
T17 3489 3488 0 0
T18 617 616 0 0
T19 27842 27841 0 0
T20 28088 28087 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 461800809 461800004 0 0
T1 111099 111098 0 0
T2 176718 176717 0 0
T3 685832 685832 0 0
T4 4385 4384 0 0
T15 7652 7651 0 0
T16 29749 29748 0 0
T17 7002 7001 0 0
T18 1313 1312 0 0
T19 66363 66362 0 0
T20 95158 95157 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T4,T2
01CoveredT1,T4,T2
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T4,T2
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T4,T2
11CoveredT1,T4,T2
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 115065346 115064541 0 0
selKnown1 461800809 461800004 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 115065346 115064541 0 0
T1 27752 27751 0 0
T2 441683 441683 0 0
T3 171459 171459 0 0
T4 1070 1069 0 0
T15 2334 2333 0 0
T16 6404 6403 0 0
T17 1744 1743 0 0
T18 309 308 0 0
T19 13921 13920 0 0
T20 14046 14045 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 461800809 461800004 0 0
T1 111099 111098 0 0
T2 176718 176717 0 0
T3 685832 685832 0 0
T4 4385 4384 0 0
T15 7652 7651 0 0
T16 29749 29748 0 0
T17 7002 7001 0 0
T18 1313 1312 0 0
T19 66363 66362 0 0
T20 95158 95157 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%