Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	165663511	20266334	0	59

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	20266334	0	59
T1	112264	12829	0	1
T2	475517	808339	0	0
T3	358012	483881	0	0
T4	2193	0	0	0
T8	0	4212	0	1
T9	0	37310	0	1
T10	0	42086	0	0
T11	0	110033	0	0
T12	0	7103	0	1
T13	0	11469	0	1
T14	0	708853	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T24	0	0	0	1
T95	0	0	0	1
T96	0	0	0	1
T97	0	0	0	1
T98	0	0	0	1