Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	954491	0	0
SrcPulseCheck_M	2147483647	952013	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	954491
T1	533357	268
T2	3932186	16376
T3	2967494	4977
T4	18632	0
T8	0	92
T9	0	228
T10	0	3354
T11	0	5952
T12	0	144
T15	33974	0
T16	113302	0
T17	27599	0
T18	6169	0
T19	237088	51
T20	340175	130
T21	0	616
T38	6418	0
T39	22272	2
T43	26806	2
T44	33142	2
T45	16560	2
T46	7555	2
T99	0	51
T100	20688	2
T101	17266	1
T102	19192	5
T103	8778	1
T104	12254	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	952013
T1	281023	268
T2	2983625	16379
T3	2451764	4978
T4	7805	0
T8	0	92
T9	0	228
T10	0	3357
T11	0	5211
T12	0	144
T15	10891	0
T16	36974	0
T17	7715	0
T18	3653	0
T19	36796	51
T20	124102	130
T21	0	616
T38	2836	0
T39	8810	2
T43	11448	2
T44	14328	2
T45	7254	2
T46	3235	2
T99	0	51
T100	18470	2
T101	7434	1
T102	17218	5
T103	3520	1
T104	4976	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	464471536	25234	0	0
SrcPulseCheck_M	166626842	25234	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	464471536	25234
T1	111099	20
T2	176718	829
T3	685832	247
T4	4385	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	7652	0
T16	29749	0
T17	7002	0
T18	1313	0
T19	66363	10
T20	95158	26
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	25234
T1	112264	20
T2	475517	829
T3	358012	247
T4	2193	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	10
T20	47581	26
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	464471536	31611	0	0
SrcPulseCheck_M	166626842	31634	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	464471536	31611
T1	111099	20
T2	176718	840
T3	685832	258
T4	4385	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	7652	0
T16	29749	0
T17	7002	0
T18	1313	0
T19	66363	20
T20	95158	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	31634
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	31602	0	0
SrcPulseCheck_M	464471536	31615	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	31602
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	464471536	31615
T1	111099	20
T2	176718	840
T3	685832	258
T4	4385	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	7652	0
T16	29749	0
T17	7002	0
T18	1313	0
T19	66363	20
T20	95158	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	231417290	25234	0	0
SrcPulseCheck_M	166626842	25234	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	231417290	25234
T1	55503	20
T2	883367	829
T3	342920	247
T4	2139	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	4675	0
T16	12804	0
T17	3489	0
T18	617	0
T19	27842	10
T20	28088	26
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	25234
T1	112264	20
T2	475517	829
T3	358012	247
T4	2193	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	10
T20	47581	26
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	231417290	31657	0	0
SrcPulseCheck_M	166626842	31689	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	231417290	31657
T1	55503	20
T2	883367	840
T3	342920	258
T4	2139	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	4675	0
T16	12804	0
T17	3489	0
T18	617	0
T19	27842	20
T20	28088	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	31689
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	31651	0	0
SrcPulseCheck_M	231417290	31660	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	31651
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	231417290	31660
T1	55503	20
T2	883367	840
T3	342920	258
T4	2139	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	4675	0
T16	12804	0
T17	3489	0
T18	617	0
T19	27842	20
T20	28088	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	115708008	25234	0	0
SrcPulseCheck_M	166626842	25234	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	115708008	25234
T1	27752	20
T2	441683	829
T3	171459	247
T4	1070	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	2334	0
T16	6404	0
T17	1744	0
T18	309	0
T19	13921	10
T20	14046	26
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	25234
T1	112264	20
T2	475517	829
T3	358012	247
T4	2193	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	10
T20	47581	26
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	115708008	31646	0	0
SrcPulseCheck_M	166626842	31695	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	115708008	31646
T1	27752	20
T2	441683	840
T3	171459	258
T4	1070	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	2334	0
T16	6404	0
T17	1744	0
T18	309	0
T19	13921	20
T20	14046	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	31695
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	31645	0	0
SrcPulseCheck_M	115708008	31652	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	31645
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	115708008	31652
T1	27752	20
T2	441683	840
T3	171459	258
T4	1070	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	2334	0
T16	6404	0
T17	1744	0
T18	309	0
T19	13921	20
T20	14046	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	495258352	25234	0	0
SrcPulseCheck_M	166626842	25234	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	495258352	25234
T1	115733	20
T2	188167	829
T3	723431	247
T4	4567	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	7971	0
T16	30990	0
T17	7293	0
T18	1368	0
T19	69131	10
T20	99126	26
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	25234
T1	112264	20
T2	475517	829
T3	358012	247
T4	2193	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	10
T20	47581	26
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	495258352	31556	0	0
SrcPulseCheck_M	166626842	31571	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	495258352	31556
T1	115733	20
T2	188167	840
T3	723431	258
T4	4567	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	7971	0
T16	30990	0
T17	7293	0
T18	1368	0
T19	69131	20
T20	99126	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	31571
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	31544	0	0
SrcPulseCheck_M	495258352	31557	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	31544
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	495258352	31557
T1	115733	20
T2	188167	840
T3	723431	258
T4	4567	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	7971	0
T16	30990	0
T17	7293	0
T18	1368	0
T19	69131	20
T20	99126	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	237799235	24815	0	0
SrcPulseCheck_M	166626842	25234	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	237799235	24815
T1	55553	20
T2	903504	829
T3	347540	247
T4	2193	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	3825	0
T16	14875	0
T17	3500	0
T18	657	0
T19	33183	10
T20	47581	20
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	25234
T1	112264	20
T2	475517	829
T3	358012	247
T4	2193	0
T8	0	8
T9	0	20
T10	0	175
T11	0	305
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	10
T20	47581	26
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	237799235	31419	0	0
SrcPulseCheck_M	166626842	31607	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	237799235	31419
T1	55553	20
T2	903504	840
T3	347540	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	3825	0
T16	14875	0
T17	3500	0
T18	657	0
T19	33183	20
T20	47581	51
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	166626842	31607
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	20
T20	47581	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	31282	0	0
SrcPulseCheck_M	237799235	31459	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	31282
T1	112264	20
T2	475517	840
T3	358012	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	1992	0
T16	7747	0
T17	1093	0
T18	1328	0
T19	4147	19
T20	47581	51
T21	0	24

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	237799235	31459
T1	55553	20
T2	903504	840
T3	347540	258
T4	2193	0
T8	0	8
T9	0	20
T10	0	181
T11	0	315
T15	3825	0
T16	14875	0
T17	3500	0
T18	657	0
T19	33183	20
T20	47581	52
T21	0	24

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T40,T42
1	0	Covered	T39,T40,T42
1	1	Covered	T39,T42,T100

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T40,T42
1	0	Covered	T39,T42,T100
1	1	Covered	T39,T40,T42

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	44	0	0
SrcPulseCheck_M	464471536	44	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	44
T39	11136	3
T40	7734	1
T42	4799	2
T43	13403	2
T44	16571	1
T100	10344	4
T101	8633	2
T102	9596	2
T105	5156	1
T106	5435	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	464471536	44
T39	10907	3
T40	7734	1
T42	9213	2
T43	12996	2
T44	15907	1
T100	20687	4
T101	8370	2
T102	19601	2
T105	82509	1
T106	20870	2

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T40,T42
1	0	Covered	T39,T40,T42
1	1	Covered	T42,T102,T107

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T40,T42
1	0	Covered	T42,T102,T107
1	1	Covered	T39,T40,T42

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	38	0	0
SrcPulseCheck_M	464471536	38	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	38
T39	11136	1
T40	7734	1
T42	4799	3
T43	13403	2
T44	16571	1
T100	10344	3
T101	8633	1
T102	9596	2
T105	5156	1
T106	5435	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	464471536	38
T39	10907	1
T40	7734	1
T42	9213	3
T43	12996	2
T44	15907	1
T100	20687	3
T101	8370	1
T102	19601	2
T105	82509	1
T106	20870	2

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T43,T44
1	0	Covered	T39,T43,T44
1	1	Covered	T43,T100,T102

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T43,T44
1	0	Covered	T43,T100,T102
1	1	Covered	T39,T43,T44

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	38	0	0
SrcPulseCheck_M	231417290	38	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	38
T39	11136	2
T43	13403	2
T44	16571	2
T45	8280	2
T46	7555	2
T100	10344	2
T101	8633	1
T102	9596	5
T103	8778	1
T104	12254	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	231417290	38
T39	4405	2
T43	5724	2
T44	7164	2
T45	3627	2
T46	3235	2
T100	9235	2
T101	3717	1
T102	8609	5
T103	3520	1
T104	4976	3

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T39,T43
1	0	Covered	T38,T39,T43
1	1	Covered	T102,T108,T109

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T39,T43
1	0	Covered	T102,T108,T109
1	1	Covered	T38,T39,T43

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	30	0	0
SrcPulseCheck_M	231417290	30	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	30
T38	6418	1
T39	11136	1
T41	9861	2
T43	13403	1
T44	16571	2
T45	8280	1
T100	10344	1
T101	8633	1
T102	9596	2
T106	5435	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	231417290	30
T38	2836	1
T39	4405	1
T41	93644	2
T43	5724	1
T44	7164	2
T45	3627	1
T100	9235	1
T101	3717	1
T102	8609	2
T106	9564	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T40,T42
1	0	Covered	T38,T40,T42
1	1	Covered	T40,T42,T110

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T40,T42
1	0	Covered	T40,T42,T110
1	1	Covered	T38,T40,T42

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	36	0	0
SrcPulseCheck_M	115708008	36	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	36
T38	6418	1
T40	7734	3
T41	9861	1
T42	4799	2
T100	10344	2
T102	9596	1
T104	12254	1
T111	8808	1
T112	6016	1
T113	4698	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	115708008	36
T38	1419	1
T40	1592	3
T41	46823	1
T42	2062	2
T100	4616	2
T102	4305	1
T104	2487	1
T111	2558	1
T112	2712	1
T113	4440	1

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T40,T42
1	0	Covered	T38,T40,T42
1	1	Covered	T40,T114

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T40,T42
1	0	Covered	T40,T114
1	1	Covered	T38,T40,T42

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	37	0	0
SrcPulseCheck_M	115708008	37	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	37
T38	6418	1
T40	7734	6
T42	4799	1
T100	10344	2
T104	12254	2
T107	4402	1
T111	8808	1
T112	6016	1
T113	4698	1
T115	11624	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	115708008	37
T38	1419	1
T40	1592	6
T42	2062	1
T100	4616	2
T104	2487	2
T107	1987	1
T111	2558	1
T112	2712	1
T113	4440	1
T115	2320	2

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T40,T43
1	0	Covered	T39,T40,T43
1	1	Covered	T40

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T39,T40,T43
1	0	Covered	T40
1	1	Covered	T39,T40,T43

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	28	0	0
SrcPulseCheck_M	495258352	28	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	28
T39	11136	1
T40	7734	4
T41	9861	1
T43	13403	2
T44	16571	1
T45	8280	1
T46	7555	1
T103	8778	1
T105	5156	1
T106	5435	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	495258352	28
T39	11362	1
T40	8057	4
T41	197227	1
T43	13539	2
T44	16571	1
T45	8626	1
T46	7788	1
T103	8778	1
T105	85951	1
T106	21741	1

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T40,T43
1	0	Covered	T38,T40,T43
1	1	Covered	T40,T116

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T38,T40,T43
1	0	Covered	T40,T116
1	1	Covered	T38,T40,T43

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	31	0	0
SrcPulseCheck_M	495258352	31	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	31
T38	6418	1
T40	7734	3
T41	9861	2
T43	13403	2
T45	8280	1
T46	7555	1
T100	10344	1
T103	8778	2
T105	5156	1
T106	5435	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	495258352	31
T38	6828	1
T40	8057	3
T41	197227	2
T43	13539	2
T45	8626	1
T46	7788	1
T100	21550	1
T103	8778	2
T105	85951	1
T106	21741	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T40,T44,T41
1	0	Covered	T40,T44,T41
1	1	Covered	T106,T115,T117

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T40,T44,T41
1	0	Covered	T106,T115,T117
1	1	Covered	T40,T44,T41

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	26	0	0
SrcPulseCheck_M	237799235	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	26
T40	7734	1
T41	9861	2
T44	16571	1
T100	10344	1
T103	8778	1
T106	5435	3
T111	8808	1
T113	4698	1
T115	11624	3
T118	16245	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	237799235	26
T40	3867	1
T41	94670	2
T44	7954	1
T100	10344	1
T103	4213	1
T106	10436	3
T111	5872	1
T113	9397	1
T115	5579	3
T118	7956	1

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T40,T44,T41
1	0	Covered	T40,T44,T41
1	1	Covered	T44,T104,T115

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T40,T44,T41
1	0	Covered	T44,T104,T115
1	1	Covered	T40,T44,T41

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo_err_update_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	166626842	26	0	0
SrcPulseCheck_M	237799235	26	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	166626842	26
T40	7734	1
T41	9861	3
T44	16571	2
T100	10344	1
T103	8778	1
T104	12254	2
T106	5435	2
T111	8808	1
T115	11624	3
T118	16245	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	237799235	26
T40	3867	1
T41	94670	3
T44	7954	2
T100	10344	1
T103	4213	1
T104	5882	2
T106	10436	2
T111	5872	1
T115	5579	3
T118	7956	1

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_io_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	461800809	95167	0	0
SrcPulseCheck_M	14677278	94176	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	461800809	95167
T1	111099	52
T2	176718	3339
T3	685832	1017
T4	4385	0
T8	0	17
T9	0	42
T10	0	691
T11	0	1180
T12	0	36
T15	7652	0
T16	29749	0
T17	7002	0
T18	1313	0
T19	66363	1
T20	95158	0
T21	0	118

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14677278	94176
T1	248	52
T2	287102	3340
T3	348160	1017
T4	320	0
T8	0	17
T9	0	42
T10	0	692
T11	0	933
T12	0	36
T15	558	0
T16	2169	0
T17	510	0
T18	95	0
T19	165	1
T20	213	0
T21	0	118

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	230131982	94525	0	0
SrcPulseCheck_M	14677278	93535	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	230131982	94525
T1	55503	52
T2	883367	3310
T3	342920	1009
T4	2139	0
T8	0	17
T9	0	42
T10	0	683
T11	0	1180
T12	0	36
T15	4675	0
T16	12804	0
T17	3489	0
T18	617	0
T19	27842	0
T20	28088	0
T21	0	118
T99	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14677278	93535
T1	248	52
T2	287102	3311
T3	348160	1009
T4	320	0
T8	0	17
T9	0	42
T10	0	684
T11	0	933
T12	0	36
T15	558	0
T16	2169	0
T17	510	0
T18	95	0
T19	165	0
T20	213	0
T21	0	118
T99	0	17

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	115065346	93545	0	0
SrcPulseCheck_M	14677278	92555	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	115065346	93545
T1	27752	52
T2	441683	3261
T3	171459	1003
T4	1070	0
T8	0	17
T9	0	42
T10	0	643
T11	0	1180
T12	0	36
T15	2334	0
T16	6404	0
T17	1744	0
T18	309	0
T19	13921	0
T20	14046	0
T21	0	118
T99	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	14677278	92555
T1	248	52
T2	287102	3262
T3	348160	1003
T4	320	0
T8	0	17
T9	0	42
T10	0	644
T11	0	933
T12	0	36
T15	558	0
T16	2169	0
T17	510	0
T18	95	0
T19	165	0
T20	213	0
T21	0	118
T99	0	17

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_main_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	492476232	115133	0	0
SrcPulseCheck_M	15395170	115105	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	492476232	115133
T1	115733	52
T2	188167	3957
T3	723431	1185
T4	4567	0
T8	0	17
T9	0	42
T10	0	800
T11	0	1477
T12	0	36
T15	7971	0
T16	30990	0
T17	7293	0
T18	1368	0
T19	69131	0
T20	99126	0
T21	0	190
T99	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15395170	115105
T1	248	52
T2	287918	3957
T3	348340	1186
T4	320	0
T8	0	17
T9	0	42
T10	0	800
T11	0	1477
T12	0	36
T15	558	0
T16	2169	0
T17	510	0
T18	95	0
T19	165	0
T20	213	0
T21	0	190
T99	0	17

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T2
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T2
0	Covered	T1,T4,T2

Assert Coverage for Instance : tb.dut.u_usb_meas.u_meas.u_sync_ref

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	236463845	114423	0	0
SrcPulseCheck_M	15295179	113999	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	236463845	114423
T1	55553	52
T2	903504	3894
T3	347540	1177
T4	2193	0
T8	0	17
T9	0	42
T10	0	742
T11	0	1489
T12	0	36
T15	3825	0
T16	14875	0
T17	3500	0
T18	657	0
T19	33183	0
T20	47581	0
T21	0	154
T99	0	17

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	15295179	113999
T1	248	52
T2	287930	3894
T3	348352	1177
T4	320	0
T8	0	17
T9	0	42
T10	0	742
T11	0	1489
T12	0	36
T15	558	0
T16	2169	0
T17	510	0
T18	95	0
T19	165	0
T20	213	0
T21	0	154
T99	0	17

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.43	100.00	85.71			100.00	100.00	u_io_meas_ctrl_en_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.92	100.00	91.67			100.00	100.00	u_io_meas_ctrl_shadowed_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb