Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	166626842	5285554	0	0
clk_enables_rd_A	166626842	51501	0	0
clk_hints_rd_A	166626842	45525	0	0
extclk_ctrl_rd_A	166626842	55521	0	0
extclk_ctrl_regwen_rd_A	166626842	43990	0	0
jitter_enable_rd_A	166626842	58217	0	0
jitter_regwen_rd_A	166626842	48819	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166626842	5285554	0	0
T2	475517	163956	0	0
T3	358012	103763	0	0
T10	0	54223	0	0
T11	0	84801	0	0
T14	0	121561	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T22	0	87129	0	0
T23	0	111608	0	0
T25	2556	0	0	0
T26	1859	0	0	0
T47	0	58648	0	0
T48	0	170036	0	0
T49	0	83928	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166626842	51501	0	0
T2	475517	0	0	0
T3	358012	4232	0	0
T4	2193	9	0	0
T10	0	2184	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T22	0	3416	0	0
T23	0	4465	0	0
T25	2556	0	0	0
T29	0	1	0	0
T50	0	7	0	0
T53	0	8	0	0
T119	0	2	0	0
T120	0	6	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166626842	45525	0	0
T3	358012	3918	0	0
T10	0	1931	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T22	0	2875	0	0
T23	0	3877	0	0
T25	2556	0	0	0
T26	1859	0	0	0
T27	1506	0	0	0
T29	0	2	0	0
T49	0	2912	0	0
T50	0	11	0	0
T53	0	12	0	0
T119	0	7	0	0
T120	0	1	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166626842	55521	0	0
T3	358012	4668	0	0
T10	0	2219	0	0
T15	1992	43	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	58	0	0
T22	0	3854	0	0
T23	0	4783	0	0
T25	2556	49	0	0
T26	1859	0	0	0
T27	1506	0	0	0
T29	0	159	0	0
T50	0	140	0	0
T119	0	17	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166626842	43990	0	0
T3	358012	3680	0	0
T10	0	1657	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	45	0	0
T22	0	3003	0	0
T23	0	3870	0	0
T25	2556	0	0	0
T26	1859	0	0	0
T27	1506	0	0	0
T49	0	2953	0	0
T86	0	45	0	0
T121	0	46	0	0
T122	0	12	0	0
T123	0	4	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166626842	58217	0	0
T2	475517	0	0	0
T3	358012	4914	0	0
T4	2193	106	0	0
T10	0	2521	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T22	0	4001	0	0
T23	0	4655	0	0
T25	2556	0	0	0
T29	0	101	0	0
T50	0	324	0	0
T53	0	349	0	0
T119	0	226	0	0
T120	0	118	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166626842	48819	0	0
T3	358012	4190	0	0
T10	0	1999	0	0
T15	1992	0	0	0
T16	7747	0	0	0
T17	1093	0	0	0
T18	1328	0	0	0
T19	4147	0	0	0
T20	47581	0	0	0
T22	0	3383	0	0
T23	0	4568	0	0
T25	2556	0	0	0
T26	1859	0	0	0
T27	1506	0	0	0
T49	0	3107	0	0
T124	0	2739	0	0
T125	0	3620	0	0
T126	0	3490	0	0
T127	0	5830	0	0
T128	0	3290	0	0