Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T3,T25
1	1	Covered	T2,T3,T15

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	461801242	4551	0	0
g_div2.Div2Whole_A	461801242	5385	0	0
g_div4.Div4Stepped_A	230132418	4455	0	0
g_div4.Div4Whole_A	230132418	5121	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461801242	4551	0	0
T2	176718	90	0	0
T3	685832	68	0	0
T10	0	52	0	0
T11	0	32	0	0
T15	7653	11	0	0
T16	29749	0	0	0
T17	7002	0	0	0
T18	1314	0	0	0
T19	66364	0	0	0
T20	95159	0	0	0
T25	2888	7	0	0
T26	1803	0	0	0
T87	0	7	0	0
T88	0	6	0	0
T89	0	8	0	0
T90	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461801242	5385	0	0
T2	176718	95	0	0
T3	685832	74	0	0
T10	0	52	0	0
T11	0	46	0	0
T15	7653	11	0	0
T16	29749	0	0	0
T17	7002	0	0	0
T18	1314	0	0	0
T19	66364	0	0	0
T20	95159	0	0	0
T25	2888	14	0	0
T26	1803	0	0	0
T87	0	10	0	0
T88	0	7	0	0
T89	0	16	0	0
T90	0	4	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230132418	4455	0	0
T2	883368	90	0	0
T3	342920	68	0	0
T10	0	52	0	0
T11	0	29	0	0
T15	4676	11	0	0
T16	12804	0	0	0
T17	3489	0	0	0
T18	618	0	0	0
T19	27842	0	0	0
T20	28089	0	0	0
T25	1557	6	0	0
T26	882	0	0	0
T87	0	6	0	0
T88	0	6	0	0
T89	0	8	0	0
T90	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230132418	5121	0	0
T2	883368	95	0	0
T3	342920	74	0	0
T10	0	52	0	0
T11	0	37	0	0
T15	4676	11	0	0
T16	12804	0	0	0
T17	3489	0	0	0
T18	618	0	0	0
T19	27842	0	0	0
T20	28089	0	0	0
T25	1557	12	0	0
T26	882	0	0	0
T87	0	8	0	0
T88	0	7	0	0
T89	0	16	0	0
T90	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T3,T25
1	1	Covered	T2,T3,T15

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	461801242	4551	0	0
g_div2.Div2Whole_A	461801242	5385	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461801242	4551	0	0
T2	176718	90	0	0
T3	685832	68	0	0
T10	0	52	0	0
T11	0	32	0	0
T15	7653	11	0	0
T16	29749	0	0	0
T17	7002	0	0	0
T18	1314	0	0	0
T19	66364	0	0	0
T20	95159	0	0	0
T25	2888	7	0	0
T26	1803	0	0	0
T87	0	7	0	0
T88	0	6	0	0
T89	0	8	0	0
T90	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461801242	5385	0	0
T2	176718	95	0	0
T3	685832	74	0	0
T10	0	52	0	0
T11	0	46	0	0
T15	7653	11	0	0
T16	29749	0	0	0
T17	7002	0	0	0
T18	1314	0	0	0
T19	66364	0	0	0
T20	95159	0	0	0
T25	2888	14	0	0
T26	1803	0	0	0
T87	0	10	0	0
T88	0	7	0	0
T89	0	16	0	0
T90	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T2
1	0	Covered	T2,T3,T25
1	1	Covered	T2,T3,T15

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	230132418	4455	0	0
g_div4.Div4Whole_A	230132418	5121	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230132418	4455	0	0
T2	883368	90	0	0
T3	342920	68	0	0
T10	0	52	0	0
T11	0	29	0	0
T15	4676	11	0	0
T16	12804	0	0	0
T17	3489	0	0	0
T18	618	0	0	0
T19	27842	0	0	0
T20	28089	0	0	0
T25	1557	6	0	0
T26	882	0	0	0
T87	0	6	0	0
T88	0	6	0	0
T89	0	8	0	0
T90	0	1	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230132418	5121	0	0
T2	883368	95	0	0
T3	342920	74	0	0
T10	0	52	0	0
T11	0	37	0	0
T15	4676	11	0	0
T16	12804	0	0	0
T17	3489	0	0	0
T18	618	0	0	0
T19	27842	0	0	0
T20	28089	0	0	0
T25	1557	12	0	0
T26	882	0	0	0
T87	0	8	0	0
T88	0	7	0	0
T89	0	16	0	0
T90	0	3	0	0