Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
IoStatusFall_A	165663511	143	0	0
IoStatusRise_A	165663511	143	0	0
MainStatusFall_A	165663511	150	0	0
MainStatusRise_A	165663511	150	0	0
UsbStatusFall_A	165663511	133	0	0
UsbStatusRise_A	165663511	133	0	0

IoStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	143	0	0
T31	748	2	0	0
T32	1422	3	0	0
T33	989	1	0	0
T85	244272	0	0	0
T120	1898	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	878	0	0	0
T137	2143	0	0	0
T138	1366	0	0	0
T139	2108	0	0	0
T140	2027	0	0	0

IoStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	143	0	0
T31	748	2	0	0
T32	1422	3	0	0
T33	989	1	0	0
T85	244272	0	0	0
T120	1898	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	878	0	0	0
T137	2143	0	0	0
T138	1366	0	0	0
T139	2108	0	0	0
T140	2027	0	0	0

MainStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	150	0	0
T31	748	1	0	0
T32	1422	3	0	0
T33	989	1	0	0
T85	244272	0	0	0
T120	1898	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	5	0	0
T132	0	3	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	878	0	0	0
T137	2143	0	0	0
T138	1366	0	0	0
T139	2108	0	0	0
T140	2027	0	0	0

MainStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	150	0	0
T31	748	1	0	0
T32	1422	3	0	0
T33	989	1	0	0
T85	244272	0	0	0
T120	1898	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	5	0	0
T132	0	3	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	878	0	0	0
T137	2143	0	0	0
T138	1366	0	0	0
T139	2108	0	0	0
T140	2027	0	0	0

UsbStatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	133	0	0
T31	748	2	0	0
T32	1422	2	0	0
T33	989	1	0	0
T85	244272	0	0	0
T120	1898	0	0	0
T129	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T135	0	3	0	0
T136	878	0	0	0
T137	2143	0	0	0
T138	1366	0	0	0
T139	2108	0	0	0
T140	2027	0	0	0
T141	0	6	0	0
T142	0	3	0	0

UsbStatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165663511	133	0	0
T31	748	2	0	0
T32	1422	2	0	0
T33	989	1	0	0
T85	244272	0	0	0
T120	1898	0	0	0
T129	0	2	0	0
T131	0	2	0	0
T132	0	2	0	0
T133	0	2	0	0
T135	0	3	0	0
T136	878	0	0	0
T137	2143	0	0	0
T138	1366	0	0	0
T139	2108	0	0	0
T140	2027	0	0	0
T141	0	6	0	0
T142	0	3	0	0