Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47784	0	0
CgEnOn_A	2147483647	38198	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47784	0	0
T1	194354	3	0	0
T2	1689935	525	0	0
T3	1923642	229	0	0
T4	12161	7	0	0
T15	22632	3	0	0
T16	79947	153	0	0
T17	19528	3	0	0
T18	3607	6	0	0
T19	177257	18	0	0
T20	236418	42	0	0
T25	3008	0	0	0
T31	6988	10	0	0
T32	2746	15	0	0
T33	4136	5	0	0
T49	0	5	0	0
T85	2137666	0	0	0
T92	0	3	0	0
T120	16919	0	0	0
T129	0	10	0	0
T130	0	5	0	0
T131	0	10	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	0	5	0	0
T136	14508	0	0	0
T137	4599	0	0	0
T138	13201	0	0	0
T139	18949	0	0	0
T140	4396	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38198	0	0
T2	3157940	273	0	0
T3	4441475	108	0	0
T4	28055	2	0	0
T10	0	192	0	0
T11	0	158	0	0
T13	0	101	0	0
T14	0	120	0	0
T15	50370	0	0	0
T16	187792	0	0	0
T17	44907	0	0	0
T18	8368	2	0	0
T19	417833	0	0	0
T20	581377	0	0	0
T22	0	60	0	0
T25	18695	0	0	0
T31	13488	10	0	0
T32	5452	15	0	0
T33	7986	5	0	0
T49	0	4	0	0
T85	2355904	0	0	0
T120	32739	0	0	0
T129	0	10	0	0
T130	0	5	0	0
T131	0	10	0	0
T132	0	20	0	0
T133	0	10	0	0
T134	0	5	0	0
T135	0	3	0	0
T136	28018	0	0	0
T137	8885	0	0	0
T138	24591	0	0	0
T139	36523	0	0	0
T140	8532	0	0	0
T143	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Unreachable
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	230131982	153	0	0
CgEnOn_A	230131982	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230131982	153	0	0
T31	1526	2	0	0
T32	583	3	0	0
T33	905	1	0	0
T49	0	1	0	0
T85	475231	0	0	0
T120	3730	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	3209	0	0	0
T137	1017	0	0	0
T138	3094	0	0	0
T139	4205	0	0	0
T140	965	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230131982	152	0	0
T31	1526	2	0	0
T32	583	3	0	0
T33	905	1	0	0
T49	0	1	0	0
T85	475231	0	0	0
T120	3730	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	3209	0	0	0
T137	1017	0	0	0
T138	3094	0	0	0
T139	4205	0	0	0
T140	965	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Unreachable
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115065346	153	0	0
CgEnOn_A	115065346	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	153	0	0
T31	763	2	0	0
T32	292	3	0	0
T33	452	1	0	0
T49	0	1	0	0
T85	237612	0	0	0
T120	1865	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	1605	0	0	0
T137	508	0	0	0
T138	1547	0	0	0
T139	2103	0	0	0
T140	482	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	152	0	0
T31	763	2	0	0
T32	292	3	0	0
T33	452	1	0	0
T49	0	1	0	0
T85	237612	0	0	0
T120	1865	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	1605	0	0	0
T137	508	0	0	0
T138	1547	0	0	0
T139	2103	0	0	0
T140	482	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Unreachable
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461800809	153	0	0
CgEnOn_A	461800809	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461800809	153	0	0
T31	3173	2	0	0
T32	1287	3	0	0
T33	1875	1	0	0
T49	0	1	0	0
T85	949599	0	0	0
T120	7594	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	6484	0	0	0
T137	2058	0	0	0
T138	5466	0	0	0
T139	8435	0	0	0
T140	1985	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461800809	145	0	0
T31	3173	2	0	0
T32	1287	3	0	0
T33	1875	1	0	0
T85	949599	0	0	0
T120	7594	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	6484	0	0	0
T137	2058	0	0	0
T138	5466	0	0	0
T139	8435	0	0	0
T140	1985	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Unreachable
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492476232	151	0	0
CgEnOn_A	492476232	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	151	0	0
T31	3250	1	0	0
T32	1353	3	0	0
T33	1925	1	0	0
T48	0	1	0	0
T85	109119	0	0	0
T120	7910	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	5	0	0
T132	0	3	0	0
T133	0	4	0	0
T134	0	1	0	0
T136	6755	0	0	0
T137	2143	0	0	0
T138	5695	0	0	0
T139	8787	0	0	0
T140	2068	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	150	0	0
T31	3250	1	0	0
T32	1353	3	0	0
T33	1925	1	0	0
T85	109119	0	0	0
T120	7910	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	5	0	0
T132	0	3	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	6755	0	0	0
T137	2143	0	0	0
T138	5695	0	0	0
T139	8787	0	0	0
T140	2068	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Unreachable
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115065346	153	0	0
CgEnOn_A	115065346	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	153	0	0
T31	763	2	0	0
T32	292	3	0	0
T33	452	1	0	0
T49	0	1	0	0
T85	237612	0	0	0
T120	1865	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	1605	0	0	0
T137	508	0	0	0
T138	1547	0	0	0
T139	2103	0	0	0
T140	482	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	152	0	0
T31	763	2	0	0
T32	292	3	0	0
T33	452	1	0	0
T49	0	1	0	0
T85	237612	0	0	0
T120	1865	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	1605	0	0	0
T137	508	0	0	0
T138	1547	0	0	0
T139	2103	0	0	0
T140	482	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Unreachable
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492476232	151	0	0
CgEnOn_A	492476232	150	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	151	0	0
T31	3250	1	0	0
T32	1353	3	0	0
T33	1925	1	0	0
T48	0	1	0	0
T85	109119	0	0	0
T120	7910	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	5	0	0
T132	0	3	0	0
T133	0	4	0	0
T134	0	1	0	0
T136	6755	0	0	0
T137	2143	0	0	0
T138	5695	0	0	0
T139	8787	0	0	0
T140	2068	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	150	0	0
T31	3250	1	0	0
T32	1353	3	0	0
T33	1925	1	0	0
T85	109119	0	0	0
T120	7910	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	5	0	0
T132	0	3	0	0
T133	0	4	0	0
T134	0	1	0	0
T135	0	3	0	0
T136	6755	0	0	0
T137	2143	0	0	0
T138	5695	0	0	0
T139	8787	0	0	0
T140	2068	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Unreachable
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115065346	153	0	0
CgEnOn_A	115065346	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	153	0	0
T31	763	2	0	0
T32	292	3	0	0
T33	452	1	0	0
T49	0	1	0	0
T85	237612	0	0	0
T120	1865	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	1605	0	0	0
T137	508	0	0	0
T138	1547	0	0	0
T139	2103	0	0	0
T140	482	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	152	0	0
T31	763	2	0	0
T32	292	3	0	0
T33	452	1	0	0
T49	0	1	0	0
T85	237612	0	0	0
T120	1865	0	0	0
T129	0	2	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	4	0	0
T133	0	2	0	0
T134	0	1	0	0
T136	1605	0	0	0
T137	508	0	0	0
T138	1547	0	0	0
T139	2103	0	0	0
T140	482	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	230131982	7635	0	0
CgEnOn_A	230131982	5247	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230131982	7635	0	0
T1	55503	1	0	0
T2	883367	144	0	0
T3	342920	65	0	0
T4	2139	2	0	0
T15	4675	1	0	0
T16	12804	51	0	0
T17	3489	1	0	0
T18	617	2	0	0
T19	27842	6	0	0
T20	28088	14	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230131982	5247	0	0
T2	883367	133	0	0
T3	342920	54	0	0
T4	2139	1	0	0
T10	0	95	0	0
T11	0	78	0	0
T13	0	48	0	0
T14	0	59	0	0
T15	4675	0	0	0
T16	12804	0	0	0
T17	3489	0	0	0
T18	617	1	0	0
T19	27842	0	0	0
T20	28088	0	0	0
T22	0	30	0	0
T25	1557	0	0	0
T143	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	115065346	7581	0	0
CgEnOn_A	115065346	5193	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	7581	0	0
T1	27752	1	0	0
T2	441683	151	0	0
T3	171459	65	0	0
T4	1070	2	0	0
T15	2334	1	0	0
T16	6404	51	0	0
T17	1744	1	0	0
T18	309	2	0	0
T19	13921	6	0	0
T20	14046	14	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065346	5193	0	0
T2	441683	140	0	0
T3	171459	54	0	0
T4	1070	1	0	0
T10	0	97	0	0
T11	0	80	0	0
T13	0	53	0	0
T14	0	61	0	0
T15	2334	0	0	0
T16	6404	0	0	0
T17	1744	0	0	0
T18	309	1	0	0
T19	13921	0	0	0
T20	14046	0	0	0
T22	0	30	0	0
T25	775	0	0	0
T143	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	461800809	7648	0	0
CgEnOn_A	461800809	5253	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461800809	7648	0	0
T1	111099	1	0	0
T2	176718	150	0	0
T3	685832	62	0	0
T4	4385	2	0	0
T15	7652	1	0	0
T16	29749	51	0	0
T17	7002	1	0	0
T18	1313	2	0	0
T19	66363	6	0	0
T20	95158	14	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461800809	5253	0	0
T2	176718	139	0	0
T3	685832	51	0	0
T4	4385	1	0	0
T10	0	91	0	0
T11	0	80	0	0
T13	0	50	0	0
T14	0	65	0	0
T15	7652	0	0	0
T16	29749	0	0	0
T17	7002	0	0	0
T18	1313	1	0	0
T19	66363	0	0	0
T20	95158	0	0	0
T22	0	29	0	0
T25	2888	0	0	0
T143	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T31,T32,T33
1	0	Covered	T1,T4,T2
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	236463845	7602	0	0
CgEnOn_A	236463845	5205	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236463845	7602	0	0
T1	55553	1	0	0
T2	903504	149	0	0
T3	347540	66	0	0
T4	2193	2	0	0
T15	3825	1	0	0
T16	14875	51	0	0
T17	3500	1	0	0
T18	657	2	0	0
T19	33183	6	0	0
T20	47581	14	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236463845	5205	0	0
T2	903504	138	0	0
T3	347540	55	0	0
T4	2193	1	0	0
T10	0	95	0	0
T11	0	86	0	0
T13	0	51	0	0
T14	0	60	0	0
T15	3825	0	0	0
T16	14875	0	0	0
T17	3500	0	0	0
T18	657	1	0	0
T19	33183	0	0	0
T20	47581	0	0	0
T22	0	32	0	0
T25	1443	0	0	0
T143	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T4,T2,T3
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492476232	4027	0	0
CgEnOn_A	492476232	4026	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4027	0	0
T2	188167	80	0	0
T3	723431	37	0	0
T4	4567	1	0	0
T10	0	35	0	0
T11	0	67	0	0
T13	0	9	0	0
T14	0	40	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T92	0	3	0	0
T93	0	1	0	0
T94	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4026	0	0
T2	188167	80	0	0
T3	723431	37	0	0
T4	4567	1	0	0
T10	0	35	0	0
T11	0	67	0	0
T13	0	9	0	0
T14	0	40	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T92	0	3	0	0
T93	0	1	0	0
T94	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T4,T2,T3
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492476232	4097	0	0
CgEnOn_A	492476232	4096	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4097	0	0
T2	188167	70	0	0
T3	723431	34	0	0
T4	4567	1	0	0
T10	0	45	0	0
T11	0	65	0	0
T13	0	5	0	0
T14	0	42	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	4	0	0
T93	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4096	0	0
T2	188167	70	0	0
T3	723431	34	0	0
T4	4567	1	0	0
T10	0	45	0	0
T11	0	65	0	0
T13	0	5	0	0
T14	0	42	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	4	0	0
T93	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T4,T2,T3
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492476232	4023	0	0
CgEnOn_A	492476232	4022	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4023	0	0
T2	188167	83	0	0
T3	723431	36	0	0
T4	4567	1	0	0
T10	0	41	0	0
T11	0	66	0	0
T13	0	6	0	0
T14	0	41	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	2	0	0
T92	0	4	0	0
T93	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4022	0	0
T2	188167	83	0	0
T3	723431	36	0	0
T4	4567	1	0	0
T10	0	41	0	0
T11	0	66	0	0
T13	0	6	0	0
T14	0	41	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	2	0	0
T92	0	4	0	0
T93	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T16
1	0	Covered	T4,T2,T3
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	492476232	4104	0	0
CgEnOn_A	492476232	4103	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4104	0	0
T2	188167	77	0	0
T3	723431	37	0	0
T4	4567	1	0	0
T10	0	43	0	0
T11	0	71	0	0
T13	0	7	0	0
T14	0	47	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	3	0	0
T93	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	492476232	4103	0	0
T2	188167	77	0	0
T3	723431	37	0	0
T4	4567	1	0	0
T10	0	43	0	0
T11	0	71	0	0
T13	0	7	0	0
T14	0	47	0	0
T15	7971	0	0	0
T16	30990	0	0	0
T17	7293	0	0	0
T18	1368	0	0	0
T19	69131	0	0	0
T20	99126	0	0	0
T25	3008	0	0	0
T26	0	1	0	0
T92	0	3	0	0
T93	0	3	0	0