Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T3
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T4,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T4,T2

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1043463671	13454	0	0
GateOpen_A	1043463671	13454	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043463671	13454	0	0
T2	2405273	318	0	0
T3	1547751	140	0	0
T4	9788	4	0	0
T10	0	221	0	0
T11	0	185	0	0
T13	0	136	0	0
T14	0	132	0	0
T15	18490	0	0	0
T16	63833	0	0	0
T17	15737	0	0	0
T18	2899	0	0	0
T19	141310	0	0	0
T20	184875	0	0	0
T22	0	57	0	0
T25	6664	0	0	0
T50	0	88	0	0
T143	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1043463671	13454	0	0
T2	2405273	318	0	0
T3	1547751	140	0	0
T4	9788	4	0	0
T10	0	221	0	0
T11	0	185	0	0
T13	0	136	0	0
T14	0	132	0	0
T15	18490	0	0	0
T16	63833	0	0	0
T17	15737	0	0	0
T18	2899	0	0	0
T19	141310	0	0	0
T20	184875	0	0	0
T22	0	57	0	0
T25	6664	0	0	0
T50	0	88	0	0
T143	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T3
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T4,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	115065744	3323	0	0
GateOpen_A	115065744	3323	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065744	3323	0	0
T2	441683	79	0	0
T3	171459	37	0	0
T4	1070	1	0	0
T10	0	57	0	0
T11	0	46	0	0
T13	0	34	0	0
T14	0	31	0	0
T15	2335	0	0	0
T16	6404	0	0	0
T17	1745	0	0	0
T18	309	0	0	0
T19	13921	0	0	0
T20	14046	0	0	0
T22	0	14	0	0
T25	775	0	0	0
T50	0	20	0	0
T143	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115065744	3323	0	0
T2	441683	79	0	0
T3	171459	37	0	0
T4	1070	1	0	0
T10	0	57	0	0
T11	0	46	0	0
T13	0	34	0	0
T14	0	31	0	0
T15	2335	0	0	0
T16	6404	0	0	0
T17	1745	0	0	0
T18	309	0	0	0
T19	13921	0	0	0
T20	14046	0	0	0
T22	0	14	0	0
T25	775	0	0	0
T50	0	20	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T3
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T4,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	230132418	3364	0	0
GateOpen_A	230132418	3364	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230132418	3364	0	0
T2	883368	79	0	0
T3	342920	35	0	0
T4	2140	1	0	0
T10	0	54	0	0
T11	0	43	0	0
T13	0	34	0	0
T14	0	33	0	0
T15	4676	0	0	0
T16	12804	0	0	0
T17	3489	0	0	0
T18	618	0	0	0
T19	27842	0	0	0
T20	28089	0	0	0
T22	0	14	0	0
T25	1557	0	0	0
T50	0	19	0	0
T143	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230132418	3364	0	0
T2	883368	79	0	0
T3	342920	35	0	0
T4	2140	1	0	0
T10	0	54	0	0
T11	0	43	0	0
T13	0	34	0	0
T14	0	33	0	0
T15	4676	0	0	0
T16	12804	0	0	0
T17	3489	0	0	0
T18	618	0	0	0
T19	27842	0	0	0
T20	28089	0	0	0
T22	0	14	0	0
T25	1557	0	0	0
T50	0	19	0	0
T143	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T3
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T4,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	461801242	3412	0	0
GateOpen_A	461801242	3412	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461801242	3412	0	0
T2	176718	78	0	0
T3	685832	33	0	0
T4	4385	1	0	0
T10	0	57	0	0
T11	0	47	0	0
T13	0	34	0	0
T14	0	34	0	0
T15	7653	0	0	0
T16	29749	0	0	0
T17	7002	0	0	0
T18	1314	0	0	0
T19	66364	0	0	0
T20	95159	0	0	0
T22	0	14	0	0
T25	2888	0	0	0
T50	0	25	0	0
T143	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461801242	3412	0	0
T2	176718	78	0	0
T3	685832	33	0	0
T4	4385	1	0	0
T10	0	57	0	0
T11	0	47	0	0
T13	0	34	0	0
T14	0	34	0	0
T15	7653	0	0	0
T16	29749	0	0	0
T17	7002	0	0	0
T18	1314	0	0	0
T19	66364	0	0	0
T20	95159	0	0	0
T22	0	14	0	0
T25	2888	0	0	0
T50	0	25	0	0
T143	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T3
0	1	Covered	T2,T3,T18
1	0	Covered	T1,T4,T2

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T3
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T4,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	236464267	3355	0	0
GateOpen_A	236464267	3355	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236464267	3355	0	0
T2	903504	82	0	0
T3	347540	35	0	0
T4	2193	1	0	0
T10	0	53	0	0
T11	0	49	0	0
T13	0	34	0	0
T14	0	34	0	0
T15	3826	0	0	0
T16	14876	0	0	0
T17	3501	0	0	0
T18	658	0	0	0
T19	33183	0	0	0
T20	47581	0	0	0
T22	0	15	0	0
T25	1444	0	0	0
T50	0	24	0	0
T143	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	236464267	3355	0	0
T2	903504	82	0	0
T3	347540	35	0	0
T4	2193	1	0	0
T10	0	53	0	0
T11	0	49	0	0
T13	0	34	0	0
T14	0	34	0	0
T15	3826	0	0	0
T16	14876	0	0	0
T17	3501	0	0	0
T18	658	0	0	0
T19	33183	0	0	0
T20	47581	0	0	0
T22	0	15	0	0
T25	1444	0	0	0
T50	0	24	0	0
T143	0	2	0	0