CLKMGR Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.760s 379.294us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.880s 43.824us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.000s 81.712us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 13.420s 3.008ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.160s 251.814us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.010s 370.172us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.000s 81.712us 20 20 100.00
clkmgr_csr_aliasing 2.160s 251.814us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.200s 172.279us 50 50 100.00
V2 trans_enables clkmgr_trans 1.760s 363.385us 50 50 100.00
V2 extclk clkmgr_extclk 1.160s 97.959us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.130s 169.637us 50 50 100.00
V2 jitter clkmgr_smoke 1.760s 379.294us 50 50 100.00
V2 frequency clkmgr_frequency 19.140s 2.477ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.550s 2.177ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.140s 2.477ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.177m 9.791ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.790s 47.703us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.010s 119.060us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.460s 560.394us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.460s 560.394us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.880s 43.824us 5 5 100.00
clkmgr_csr_rw 1.000s 81.712us 20 20 100.00
clkmgr_csr_aliasing 2.160s 251.814us 5 5 100.00
clkmgr_same_csr_outstanding 1.960s 211.664us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.880s 43.824us 5 5 100.00
clkmgr_csr_rw 1.000s 81.712us 20 20 100.00
clkmgr_csr_aliasing 2.160s 251.814us 5 5 100.00
clkmgr_same_csr_outstanding 1.960s 211.664us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.790s 390.013us 5 5 100.00
clkmgr_tl_intg_err 3.480s 705.878us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.590s 341.471us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.590s 341.471us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.590s 341.471us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.590s 341.471us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.990s 1.972ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.480s 705.878us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.140s 2.477ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.550s 2.177ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.590s 341.471us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.050s 432.383us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.280s 219.953us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.200s 185.756us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.730s 298.877us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.640s 332.854us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.000s 81.712us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.790s 390.013us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.000s 81.712us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.000s 81.712us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.790s 390.013us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.910s 1.117ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 42.306m 703.826ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results