CLKMGR Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.190s 144.680us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.930s 101.957us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.390s 239.817us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.770s 1.647ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.440s 273.044us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.010s 43.359us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.390s 239.817us 20 20 100.00
clkmgr_csr_aliasing 2.440s 273.044us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.070s 53.149us 50 50 100.00
V2 trans_enables clkmgr_trans 1.970s 384.754us 50 50 100.00
V2 extclk clkmgr_extclk 1.320s 179.722us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.100s 168.602us 50 50 100.00
V2 jitter clkmgr_smoke 1.190s 144.680us 50 50 100.00
V2 frequency clkmgr_frequency 17.020s 2.240ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.810s 2.414ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.020s 2.240ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.115m 9.837ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.890s 111.183us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.340s 218.120us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 8.140s 1.935ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 8.140s 1.935ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.930s 101.957us 5 5 100.00
clkmgr_csr_rw 1.390s 239.817us 20 20 100.00
clkmgr_csr_aliasing 2.440s 273.044us 5 5 100.00
clkmgr_same_csr_outstanding 1.590s 67.992us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.930s 101.957us 5 5 100.00
clkmgr_csr_rw 1.390s 239.817us 20 20 100.00
clkmgr_csr_aliasing 2.440s 273.044us 5 5 100.00
clkmgr_same_csr_outstanding 1.590s 67.992us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.350s 546.009us 5 5 100.00
clkmgr_tl_intg_err 3.630s 405.985us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.410s 346.156us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.410s 346.156us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.410s 346.156us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.410s 346.156us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.440s 1.675ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.630s 405.985us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.020s 2.240ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.810s 2.414ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.410s 346.156us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.480s 259.968us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.540s 282.253us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.260s 178.475us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.500s 234.501us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.340s 192.536us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.390s 239.817us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.350s 546.009us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.390s 239.817us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.390s 239.817us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.350s 546.009us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.470s 1.389ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 42.243m 697.316ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results