CLKMGR Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.520s 89.950us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 2.040s 168.317us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 2.470s 264.779us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.150s 712.055us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 3.380s 134.117us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.760s 82.310us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 2.470s 264.779us 20 20 100.00
clkmgr_csr_aliasing 3.380s 134.117us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 2.100s 166.064us 50 50 100.00
V2 trans_enables clkmgr_trans 2.490s 151.989us 50 50 100.00
V2 extclk clkmgr_extclk 2.790s 278.902us 50 50 100.00
V2 clk_status clkmgr_clk_status 2.050s 194.595us 50 50 100.00
V2 jitter clkmgr_smoke 1.520s 89.950us 50 50 100.00
V2 frequency clkmgr_frequency 32.910s 2.477ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 36.520s 2.422ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 32.910s 2.477ms 50 50 100.00
V2 stress_all clkmgr_stress_all 4.023m 18.576ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.280s 95.243us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.520s 61.189us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 7.000s 759.439us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 7.000s 759.439us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 2.040s 168.317us 5 5 100.00
clkmgr_csr_rw 2.470s 264.779us 20 20 100.00
clkmgr_csr_aliasing 3.380s 134.117us 5 5 100.00
clkmgr_same_csr_outstanding 4.060s 394.053us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 2.040s 168.317us 5 5 100.00
clkmgr_csr_rw 2.470s 264.779us 20 20 100.00
clkmgr_csr_aliasing 3.380s 134.117us 5 5 100.00
clkmgr_same_csr_outstanding 4.060s 394.053us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 8.120s 900.453us 5 5 100.00
clkmgr_tl_intg_err 7.680s 1.309ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 4.620s 360.390us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 4.620s 360.390us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 4.620s 360.390us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 4.620s 360.390us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.400s 547.655us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 7.680s 1.309ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 32.910s 2.477ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 36.520s 2.422ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 4.620s 360.390us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 3.040s 294.648us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 2.610s 323.945us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 3.530s 382.263us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.840s 301.825us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.190s 165.864us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 2.470s 264.779us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 8.120s 900.453us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 2.470s 264.779us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 2.470s 264.779us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 8.120s 900.453us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 14.530s 2.655ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 1.190h 805.311ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results