CLKMGR Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: 12e3b8572e

Branch: os_regression_2024_10_14

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 22.467s 49 50 98.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.200s 18.253us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.600s 109.696us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 30.260s 9.502ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.930s 71.303us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.540s 182.897us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.600s 109.696us 20 20 100.00
clkmgr_csr_aliasing 2.930s 71.303us 5 5 100.00
V1 TOTAL 104 105 99.05
V2 peri_enables clkmgr_peri 22.668s 49 50 98.00
V2 trans_enables clkmgr_trans 25.337s 48 50 96.00
V2 extclk clkmgr_extclk 23.852s 48 50 96.00
V2 clk_status clkmgr_clk_status 1.570s 128.314us 50 50 100.00
V2 jitter clkmgr_smoke 22.467s 49 50 98.00
V2 frequency clkmgr_frequency 28.520s 2.482ms 48 50 96.00
V2 frequency_timeout clkmgr_frequency_timeout 25.392s 48 50 96.00
V2 frequency_overflow clkmgr_frequency 28.520s 2.482ms 48 50 96.00
V2 stress_all clkmgr_stress_all 1.997m 12.361ms 48 50 96.00
V2 intr_test clkmgr_intr_test 1.500s 116.693us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.990s 130.292us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.810s 381.222us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.810s 381.222us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.200s 18.253us 5 5 100.00
clkmgr_csr_rw 1.600s 109.696us 20 20 100.00
clkmgr_csr_aliasing 2.930s 71.303us 5 5 100.00
clkmgr_same_csr_outstanding 2.260s 182.696us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.200s 18.253us 5 5 100.00
clkmgr_csr_rw 1.600s 109.696us 20 20 100.00
clkmgr_csr_aliasing 2.930s 71.303us 5 5 100.00
clkmgr_same_csr_outstanding 2.260s 182.696us 20 20 100.00
V2 TOTAL 479 490 97.76
V2S tl_intg_err clkmgr_sec_cm 6.070s 1.202ms 5 5 100.00
clkmgr_tl_intg_err 11.120s 2.081ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 4.030s 806.143us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 4.030s 806.143us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 4.030s 806.143us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 4.030s 806.143us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.800s 913.949us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 11.120s 2.081ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 28.520s 2.482ms 48 50 96.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 25.392s 48 50 96.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 4.030s 806.143us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 35.690s 48 50 96.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.730s 115.691us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 25.204s 49 50 98.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.360s 238.196us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 2.690s 290.520us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.600s 109.696us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 6.070s 1.202ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.600s 109.696us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.600s 109.696us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 6.070s 1.202ms 5 5 100.00
V2S TOTAL 312 315 99.05
V3 regwen clkmgr_regwen 32.612s 49 50 98.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 3.595m 60.584ms 49 50 98.00
V3 TOTAL 98 100 98.00
TOTAL 993 1010 98.32

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 11 11 5 45.45
V2S 9 9 7 77.78
V3 2 2 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.47 99.10 95.68 100.00 100.00 98.70 97.02 98.80

Failure Buckets

Past Results