Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	671250	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3943419

1

T4

98

T5

3

T6

42

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1130829	1			T4	10		T6	46		T24	15
values[0x0]	1603637	1			T4	107		T5	7		T6	31
values[0x1]	1880203	1			T4	104		T5	5		T6	27

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	369601	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4245068

1

T4

128

T5

3

T6

48

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17504	1			T5	1		T1	251		T2	1
valid_sources[0x01]	19047	1			T1	229		T18	1		T2	4
valid_sources[0x02]	17948	1			T1	103		T3	231		T7	1
valid_sources[0x03]	17742	1			T1	136		T3	272		T7	1
valid_sources[0x04]	18320	1			T1	155		T3	122		T7	3
valid_sources[0x05]	17418	1			T4	5		T1	141		T3	504
valid_sources[0x06]	19089	1			T1	267		T2	1		T3	521
valid_sources[0x07]	18512	1			T5	1		T1	90		T3	466
valid_sources[0x08]	17503	1			T1	159		T2	3		T3	288
valid_sources[0x09]	18733	1			T1	172		T3	401		T7	2
valid_sources[0x0a]	18211	1			T1	250		T3	355		T105	1
valid_sources[0x0b]	17920	1			T1	197		T2	1		T3	459
valid_sources[0x0c]	16944	1			T4	2		T1	148		T2	1
valid_sources[0x0d]	18081	1			T1	253		T3	191		T7	4
valid_sources[0x0e]	18024	1			T4	2		T27	1		T1	191
valid_sources[0x0f]	16707	1			T1	146		T2	4		T3	266
valid_sources[0x10]	16950	1			T1	195		T2	1		T3	218
valid_sources[0x11]	18139	1			T1	227		T2	1		T3	221
valid_sources[0x12]	17911	1			T1	141		T18	1		T3	176
valid_sources[0x13]	17316	1			T4	2		T26	2		T1	218
valid_sources[0x14]	17558	1			T28	28		T1	255		T3	446
valid_sources[0x15]	18159	1			T4	1		T1	119		T3	417
valid_sources[0x16]	18074	1			T1	154		T3	203		T105	7
valid_sources[0x17]	18970	1			T1	214		T2	4		T3	605
valid_sources[0x18]	19119	1			T1	251		T2	2		T3	491
valid_sources[0x19]	17163	1			T1	157		T3	130		T7	6
valid_sources[0x1a]	17479	1			T1	157		T3	105		T7	2
valid_sources[0x1b]	18447	1			T1	296		T2	3		T3	179
valid_sources[0x1c]	18515	1			T1	355		T2	9		T3	116
valid_sources[0x1d]	18040	1			T4	5		T1	116		T3	646
valid_sources[0x1e]	17292	1			T1	205		T3	664		T7	2
valid_sources[0x1f]	17429	1			T1	172		T2	2		T3	346
valid_sources[0x20]	18516	1			T1	219		T2	1		T3	418
valid_sources[0x21]	19185	1			T5	1		T1	289		T2	4
valid_sources[0x22]	17611	1			T1	193		T2	4		T3	176
valid_sources[0x23]	17240	1			T1	133		T18	1		T3	72
valid_sources[0x24]	17756	1			T1	127		T18	1		T3	446
valid_sources[0x25]	18739	1			T1	172		T2	1		T3	158
valid_sources[0x26]	18759	1			T26	2		T1	197		T18	1
valid_sources[0x27]	18399	1			T26	2		T1	187		T2	3
valid_sources[0x28]	17800	1			T1	150		T3	737		T7	3
valid_sources[0x29]	16962	1			T1	229		T2	2		T3	113
valid_sources[0x2a]	19029	1			T1	211		T3	230		T7	1
valid_sources[0x2b]	17441	1			T1	206		T2	1		T3	38
valid_sources[0x2c]	17523	1			T4	4		T1	198		T3	350
valid_sources[0x2d]	19864	1			T4	10		T1	190		T3	17
valid_sources[0x2e]	18243	1			T26	1		T1	158		T2	3
valid_sources[0x2f]	18500	1			T1	139		T18	1		T3	684
valid_sources[0x30]	17341	1			T1	205		T20	1		T3	56
valid_sources[0x31]	17668	1			T26	1		T1	242		T2	9
valid_sources[0x32]	17012	1			T1	82		T2	2		T3	226
valid_sources[0x33]	17736	1			T1	206		T2	3		T22	1
valid_sources[0x34]	18324	1			T1	204		T3	220		T7	5
valid_sources[0x35]	17210	1			T1	152		T2	3		T20	1
valid_sources[0x36]	17812	1			T1	136		T3	180		T7	3
valid_sources[0x37]	18800	1			T1	167		T2	1		T3	515
valid_sources[0x38]	17601	1			T1	195		T18	1		T3	502
valid_sources[0x39]	17702	1			T1	196		T3	118		T7	4
valid_sources[0x3a]	18567	1			T1	146		T2	1		T22	1
valid_sources[0x3b]	18337	1			T1	170		T2	1		T3	723
valid_sources[0x3c]	17542	1			T1	121		T18	1		T3	388
valid_sources[0x3d]	17461	1			T4	6		T26	2		T1	162
valid_sources[0x3e]	17626	1			T1	127		T2	3		T3	350
valid_sources[0x3f]	17431	1			T1	140		T2	2		T22	1
valid_sources[0x40]	17472	1			T4	11		T1	190		T2	1
valid_sources[0x41]	18927	1			T5	1		T1	228		T3	781
valid_sources[0x42]	18236	1			T1	203		T3	457		T7	3
valid_sources[0x43]	17152	1			T1	188		T2	5		T22	1
valid_sources[0x44]	17547	1			T1	253		T2	1		T3	47
valid_sources[0x45]	16939	1			T1	140		T3	451		T7	2
valid_sources[0x46]	17639	1			T27	2		T1	198		T3	254
valid_sources[0x47]	17854	1			T1	198		T3	284		T7	8
valid_sources[0x48]	16664	1			T1	220		T18	2		T2	2
valid_sources[0x49]	17364	1			T1	166		T3	130		T7	5
valid_sources[0x4a]	17872	1			T1	154		T3	517		T7	5
valid_sources[0x4b]	18293	1			T1	200		T18	1		T2	1
valid_sources[0x4c]	19545	1			T4	4		T1	183		T2	2
valid_sources[0x4d]	17158	1			T1	192		T3	490		T7	1
valid_sources[0x4e]	18586	1			T1	188		T2	2		T3	656
valid_sources[0x4f]	19016	1			T1	236		T18	1		T2	1
valid_sources[0x50]	19720	1			T1	252		T3	205		T7	4
valid_sources[0x51]	18850	1			T1	241		T2	1		T3	397
valid_sources[0x52]	18247	1			T1	227		T2	1		T3	431
valid_sources[0x53]	18338	1			T1	183		T2	4		T3	792
valid_sources[0x54]	18097	1			T4	6		T1	254		T2	1
valid_sources[0x55]	20200	1			T26	1		T1	187		T2	4
valid_sources[0x56]	17188	1			T1	143		T3	145		T7	1
valid_sources[0x57]	18406	1			T1	182		T2	1		T3	477
valid_sources[0x58]	17888	1			T4	1		T26	1		T1	260
valid_sources[0x59]	18021	1			T1	278		T2	1		T3	165
valid_sources[0x5a]	18000	1			T4	14		T1	106		T3	273
valid_sources[0x5b]	17650	1			T1	164		T2	1		T3	39
valid_sources[0x5c]	17183	1			T4	5		T1	113		T3	42
valid_sources[0x5d]	18149	1			T1	177		T17	7		T2	9
valid_sources[0x5e]	17463	1			T4	5		T27	1		T1	238
valid_sources[0x5f]	18255	1			T1	227		T2	3		T3	274
valid_sources[0x60]	18213	1			T1	203		T18	2		T2	5
valid_sources[0x61]	17879	1			T1	289		T18	1		T2	3
valid_sources[0x62]	18669	1			T1	142		T3	411		T7	1
valid_sources[0x63]	17590	1			T4	1		T1	121		T3	252
valid_sources[0x64]	18543	1			T4	3		T1	140		T3	781
valid_sources[0x65]	17838	1			T1	111		T3	89		T7	6
valid_sources[0x66]	17502	1			T1	147		T3	123		T7	6
valid_sources[0x67]	17708	1			T4	14		T1	150		T2	5
valid_sources[0x68]	16708	1			T1	167		T2	1		T3	162
valid_sources[0x69]	17815	1			T27	1		T1	207		T3	365
valid_sources[0x6a]	18631	1			T1	203		T3	401		T7	2
valid_sources[0x6b]	17717	1			T1	260		T2	2		T3	22
valid_sources[0x6c]	18703	1			T1	83		T3	326		T7	5
valid_sources[0x6d]	17714	1			T1	208		T2	1		T3	95
valid_sources[0x6e]	16473	1			T1	228		T2	2		T3	149
valid_sources[0x6f]	18148	1			T4	17		T1	313		T3	378
valid_sources[0x70]	17210	1			T1	253		T2	2		T3	273
valid_sources[0x71]	19129	1			T1	144		T3	197		T7	7
valid_sources[0x72]	19007	1			T4	5		T1	238		T2	1
valid_sources[0x73]	17582	1			T1	114		T3	356		T7	1
valid_sources[0x74]	17943	1			T27	1		T1	161		T2	3
valid_sources[0x75]	17475	1			T1	113		T3	348		T7	3
valid_sources[0x76]	16395	1			T1	200		T2	1		T22	1
valid_sources[0x77]	18230	1			T1	179		T3	33		T7	3
valid_sources[0x78]	17557	1			T4	3		T26	2		T1	161
valid_sources[0x79]	18824	1			T27	1		T1	166		T3	254
valid_sources[0x7a]	18374	1			T1	136		T2	1		T3	574
valid_sources[0x7b]	18617	1			T1	148		T2	3		T3	656
valid_sources[0x7c]	17319	1			T1	255		T2	1		T3	101
valid_sources[0x7d]	20082	1			T4	6		T1	257		T2	4
valid_sources[0x7e]	17808	1			T1	132		T20	1		T3	141
valid_sources[0x7f]	18819	1			T5	1		T1	147		T2	8
valid_sources[0x80]	18438	1			T1	157		T2	7		T3	351

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

994196

1

T4

6

T6

28

T24

3

values[0x0]

all_enables

biggest_size

1500512

1

T4

62

T5

2

T6

8

values[0x1]

all_enables

biggest_size

1448711

1

T4

30

T5

1

T6

6