Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.63	100.00	93.15	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	901930825	81813	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	901930825	81813	0	0
T1	991970	429	0	0
T2	452515	272	0	0
T3	1114310	2165	0	0
T10	0	40	0	0
T11	0	1310	0	0
T12	0	491	0	0
T13	0	183	0	0
T14	0	303	0	0
T15	0	100	0	0
T16	0	1497	0	0
T17	7360	0	0	0
T18	8780	0	0	0
T19	96535	0	0	0
T20	5090	0	0	0
T21	4930	0	0	0
T22	8995	0	0	0
T23	5715	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	180386165	11871	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	11871	0	0
T1	198394	65	0	0
T2	90503	38	0	0
T3	222862	286	0	0
T10	0	7	0	0
T11	0	173	0	0
T12	0	66	0	0
T13	0	27	0	0
T14	0	44	0	0
T15	0	16	0	0
T16	0	194	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	180386165	16473	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	16473	0	0
T1	198394	87	0	0
T2	90503	53	0	0
T3	222862	440	0	0
T10	0	8	0	0
T11	0	264	0	0
T12	0	98	0	0
T13	0	39	0	0
T14	0	60	0	0
T15	0	20	0	0
T16	0	305	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	180386165	25273	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	25273	0	0
T1	198394	127	0	0
T2	90503	82	0	0
T3	222862	724	0	0
T10	0	10	0	0
T11	0	436	0	0
T12	0	165	0	0
T13	0	59	0	0
T14	0	94	0	0
T15	0	28	0	0
T16	0	502	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	180386165	11724	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	11724	0	0
T1	198394	66	0	0
T2	90503	38	0	0
T3	222862	279	0	0
T10	0	7	0	0
T11	0	170	0	0
T12	0	63	0	0
T13	0	23	0	0
T14	0	44	0	0
T15	0	16	0	0
T16	0	192	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	180386165	16472	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	180386165	16472	0	0
T1	198394	84	0	0
T2	90503	61	0	0
T3	222862	436	0	0
T10	0	8	0	0
T11	0	267	0	0
T12	0	99	0	0
T13	0	35	0	0
T14	0	61	0	0
T15	0	20	0	0
T16	0	304	0	0
T17	1472	0	0	0
T18	1756	0	0	0
T19	19307	0	0	0
T20	1018	0	0	0
T21	986	0	0	0
T22	1799	0	0	0
T23	1143	0	0	0